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-rw-r--r--arch/mips/alchemy/common/reset.c188
1 files changed, 0 insertions, 188 deletions
diff --git a/arch/mips/alchemy/common/reset.c b/arch/mips/alchemy/common/reset.c
deleted file mode 100644
index 4791011e8f9..00000000000
--- a/arch/mips/alchemy/common/reset.c
+++ /dev/null
@@ -1,188 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Au1xx0 reset routines.
5 *
6 * Copyright 2001, 2006, 2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30#include <linux/gpio.h>
31
32#include <asm/cacheflush.h>
33#include <asm/mach-au1x00/au1000.h>
34
35void au1000_restart(char *command)
36{
37 /* Set all integrated peripherals to disabled states */
38 extern void board_reset(void);
39 u32 prid = read_c0_prid();
40
41 printk(KERN_NOTICE "\n** Resetting Integrated Peripherals\n");
42
43 switch (prid & 0xFF000000) {
44 case 0x00000000: /* Au1000 */
45 au_writel(0x02, 0xb0000010); /* ac97_enable */
46 au_writel(0x08, 0xb017fffc); /* usbh_enable - early errata */
47 asm("sync");
48 au_writel(0x00, 0xb017fffc); /* usbh_enable */
49 au_writel(0x00, 0xb0200058); /* usbd_enable */
50 au_writel(0x00, 0xb0300040); /* ir_enable */
51 au_writel(0x00, 0xb4004104); /* mac dma */
52 au_writel(0x00, 0xb4004114); /* mac dma */
53 au_writel(0x00, 0xb4004124); /* mac dma */
54 au_writel(0x00, 0xb4004134); /* mac dma */
55 au_writel(0x00, 0xb0520000); /* macen0 */
56 au_writel(0x00, 0xb0520004); /* macen1 */
57 au_writel(0x00, 0xb1000008); /* i2s_enable */
58 au_writel(0x00, 0xb1100100); /* uart0_enable */
59 au_writel(0x00, 0xb1200100); /* uart1_enable */
60 au_writel(0x00, 0xb1300100); /* uart2_enable */
61 au_writel(0x00, 0xb1400100); /* uart3_enable */
62 au_writel(0x02, 0xb1600100); /* ssi0_enable */
63 au_writel(0x02, 0xb1680100); /* ssi1_enable */
64 au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
65 au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
66 au_writel(0x00, 0xb1900028); /* sys_clksrc */
67 au_writel(0x10, 0xb1900060); /* sys_cpupll */
68 au_writel(0x00, 0xb1900064); /* sys_auxpll */
69 au_writel(0x00, 0xb1900100); /* sys_pininputen */
70 break;
71 case 0x01000000: /* Au1500 */
72 au_writel(0x02, 0xb0000010); /* ac97_enable */
73 au_writel(0x08, 0xb017fffc); /* usbh_enable - early errata */
74 asm("sync");
75 au_writel(0x00, 0xb017fffc); /* usbh_enable */
76 au_writel(0x00, 0xb0200058); /* usbd_enable */
77 au_writel(0x00, 0xb4004104); /* mac dma */
78 au_writel(0x00, 0xb4004114); /* mac dma */
79 au_writel(0x00, 0xb4004124); /* mac dma */
80 au_writel(0x00, 0xb4004134); /* mac dma */
81 au_writel(0x00, 0xb1520000); /* macen0 */
82 au_writel(0x00, 0xb1520004); /* macen1 */
83 au_writel(0x00, 0xb1100100); /* uart0_enable */
84 au_writel(0x00, 0xb1400100); /* uart3_enable */
85 au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
86 au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
87 au_writel(0x00, 0xb1900028); /* sys_clksrc */
88 au_writel(0x10, 0xb1900060); /* sys_cpupll */
89 au_writel(0x00, 0xb1900064); /* sys_auxpll */
90 au_writel(0x00, 0xb1900100); /* sys_pininputen */
91 break;
92 case 0x02000000: /* Au1100 */
93 au_writel(0x02, 0xb0000010); /* ac97_enable */
94 au_writel(0x08, 0xb017fffc); /* usbh_enable - early errata */
95 asm("sync");
96 au_writel(0x00, 0xb017fffc); /* usbh_enable */
97 au_writel(0x00, 0xb0200058); /* usbd_enable */
98 au_writel(0x00, 0xb0300040); /* ir_enable */
99 au_writel(0x00, 0xb4004104); /* mac dma */
100 au_writel(0x00, 0xb4004114); /* mac dma */
101 au_writel(0x00, 0xb4004124); /* mac dma */
102 au_writel(0x00, 0xb4004134); /* mac dma */
103 au_writel(0x00, 0xb0520000); /* macen0 */
104 au_writel(0x00, 0xb1000008); /* i2s_enable */
105 au_writel(0x00, 0xb1100100); /* uart0_enable */
106 au_writel(0x00, 0xb1200100); /* uart1_enable */
107 au_writel(0x00, 0xb1400100); /* uart3_enable */
108 au_writel(0x02, 0xb1600100); /* ssi0_enable */
109 au_writel(0x02, 0xb1680100); /* ssi1_enable */
110 au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
111 au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
112 au_writel(0x00, 0xb1900028); /* sys_clksrc */
113 au_writel(0x10, 0xb1900060); /* sys_cpupll */
114 au_writel(0x00, 0xb1900064); /* sys_auxpll */
115 au_writel(0x00, 0xb1900100); /* sys_pininputen */
116 break;
117 case 0x03000000: /* Au1550 */
118 au_writel(0x00, 0xb1a00004); /* psc 0 */
119 au_writel(0x00, 0xb1b00004); /* psc 1 */
120 au_writel(0x00, 0xb0a00004); /* psc 2 */
121 au_writel(0x00, 0xb0b00004); /* psc 3 */
122 au_writel(0x00, 0xb017fffc); /* usbh_enable */
123 au_writel(0x00, 0xb0200058); /* usbd_enable */
124 au_writel(0x00, 0xb4004104); /* mac dma */
125 au_writel(0x00, 0xb4004114); /* mac dma */
126 au_writel(0x00, 0xb4004124); /* mac dma */
127 au_writel(0x00, 0xb4004134); /* mac dma */
128 au_writel(0x00, 0xb1520000); /* macen0 */
129 au_writel(0x00, 0xb1520004); /* macen1 */
130 au_writel(0x00, 0xb1100100); /* uart0_enable */
131 au_writel(0x00, 0xb1200100); /* uart1_enable */
132 au_writel(0x00, 0xb1400100); /* uart3_enable */
133 au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
134 au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
135 au_writel(0x00, 0xb1900028); /* sys_clksrc */
136 au_writel(0x10, 0xb1900060); /* sys_cpupll */
137 au_writel(0x00, 0xb1900064); /* sys_auxpll */
138 au_writel(0x00, 0xb1900100); /* sys_pininputen */
139 break;
140 }
141
142 set_c0_status(ST0_BEV | ST0_ERL);
143 change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
144 flush_cache_all();
145 write_c0_wired(0);
146
147 /* Give board a chance to do a hardware reset */
148 board_reset();
149
150 /* Jump to the beggining in case board_reset() is empty */
151 __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
152}
153
154void au1000_halt(void)
155{
156#if defined(CONFIG_MIPS_PB1550) || defined(CONFIG_MIPS_DB1550)
157 /* Power off system */
158 printk(KERN_NOTICE "\n** Powering off...\n");
159 au_writew(au_readw(0xAF00001C) | (3 << 14), 0xAF00001C);
160 au_sync();
161 while (1); /* should not get here */
162#else
163 printk(KERN_NOTICE "\n** You can safely turn off the power\n");
164#ifdef CONFIG_MIPS_MIRAGE
165 gpio_direction_output(210, 1);
166#endif
167#ifdef CONFIG_MIPS_DB1200
168 au_writew(au_readw(0xB980001C) | (1 << 14), 0xB980001C);
169#endif
170#ifdef CONFIG_PM
171 au_sleep();
172
173 /* Should not get here */
174 printk(KERN_ERR "Unable to put CPU in sleep mode\n");
175 while (1);
176#else
177 while (1)
178 __asm__(".set\tmips3\n\t"
179 "wait\n\t"
180 ".set\tmips0");
181#endif
182#endif /* defined(CONFIG_MIPS_PB1550) || defined(CONFIG_MIPS_DB1550) */
183}
184
185void au1000_power_off(void)
186{
187 au1000_halt();
188}
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