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Diffstat (limited to 'arch/mips/alchemy/common/irq.c')
-rw-r--r--arch/mips/alchemy/common/irq.c290
1 files changed, 146 insertions, 144 deletions
diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c
index 8b5f00b3ad4..f5b148af8b8 100644
--- a/arch/mips/alchemy/common/irq.c
+++ b/arch/mips/alchemy/common/irq.c
@@ -53,160 +53,160 @@ struct au1xxx_irqmap {
53 int im_request; /* set 1 to get higher priority */ 53 int im_request; /* set 1 to get higher priority */
54} au1xxx_ic0_map[] __initdata = { 54} au1xxx_ic0_map[] __initdata = {
55#if defined(CONFIG_SOC_AU1000) 55#if defined(CONFIG_SOC_AU1000)
56 { AU1000_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 56 { AU1000_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
57 { AU1000_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 57 { AU1000_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
58 { AU1000_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 58 { AU1000_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
59 { AU1000_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 59 { AU1000_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
60 { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 60 { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
61 { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 61 { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
62 { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 }, 62 { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 },
63 { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 }, 63 { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 },
64 { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 }, 64 { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 },
65 { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 }, 65 { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 },
66 { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 }, 66 { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 },
67 { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 }, 67 { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 },
68 { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 }, 68 { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 },
69 { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 }, 69 { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 },
70 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, 70 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
71 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 71 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
72 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 72 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
73 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, 73 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
74 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 74 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
75 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 75 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
76 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 76 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
77 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, 77 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
78 { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 78 { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
79 { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 79 { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
80 { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, 80 { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 },
81 { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, 81 { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
82 { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, 82 { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
83 { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 83 { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 },
84 { AU1000_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 84 { AU1000_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
85 { AU1000_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 85 { AU1000_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
86 { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 }, 86 { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
87 87
88#elif defined(CONFIG_SOC_AU1500) 88#elif defined(CONFIG_SOC_AU1500)
89 89
90 { AU1500_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 90 { AU1500_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
91 { AU1000_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 }, 91 { AU1500_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 },
92 { AU1000_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 }, 92 { AU1500_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 },
93 { AU1500_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 93 { AU1500_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
94 { AU1000_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 }, 94 { AU1500_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 },
95 { AU1000_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 }, 95 { AU1500_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 },
96 { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 }, 96 { AU1500_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 },
97 { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 }, 97 { AU1500_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 },
98 { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 }, 98 { AU1500_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 },
99 { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 }, 99 { AU1500_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 },
100 { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 }, 100 { AU1500_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 },
101 { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 }, 101 { AU1500_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 },
102 { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 }, 102 { AU1500_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 },
103 { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 }, 103 { AU1500_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 },
104 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, 104 { AU1500_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
105 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 105 { AU1500_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
106 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 106 { AU1500_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
107 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, 107 { AU1500_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
108 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 108 { AU1500_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
109 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 109 { AU1500_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
110 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 110 { AU1500_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
111 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, 111 { AU1500_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
112 { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, 112 { AU1500_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 },
113 { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, 113 { AU1500_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
114 { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, 114 { AU1500_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
115 { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 115 { AU1500_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 },
116 { AU1500_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 116 { AU1500_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
117 { AU1500_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 117 { AU1500_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
118 { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 }, 118 { AU1500_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
119 119
120#elif defined(CONFIG_SOC_AU1100) 120#elif defined(CONFIG_SOC_AU1100)
121 121
122 { AU1100_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 122 { AU1100_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
123 { AU1100_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 123 { AU1100_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
124 { AU1100_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 124 { AU1100_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
125 { AU1100_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 125 { AU1100_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
126 { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 126 { AU1100_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
127 { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 127 { AU1100_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
128 { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 }, 128 { AU1100_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 },
129 { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 }, 129 { AU1100_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 },
130 { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 }, 130 { AU1100_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 },
131 { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 }, 131 { AU1100_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 },
132 { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 }, 132 { AU1100_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 },
133 { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 }, 133 { AU1100_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 },
134 { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 }, 134 { AU1100_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 },
135 { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 }, 135 { AU1100_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 },
136 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, 136 { AU1100_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
137 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 137 { AU1100_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
138 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 138 { AU1100_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
139 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, 139 { AU1100_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
140 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 140 { AU1100_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
141 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 141 { AU1100_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
142 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 142 { AU1100_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
143 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, 143 { AU1100_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
144 { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 144 { AU1100_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
145 { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 145 { AU1100_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
146 { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, 146 { AU1100_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 },
147 { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, 147 { AU1100_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
148 { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, 148 { AU1100_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
149 { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 149 { AU1100_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 },
150 { AU1100_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 150 { AU1100_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
151 { AU1100_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 151 { AU1100_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
152 { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 }, 152 { AU1100_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
153 153
154#elif defined(CONFIG_SOC_AU1550) 154#elif defined(CONFIG_SOC_AU1550)
155 155
156 { AU1550_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 156 { AU1550_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
157 { AU1550_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 }, 157 { AU1550_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 },
158 { AU1550_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 }, 158 { AU1550_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 },
159 { AU1550_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 159 { AU1550_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
160 { AU1550_CRYPTO_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 160 { AU1550_CRYPTO_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
161 { AU1550_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 }, 161 { AU1550_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 },
162 { AU1550_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 }, 162 { AU1550_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 },
163 { AU1550_PCI_RST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, 163 { AU1550_PCI_RST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
164 { AU1550_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 164 { AU1550_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
165 { AU1550_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 165 { AU1550_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
166 { AU1550_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 166 { AU1550_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
167 { AU1550_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 167 { AU1550_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
168 { AU1550_PSC2_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 168 { AU1550_PSC2_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
169 { AU1550_PSC3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 169 { AU1550_PSC3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
170 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, 170 { AU1550_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
171 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 171 { AU1550_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
172 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 172 { AU1550_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
173 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, 173 { AU1550_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
174 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 174 { AU1550_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
175 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 175 { AU1550_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
176 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 176 { AU1550_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
177 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, 177 { AU1550_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
178 { AU1550_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 }, 178 { AU1550_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 },
179 { AU1550_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, 179 { AU1550_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 },
180 { AU1550_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, 180 { AU1550_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
181 { AU1550_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, 181 { AU1550_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
182 { AU1550_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 182 { AU1550_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
183 { AU1550_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 183 { AU1550_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
184 184
185#elif defined(CONFIG_SOC_AU1200) 185#elif defined(CONFIG_SOC_AU1200)
186 186
187 { AU1200_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 187 { AU1200_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
188 { AU1200_SWT_INT, IRQ_TYPE_EDGE_RISING, 0 }, 188 { AU1200_SWT_INT, IRQ_TYPE_EDGE_RISING, 0 },
189 { AU1200_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 189 { AU1200_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
190 { AU1200_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 190 { AU1200_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
191 { AU1200_MAE_BE_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 191 { AU1200_MAE_BE_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
192 { AU1200_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 192 { AU1200_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
193 { AU1200_MAE_FE_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 193 { AU1200_MAE_FE_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
194 { AU1200_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 194 { AU1200_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
195 { AU1200_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 195 { AU1200_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
196 { AU1200_AES_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 196 { AU1200_AES_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
197 { AU1200_CAMERA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 197 { AU1200_CAMERA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
198 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, 198 { AU1200_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
199 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 199 { AU1200_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
200 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 200 { AU1200_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
201 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, 201 { AU1200_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
202 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 202 { AU1200_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
203 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 203 { AU1200_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
204 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 204 { AU1200_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
205 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, 205 { AU1200_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
206 { AU1200_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 }, 206 { AU1200_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 },
207 { AU1200_USB_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 207 { AU1200_USB_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
208 { AU1200_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 208 { AU1200_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
209 { AU1200_MAE_BOTH_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 209 { AU1200_MAE_BOTH_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
210 210
211#else 211#else
212#error "Error: Unknown Alchemy SOC" 212#error "Error: Unknown Alchemy SOC"
@@ -316,7 +316,7 @@ static void au1x_ic1_unmask(unsigned int irq_nr)
316 * nowhere in the current kernel sources is it disabled. --mlau 316 * nowhere in the current kernel sources is it disabled. --mlau
317 */ 317 */
318#if defined(CONFIG_MIPS_PB1000) 318#if defined(CONFIG_MIPS_PB1000)
319 if (irq_nr == AU1000_GPIO_15) 319 if (irq_nr == AU1000_GPIO15_INT)
320 au_writel(0x4000, PB1000_MDR); /* enable int */ 320 au_writel(0x4000, PB1000_MDR); /* enable int */
321#endif 321#endif
322 au_sync(); 322 au_sync();
@@ -388,11 +388,13 @@ static void au1x_ic1_maskack(unsigned int irq_nr)
388 388
389static int au1x_ic1_setwake(unsigned int irq, unsigned int on) 389static int au1x_ic1_setwake(unsigned int irq, unsigned int on)
390{ 390{
391 unsigned int bit = irq - AU1000_INTC1_INT_BASE; 391 int bit = irq - AU1000_INTC1_INT_BASE;
392 unsigned long wakemsk, flags; 392 unsigned long wakemsk, flags;
393 393
394 /* only GPIO 0-7 can act as wakeup source: */ 394 /* only GPIO 0-7 can act as wakeup source. Fortunately these
395 if ((irq < AU1000_GPIO_0) || (irq > AU1000_GPIO_7)) 395 * are wired up identically on all supported variants.
396 */
397 if ((bit < 0) || (bit > 7))
396 return -EINVAL; 398 return -EINVAL;
397 399
398 local_irq_save(flags); 400 local_irq_save(flags);
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-11 19:22:55 -0400