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Diffstat (limited to 'arch/m32r/platforms/mappi3/setup.c')
-rw-r--r--arch/m32r/platforms/mappi3/setup.c20
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/m32r/platforms/mappi3/setup.c b/arch/m32r/platforms/mappi3/setup.c
index b44f5ded2bb..2408e356ad1 100644
--- a/arch/m32r/platforms/mappi3/setup.c
+++ b/arch/m32r/platforms/mappi3/setup.c
@@ -75,38 +75,38 @@ void __init init_IRQ(void)
75{ 75{
76#if defined(CONFIG_SMC91X) 76#if defined(CONFIG_SMC91X)
77 /* INT0 : LAN controller (SMC91111) */ 77 /* INT0 : LAN controller (SMC91111) */
78 set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi3_irq_type, 78 irq_set_chip_and_handler(M32R_IRQ_INT0, &mappi3_irq_type,
79 handle_level_irq); 79 handle_level_irq);
80 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 80 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
81 disable_mappi3_irq(M32R_IRQ_INT0); 81 disable_mappi3_irq(M32R_IRQ_INT0);
82#endif /* CONFIG_SMC91X */ 82#endif /* CONFIG_SMC91X */
83 83
84 /* MFT2 : system timer */ 84 /* MFT2 : system timer */
85 set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi3_irq_type, 85 irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi3_irq_type,
86 handle_level_irq); 86 handle_level_irq);
87 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 87 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
88 disable_mappi3_irq(M32R_IRQ_MFT2); 88 disable_mappi3_irq(M32R_IRQ_MFT2);
89 89
90#ifdef CONFIG_SERIAL_M32R_SIO 90#ifdef CONFIG_SERIAL_M32R_SIO
91 /* SIO0_R : uart receive data */ 91 /* SIO0_R : uart receive data */
92 set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi3_irq_type, 92 irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi3_irq_type,
93 handle_level_irq); 93 handle_level_irq);
94 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 94 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
95 disable_mappi3_irq(M32R_IRQ_SIO0_R); 95 disable_mappi3_irq(M32R_IRQ_SIO0_R);
96 96
97 /* SIO0_S : uart send data */ 97 /* SIO0_S : uart send data */
98 set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi3_irq_type, 98 irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi3_irq_type,
99 handle_level_irq); 99 handle_level_irq);
100 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 100 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
101 disable_mappi3_irq(M32R_IRQ_SIO0_S); 101 disable_mappi3_irq(M32R_IRQ_SIO0_S);
102 /* SIO1_R : uart receive data */ 102 /* SIO1_R : uart receive data */
103 set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi3_irq_type, 103 irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi3_irq_type,
104 handle_level_irq); 104 handle_level_irq);
105 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 105 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
106 disable_mappi3_irq(M32R_IRQ_SIO1_R); 106 disable_mappi3_irq(M32R_IRQ_SIO1_R);
107 107
108 /* SIO1_S : uart send data */ 108 /* SIO1_S : uart send data */
109 set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi3_irq_type, 109 irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi3_irq_type,
110 handle_level_irq); 110 handle_level_irq);
111 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 111 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
112 disable_mappi3_irq(M32R_IRQ_SIO1_S); 112 disable_mappi3_irq(M32R_IRQ_SIO1_S);
@@ -114,21 +114,21 @@ void __init init_IRQ(void)
114 114
115#if defined(CONFIG_USB) 115#if defined(CONFIG_USB)
116 /* INT1 : USB Host controller interrupt */ 116 /* INT1 : USB Host controller interrupt */
117 set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi3_irq_type, 117 irq_set_chip_and_handler(M32R_IRQ_INT1, &mappi3_irq_type,
118 handle_level_irq); 118 handle_level_irq);
119 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; 119 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01;
120 disable_mappi3_irq(M32R_IRQ_INT1); 120 disable_mappi3_irq(M32R_IRQ_INT1);
121#endif /* CONFIG_USB */ 121#endif /* CONFIG_USB */
122 122
123 /* CFC IREQ */ 123 /* CFC IREQ */
124 set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &mappi3_irq_type, 124 irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &mappi3_irq_type,
125 handle_level_irq); 125 handle_level_irq);
126 icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; 126 icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
127 disable_mappi3_irq(PLD_IRQ_CFIREQ); 127 disable_mappi3_irq(PLD_IRQ_CFIREQ);
128 128
129#if defined(CONFIG_M32R_CFC) 129#if defined(CONFIG_M32R_CFC)
130 /* ICUCR41: CFC Insert & eject */ 130 /* ICUCR41: CFC Insert & eject */
131 set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi3_irq_type, 131 irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi3_irq_type,
132 handle_level_irq); 132 handle_level_irq);
133 icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; 133 icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00;
134 disable_mappi3_irq(PLD_IRQ_CFC_INSERT); 134 disable_mappi3_irq(PLD_IRQ_CFC_INSERT);
@@ -136,7 +136,7 @@ void __init init_IRQ(void)
136#endif /* CONFIG_M32R_CFC */ 136#endif /* CONFIG_M32R_CFC */
137 137
138 /* IDE IREQ */ 138 /* IDE IREQ */
139 set_irq_chip_and_handler(PLD_IRQ_IDEIREQ, &mappi3_irq_type, 139 irq_set_chip_and_handler(PLD_IRQ_IDEIREQ, &mappi3_irq_type,
140 handle_level_irq); 140 handle_level_irq);
141 icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 141 icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
142 disable_mappi3_irq(PLD_IRQ_IDEIREQ); 142 disable_mappi3_irq(PLD_IRQ_IDEIREQ);