diff options
Diffstat (limited to 'arch/blackfin/mach-bf548/include/mach/defBF54x_base.h')
| -rw-r--r-- | arch/blackfin/mach-bf548/include/mach/defBF54x_base.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h index 54143441af5..01d52fade45 100644 --- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h +++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h | |||
| @@ -105,15 +105,15 @@ | |||
| 105 | #define TWI0_REGBASE 0xffc00700 | 105 | #define TWI0_REGBASE 0xffc00700 |
| 106 | #define TWI0_CLKDIV 0xffc00700 /* Clock Divider Register */ | 106 | #define TWI0_CLKDIV 0xffc00700 /* Clock Divider Register */ |
| 107 | #define TWI0_CONTROL 0xffc00704 /* TWI Control Register */ | 107 | #define TWI0_CONTROL 0xffc00704 /* TWI Control Register */ |
| 108 | #define TWI0_SLAVE_CTRL 0xffc00708 /* TWI Slave Mode Control Register */ | 108 | #define TWI0_SLAVE_CTL 0xffc00708 /* TWI Slave Mode Control Register */ |
| 109 | #define TWI0_SLAVE_STAT 0xffc0070c /* TWI Slave Mode Status Register */ | 109 | #define TWI0_SLAVE_STAT 0xffc0070c /* TWI Slave Mode Status Register */ |
| 110 | #define TWI0_SLAVE_ADDR 0xffc00710 /* TWI Slave Mode Address Register */ | 110 | #define TWI0_SLAVE_ADDR 0xffc00710 /* TWI Slave Mode Address Register */ |
| 111 | #define TWI0_MASTER_CTRL 0xffc00714 /* TWI Master Mode Control Register */ | 111 | #define TWI0_MASTER_CTL 0xffc00714 /* TWI Master Mode Control Register */ |
| 112 | #define TWI0_MASTER_STAT 0xffc00718 /* TWI Master Mode Status Register */ | 112 | #define TWI0_MASTER_STAT 0xffc00718 /* TWI Master Mode Status Register */ |
| 113 | #define TWI0_MASTER_ADDR 0xffc0071c /* TWI Master Mode Address Register */ | 113 | #define TWI0_MASTER_ADDR 0xffc0071c /* TWI Master Mode Address Register */ |
| 114 | #define TWI0_INT_STAT 0xffc00720 /* TWI Interrupt Status Register */ | 114 | #define TWI0_INT_STAT 0xffc00720 /* TWI Interrupt Status Register */ |
| 115 | #define TWI0_INT_MASK 0xffc00724 /* TWI Interrupt Mask Register */ | 115 | #define TWI0_INT_MASK 0xffc00724 /* TWI Interrupt Mask Register */ |
| 116 | #define TWI0_FIFO_CTRL 0xffc00728 /* TWI FIFO Control Register */ | 116 | #define TWI0_FIFO_CTL 0xffc00728 /* TWI FIFO Control Register */ |
| 117 | #define TWI0_FIFO_STAT 0xffc0072c /* TWI FIFO Status Register */ | 117 | #define TWI0_FIFO_STAT 0xffc0072c /* TWI FIFO Status Register */ |
| 118 | #define TWI0_XMT_DATA8 0xffc00780 /* TWI FIFO Transmit Data Single Byte Register */ | 118 | #define TWI0_XMT_DATA8 0xffc00780 /* TWI FIFO Transmit Data Single Byte Register */ |
| 119 | #define TWI0_XMT_DATA16 0xffc00784 /* TWI FIFO Transmit Data Double Byte Register */ | 119 | #define TWI0_XMT_DATA16 0xffc00784 /* TWI FIFO Transmit Data Double Byte Register */ |