diff options
Diffstat (limited to 'arch/blackfin/mach-bf548/include/mach/defBF544.h')
| -rw-r--r-- | arch/blackfin/mach-bf548/include/mach/defBF544.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF544.h b/arch/blackfin/mach-bf548/include/mach/defBF544.h index f916c52a148..e2771094de0 100644 --- a/arch/blackfin/mach-bf548/include/mach/defBF544.h +++ b/arch/blackfin/mach-bf548/include/mach/defBF544.h | |||
| @@ -60,15 +60,15 @@ | |||
| 60 | #define TWI1_REGBASE 0xffc02200 | 60 | #define TWI1_REGBASE 0xffc02200 |
| 61 | #define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ | 61 | #define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ |
| 62 | #define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ | 62 | #define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ |
| 63 | #define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */ | 63 | #define TWI1_SLAVE_CTL 0xffc02208 /* TWI Slave Mode Control Register */ |
| 64 | #define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */ | 64 | #define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */ |
| 65 | #define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */ | 65 | #define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */ |
| 66 | #define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */ | 66 | #define TWI1_MASTER_CTL 0xffc02214 /* TWI Master Mode Control Register */ |
| 67 | #define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */ | 67 | #define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */ |
| 68 | #define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */ | 68 | #define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */ |
| 69 | #define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */ | 69 | #define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */ |
| 70 | #define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */ | 70 | #define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */ |
| 71 | #define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */ | 71 | #define TWI1_FIFO_CTL 0xffc02228 /* TWI FIFO Control Register */ |
| 72 | #define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */ | 72 | #define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */ |
| 73 | #define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */ | 73 | #define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */ |
| 74 | #define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */ | 74 | #define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */ |