diff options
Diffstat (limited to 'arch/blackfin/mach-bf533/include/mach/defBF532.h')
| -rw-r--r-- | arch/blackfin/mach-bf533/include/mach/defBF532.h | 77 |
1 files changed, 0 insertions, 77 deletions
diff --git a/arch/blackfin/mach-bf533/include/mach/defBF532.h b/arch/blackfin/mach-bf533/include/mach/defBF532.h index 3adb0b44e59..8e8099b567f 100644 --- a/arch/blackfin/mach-bf533/include/mach/defBF532.h +++ b/arch/blackfin/mach-bf533/include/mach/defBF532.h | |||
| @@ -432,83 +432,6 @@ | |||
| 432 | #define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ | 432 | #define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ |
| 433 | #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ | 433 | #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ |
| 434 | 434 | ||
| 435 | /* ***************************** UART CONTROLLER MASKS ********************** */ | ||
| 436 | |||
| 437 | /* UART_LCR Register */ | ||
| 438 | |||
| 439 | #define DLAB 0x80 | ||
| 440 | #define SB 0x40 | ||
| 441 | #define STP 0x20 | ||
| 442 | #define EPS 0x10 | ||
| 443 | #define PEN 0x08 | ||
| 444 | #define STB 0x04 | ||
| 445 | #define WLS(x) ((x-5) & 0x03) | ||
| 446 | |||
| 447 | #define DLAB_P 0x07 | ||
| 448 | #define SB_P 0x06 | ||
| 449 | #define STP_P 0x05 | ||
| 450 | #define EPS_P 0x04 | ||
| 451 | #define PEN_P 0x03 | ||
| 452 | #define STB_P 0x02 | ||
| 453 | #define WLS_P1 0x01 | ||
| 454 | #define WLS_P0 0x00 | ||
| 455 | |||
| 456 | /* UART_MCR Register */ | ||
| 457 | #define LOOP_ENA 0x10 | ||
| 458 | #define LOOP_ENA_P 0x04 | ||
| 459 | |||
| 460 | /* UART_LSR Register */ | ||
| 461 | #define TEMT 0x40 | ||
| 462 | #define THRE 0x20 | ||
| 463 | #define BI 0x10 | ||
| 464 | #define FE 0x08 | ||
| 465 | #define PE 0x04 | ||
| 466 | #define OE 0x02 | ||
| 467 | #define DR 0x01 | ||
| 468 | |||
| 469 | #define TEMP_P 0x06 | ||
| 470 | #define THRE_P 0x05 | ||
| 471 | #define BI_P 0x04 | ||
| 472 | #define FE_P 0x03 | ||
| 473 | #define PE_P 0x02 | ||
| 474 | #define OE_P 0x01 | ||
| 475 | #define DR_P 0x00 | ||
| 476 | |||
| 477 | /* UART_IER Register */ | ||
| 478 | #define ELSI 0x04 | ||
| 479 | #define ETBEI 0x02 | ||
| 480 | #define ERBFI 0x01 | ||
| 481 | |||
| 482 | #define ELSI_P 0x02 | ||
| 483 | #define ETBEI_P 0x01 | ||
| 484 | #define ERBFI_P 0x00 | ||
| 485 | |||
| 486 | /* UART_IIR Register */ | ||
| 487 | #define STATUS(x) ((x << 1) & 0x06) | ||
| 488 | #define NINT 0x01 | ||
| 489 | #define STATUS_P1 0x02 | ||
| 490 | #define STATUS_P0 0x01 | ||
| 491 | #define NINT_P 0x00 | ||
| 492 | #define IIR_TX_READY 0x02 /* UART_THR empty */ | ||
| 493 | #define IIR_RX_READY 0x04 /* Receive data ready */ | ||
| 494 | #define IIR_LINE_CHANGE 0x06 /* Receive line status */ | ||
| 495 | #define IIR_STATUS 0x06 | ||
| 496 | |||
| 497 | /* UART_GCTL Register */ | ||
| 498 | #define FFE 0x20 | ||
| 499 | #define FPE 0x10 | ||
| 500 | #define RPOLC 0x08 | ||
| 501 | #define TPOLC 0x04 | ||
| 502 | #define IREN 0x02 | ||
| 503 | #define UCEN 0x01 | ||
| 504 | |||
| 505 | #define FFE_P 0x05 | ||
| 506 | #define FPE_P 0x04 | ||
| 507 | #define RPOLC_P 0x03 | ||
| 508 | #define TPOLC_P 0x02 | ||
| 509 | #define IREN_P 0x01 | ||
| 510 | #define UCEN_P 0x00 | ||
| 511 | |||
| 512 | /* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */ | 435 | /* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */ |
| 513 | 436 | ||
| 514 | /* PPI_CONTROL Masks */ | 437 | /* PPI_CONTROL Masks */ |
