diff options
Diffstat (limited to 'arch/arm/mach-shmobile/setup-sh73a0.c')
-rw-r--r-- | arch/arm/mach-shmobile/setup-sh73a0.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index f1eff8b37bd..685c40a2f5e 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c | |||
@@ -36,6 +36,8 @@ | |||
36 | static struct plat_sci_port scif0_platform_data = { | 36 | static struct plat_sci_port scif0_platform_data = { |
37 | .mapbase = 0xe6c40000, | 37 | .mapbase = 0xe6c40000, |
38 | .flags = UPF_BOOT_AUTOCONF, | 38 | .flags = UPF_BOOT_AUTOCONF, |
39 | .scscr = SCSCR_RE | SCSCR_TE, | ||
40 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
39 | .type = PORT_SCIFA, | 41 | .type = PORT_SCIFA, |
40 | .irqs = { gic_spi(72), gic_spi(72), | 42 | .irqs = { gic_spi(72), gic_spi(72), |
41 | gic_spi(72), gic_spi(72) }, | 43 | gic_spi(72), gic_spi(72) }, |
@@ -52,6 +54,8 @@ static struct platform_device scif0_device = { | |||
52 | static struct plat_sci_port scif1_platform_data = { | 54 | static struct plat_sci_port scif1_platform_data = { |
53 | .mapbase = 0xe6c50000, | 55 | .mapbase = 0xe6c50000, |
54 | .flags = UPF_BOOT_AUTOCONF, | 56 | .flags = UPF_BOOT_AUTOCONF, |
57 | .scscr = SCSCR_RE | SCSCR_TE, | ||
58 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
55 | .type = PORT_SCIFA, | 59 | .type = PORT_SCIFA, |
56 | .irqs = { gic_spi(73), gic_spi(73), | 60 | .irqs = { gic_spi(73), gic_spi(73), |
57 | gic_spi(73), gic_spi(73) }, | 61 | gic_spi(73), gic_spi(73) }, |
@@ -68,6 +72,8 @@ static struct platform_device scif1_device = { | |||
68 | static struct plat_sci_port scif2_platform_data = { | 72 | static struct plat_sci_port scif2_platform_data = { |
69 | .mapbase = 0xe6c60000, | 73 | .mapbase = 0xe6c60000, |
70 | .flags = UPF_BOOT_AUTOCONF, | 74 | .flags = UPF_BOOT_AUTOCONF, |
75 | .scscr = SCSCR_RE | SCSCR_TE, | ||
76 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
71 | .type = PORT_SCIFA, | 77 | .type = PORT_SCIFA, |
72 | .irqs = { gic_spi(74), gic_spi(74), | 78 | .irqs = { gic_spi(74), gic_spi(74), |
73 | gic_spi(74), gic_spi(74) }, | 79 | gic_spi(74), gic_spi(74) }, |
@@ -84,6 +90,8 @@ static struct platform_device scif2_device = { | |||
84 | static struct plat_sci_port scif3_platform_data = { | 90 | static struct plat_sci_port scif3_platform_data = { |
85 | .mapbase = 0xe6c70000, | 91 | .mapbase = 0xe6c70000, |
86 | .flags = UPF_BOOT_AUTOCONF, | 92 | .flags = UPF_BOOT_AUTOCONF, |
93 | .scscr = SCSCR_RE | SCSCR_TE, | ||
94 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
87 | .type = PORT_SCIFA, | 95 | .type = PORT_SCIFA, |
88 | .irqs = { gic_spi(75), gic_spi(75), | 96 | .irqs = { gic_spi(75), gic_spi(75), |
89 | gic_spi(75), gic_spi(75) }, | 97 | gic_spi(75), gic_spi(75) }, |
@@ -100,6 +108,8 @@ static struct platform_device scif3_device = { | |||
100 | static struct plat_sci_port scif4_platform_data = { | 108 | static struct plat_sci_port scif4_platform_data = { |
101 | .mapbase = 0xe6c80000, | 109 | .mapbase = 0xe6c80000, |
102 | .flags = UPF_BOOT_AUTOCONF, | 110 | .flags = UPF_BOOT_AUTOCONF, |
111 | .scscr = SCSCR_RE | SCSCR_TE, | ||
112 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
103 | .type = PORT_SCIFA, | 113 | .type = PORT_SCIFA, |
104 | .irqs = { gic_spi(78), gic_spi(78), | 114 | .irqs = { gic_spi(78), gic_spi(78), |
105 | gic_spi(78), gic_spi(78) }, | 115 | gic_spi(78), gic_spi(78) }, |
@@ -116,6 +126,8 @@ static struct platform_device scif4_device = { | |||
116 | static struct plat_sci_port scif5_platform_data = { | 126 | static struct plat_sci_port scif5_platform_data = { |
117 | .mapbase = 0xe6cb0000, | 127 | .mapbase = 0xe6cb0000, |
118 | .flags = UPF_BOOT_AUTOCONF, | 128 | .flags = UPF_BOOT_AUTOCONF, |
129 | .scscr = SCSCR_RE | SCSCR_TE, | ||
130 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
119 | .type = PORT_SCIFA, | 131 | .type = PORT_SCIFA, |
120 | .irqs = { gic_spi(79), gic_spi(79), | 132 | .irqs = { gic_spi(79), gic_spi(79), |
121 | gic_spi(79), gic_spi(79) }, | 133 | gic_spi(79), gic_spi(79) }, |
@@ -132,6 +144,8 @@ static struct platform_device scif5_device = { | |||
132 | static struct plat_sci_port scif6_platform_data = { | 144 | static struct plat_sci_port scif6_platform_data = { |
133 | .mapbase = 0xe6cc0000, | 145 | .mapbase = 0xe6cc0000, |
134 | .flags = UPF_BOOT_AUTOCONF, | 146 | .flags = UPF_BOOT_AUTOCONF, |
147 | .scscr = SCSCR_RE | SCSCR_TE, | ||
148 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
135 | .type = PORT_SCIFA, | 149 | .type = PORT_SCIFA, |
136 | .irqs = { gic_spi(156), gic_spi(156), | 150 | .irqs = { gic_spi(156), gic_spi(156), |
137 | gic_spi(156), gic_spi(156) }, | 151 | gic_spi(156), gic_spi(156) }, |
@@ -148,6 +162,8 @@ static struct platform_device scif6_device = { | |||
148 | static struct plat_sci_port scif7_platform_data = { | 162 | static struct plat_sci_port scif7_platform_data = { |
149 | .mapbase = 0xe6cd0000, | 163 | .mapbase = 0xe6cd0000, |
150 | .flags = UPF_BOOT_AUTOCONF, | 164 | .flags = UPF_BOOT_AUTOCONF, |
165 | .scscr = SCSCR_RE | SCSCR_TE, | ||
166 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
151 | .type = PORT_SCIFA, | 167 | .type = PORT_SCIFA, |
152 | .irqs = { gic_spi(143), gic_spi(143), | 168 | .irqs = { gic_spi(143), gic_spi(143), |
153 | gic_spi(143), gic_spi(143) }, | 169 | gic_spi(143), gic_spi(143) }, |
@@ -164,6 +180,8 @@ static struct platform_device scif7_device = { | |||
164 | static struct plat_sci_port scif8_platform_data = { | 180 | static struct plat_sci_port scif8_platform_data = { |
165 | .mapbase = 0xe6c30000, | 181 | .mapbase = 0xe6c30000, |
166 | .flags = UPF_BOOT_AUTOCONF, | 182 | .flags = UPF_BOOT_AUTOCONF, |
183 | .scscr = SCSCR_RE | SCSCR_TE, | ||
184 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
167 | .type = PORT_SCIFB, | 185 | .type = PORT_SCIFB, |
168 | .irqs = { gic_spi(80), gic_spi(80), | 186 | .irqs = { gic_spi(80), gic_spi(80), |
169 | gic_spi(80), gic_spi(80) }, | 187 | gic_spi(80), gic_spi(80) }, |