diff options
| -rw-r--r-- | arch/arm/mm/proc-macros.S | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S index 7d63beaf974..321555b894d 100644 --- a/arch/arm/mm/proc-macros.S +++ b/arch/arm/mm/proc-macros.S | |||
| @@ -61,14 +61,14 @@ | |||
| 61 | .endm | 61 | .endm |
| 62 | 62 | ||
| 63 | /* | 63 | /* |
| 64 | * cache_line_size - get the cache line size from the CSIDR register | 64 | * dcache_line_size - get the minimum D-cache line size from the CTR register |
| 65 | * (available on ARMv7+). It assumes that the CSSR register was configured | 65 | * on ARMv7. |
| 66 | * to access the L1 data cache CSIDR. | ||
| 67 | */ | 66 | */ |
| 68 | .macro dcache_line_size, reg, tmp | 67 | .macro dcache_line_size, reg, tmp |
| 69 | mrc p15, 1, \tmp, c0, c0, 0 @ read CSIDR | 68 | mrc p15, 0, \tmp, c0, c0, 1 @ read ctr |
| 70 | and \tmp, \tmp, #7 @ cache line size encoding | 69 | lsr \tmp, \tmp, #16 |
| 71 | mov \reg, #16 @ size offset | 70 | and \tmp, \tmp, #0xf @ cache line size encoding |
| 71 | mov \reg, #4 @ bytes per word | ||
| 72 | mov \reg, \reg, lsl \tmp @ actual cache line size | 72 | mov \reg, \reg, lsl \tmp @ actual cache line size |
| 73 | .endm | 73 | .endm |
| 74 | 74 | ||