2 files changed, 12 insertions, 3 deletions

diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 286c3ac6bdc..e5e172d2169 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -50,9 +50,11 @@ static void dma_init(struct fsldma_chan *chan)
                  * EIE - Error interrupt enable
                  * EOSIE - End of segments interrupt enable (basic mode)
                  * EOLNIE - End of links interrupt enable
+                 * BWC - Bandwidth sharing among channels
                  */
-                DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EIE
-                                | FSL_DMA_MR_EOLNIE | FSL_DMA_MR_EOSIE, 32);
+                DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_BWC
+                                | FSL_DMA_MR_EIE | FSL_DMA_MR_EOLNIE
+                                | FSL_DMA_MR_EOSIE, 32);
                 break;
         case FSL_DMA_IP_83XX:
                 /* Set the channel to below modes:
diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h
index cb4d6ff5159..ba9f403c0fb 100644
--- a/drivers/dma/fsldma.h
+++ b/drivers/dma/fsldma.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
+ * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
  *
  * Author:
  *   Zhang Wei <wei.zhang@freescale.com>, Jul 2007
@@ -36,6 +36,13 @@
 #define FSL_DMA_MR_DAHE         0x00002000
 #define FSL_DMA_MR_SAHE         0x00001000
 
+/*
+ * Bandwidth/pause control determines how many bytes a given
+ * channel is allowed to transfer before the DMA engine pauses
+ * the current channel and switches to the next channel
+ */
+#define FSL_DMA_MR_BWC         0x08000000
+
 /* Special MR definition for MPC8349 */
 #define FSL_DMA_MR_EOTIE        0x00000080
 #define FSL_DMA_MR_PRC_RM       0x00000800