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-rw-r--r--drivers/gpu/pvr/bridged_pvr_bridge.c23
-rw-r--r--drivers/gpu/pvr/buffer_manager.c19
-rw-r--r--drivers/gpu/pvr/device.h4
-rw-r--r--drivers/gpu/pvr/deviceclass.c27
-rw-r--r--drivers/gpu/pvr/devicemem.c43
-rw-r--r--drivers/gpu/pvr/event.c5
-rw-r--r--drivers/gpu/pvr/img_defs.h3
-rw-r--r--drivers/gpu/pvr/img_types.h9
-rw-r--r--drivers/gpu/pvr/mem.c10
-rw-r--r--drivers/gpu/pvr/module.c71
-rw-r--r--drivers/gpu/pvr/omap4/sysconfig.c239
-rw-r--r--drivers/gpu/pvr/omap4/sysconfig.h12
-rw-r--r--drivers/gpu/pvr/omap4/syslocal.h61
-rw-r--r--drivers/gpu/pvr/omap4/sysutils_linux.c308
-rw-r--r--drivers/gpu/pvr/osfunc.c45
-rw-r--r--drivers/gpu/pvr/pdump/dbgdriv.c8
-rw-r--r--drivers/gpu/pvr/pdump/dbgdriv.h12
-rw-r--r--drivers/gpu/pvr/pdump/dbgdriv_ioctl.h2
-rw-r--r--drivers/gpu/pvr/pdump/handle.c4
-rw-r--r--drivers/gpu/pvr/pdump/hostfunc.c18
-rw-r--r--drivers/gpu/pvr/pdump/hostfunc.h2
-rw-r--r--drivers/gpu/pvr/pdump/hotkey.c2
-rw-r--r--drivers/gpu/pvr/pdump/hotkey.h2
-rw-r--r--drivers/gpu/pvr/pdump/ioctl.c4
-rw-r--r--drivers/gpu/pvr/pdump/linuxsrv.h4
-rw-r--r--drivers/gpu/pvr/pdump/main.c13
-rw-r--r--drivers/gpu/pvr/perproc.c5
-rw-r--r--drivers/gpu/pvr/pvr_bridge_km.h2
-rw-r--r--drivers/gpu/pvr/pvr_debug.c5
-rw-r--r--drivers/gpu/pvr/pvrversion.h4
-rw-r--r--drivers/gpu/pvr/resman.c23
-rw-r--r--drivers/gpu/pvr/resman.h5
-rw-r--r--drivers/gpu/pvr/services.h4
-rw-r--r--drivers/gpu/pvr/servicesext.h49
-rw-r--r--drivers/gpu/pvr/sgx/bridged_sgx_bridge.c12
-rw-r--r--drivers/gpu/pvr/sgx/mmu.c5
-rw-r--r--drivers/gpu/pvr/sgx/mmu.h2
-rw-r--r--drivers/gpu/pvr/sgx/pb.c17
-rw-r--r--drivers/gpu/pvr/sgx/sgxinit.c12
-rw-r--r--drivers/gpu/pvr/sgx/sgxtransfer.c151
-rw-r--r--drivers/gpu/pvr/sgx/sgxutils.c154
-rw-r--r--drivers/gpu/pvr/sgx/sgxutils.h15
-rw-r--r--drivers/gpu/pvr/sgx520defs.h (renamed from drivers/gpu/pvr/sgx535defs.h)390
-rw-r--r--drivers/gpu/pvr/sgx544defs.h16
-rw-r--r--drivers/gpu/pvr/sgx_bridge.h3
-rw-r--r--drivers/gpu/pvr/sgxerrata.h27
46 files changed, 957 insertions, 894 deletions
diff --git a/drivers/gpu/pvr/bridged_pvr_bridge.c b/drivers/gpu/pvr/bridged_pvr_bridge.c
index b292d96b582..f1e606c87bc 100644
--- a/drivers/gpu/pvr/bridged_pvr_bridge.c
+++ b/drivers/gpu/pvr/bridged_pvr_bridge.c
@@ -822,6 +822,7 @@ PVRSRVMapDeviceMemoryBW(IMG_UINT32 ui32BridgeID,
822 822
823 NEW_HANDLE_BATCH_OR_ERROR(psMapDevMemOUT->eError, psPerProc, 2) 823 NEW_HANDLE_BATCH_OR_ERROR(psMapDevMemOUT->eError, psPerProc, 2)
824 824
825
825 psMapDevMemOUT->eError = PVRSRVLookupHandle(KERNEL_HANDLE_BASE, 826 psMapDevMemOUT->eError = PVRSRVLookupHandle(KERNEL_HANDLE_BASE,
826 (IMG_VOID**)&psSrcKernelMemInfo, 827 (IMG_VOID**)&psSrcKernelMemInfo,
827 psMapDevMemIN->hKernelMemInfo, 828 psMapDevMemIN->hKernelMemInfo,
@@ -831,6 +832,7 @@ PVRSRVMapDeviceMemoryBW(IMG_UINT32 ui32BridgeID,
831 return 0; 832 return 0;
832 } 833 }
833 834
835
834 psMapDevMemOUT->eError = PVRSRVLookupHandle(psPerProc->psHandleBase, 836 psMapDevMemOUT->eError = PVRSRVLookupHandle(psPerProc->psHandleBase,
835 &hDstDevMemHeap, 837 &hDstDevMemHeap,
836 psMapDevMemIN->hDstDevMemHeap, 838 psMapDevMemIN->hDstDevMemHeap,
@@ -839,11 +841,20 @@ PVRSRVMapDeviceMemoryBW(IMG_UINT32 ui32BridgeID,
839 { 841 {
840 return 0; 842 return 0;
841 } 843 }
844
842 845
843 if (psSrcKernelMemInfo->sShareMemWorkaround.bInUse) 846 if (psSrcKernelMemInfo->sShareMemWorkaround.bInUse)
844 { 847 {
845 PVR_DPF((PVR_DBG_MESSAGE, "using the mem wrap workaround.")); 848 PVR_DPF((PVR_DBG_MESSAGE, "using the mem wrap workaround."));
846 849
850
851
852
853
854
855
856
857
847 psMapDevMemOUT->eError = BM_XProcWorkaroundSetShareIndex(psSrcKernelMemInfo->sShareMemWorkaround.ui32ShareIndex); 858 psMapDevMemOUT->eError = BM_XProcWorkaroundSetShareIndex(psSrcKernelMemInfo->sShareMemWorkaround.ui32ShareIndex);
848 if(psMapDevMemOUT->eError != PVRSRV_OK) 859 if(psMapDevMemOUT->eError != PVRSRV_OK)
849 { 860 {
@@ -3833,11 +3844,13 @@ static PVRSRV_ERROR DoModifyCompleteSyncOps(MODIFY_SYNC_OP_INFO *psModSyncOpInfo
3833 3844
3834 3845
3835static PVRSRV_ERROR ModifyCompleteSyncOpsCallBack(IMG_PVOID pvParam, 3846static PVRSRV_ERROR ModifyCompleteSyncOpsCallBack(IMG_PVOID pvParam,
3836 IMG_UINT32 ui32Param) 3847 IMG_UINT32 ui32Param,
3848 IMG_BOOL bDummy)
3837{ 3849{
3838 MODIFY_SYNC_OP_INFO *psModSyncOpInfo; 3850 MODIFY_SYNC_OP_INFO *psModSyncOpInfo;
3839 3851
3840 PVR_UNREFERENCED_PARAMETER(ui32Param); 3852 PVR_UNREFERENCED_PARAMETER(ui32Param);
3853 PVR_UNREFERENCED_PARAMETER(bDummy);
3841 3854
3842 if (!pvParam) 3855 if (!pvParam)
3843 { 3856 {
@@ -3969,7 +3982,7 @@ PVRSRVDestroySyncInfoModObjBW(IMG_UINT32
3969 return 0; 3982 return 0;
3970 } 3983 }
3971 3984
3972 psDestroySyncInfoModObjOUT->eError = ResManFreeResByPtr(psModSyncOpInfo->hResItem); 3985 psDestroySyncInfoModObjOUT->eError = ResManFreeResByPtr(psModSyncOpInfo->hResItem, CLEANUP_WITH_POLL);
3973 if (psDestroySyncInfoModObjOUT->eError != PVRSRV_OK) 3986 if (psDestroySyncInfoModObjOUT->eError != PVRSRV_OK)
3974 { 3987 {
3975 PVR_DPF((PVR_DBG_ERROR, "PVRSRVDestroySyncInfoModObjBW: ResManFreeResByPtr failed")); 3988 PVR_DPF((PVR_DBG_ERROR, "PVRSRVDestroySyncInfoModObjBW: ResManFreeResByPtr failed"));
@@ -4274,12 +4287,14 @@ PVRSRVSyncOpsFlushToDeltaBW(IMG_UINT32 u
4274 4287
4275static PVRSRV_ERROR 4288static PVRSRV_ERROR
4276FreeSyncInfoCallback(IMG_PVOID pvParam, 4289FreeSyncInfoCallback(IMG_PVOID pvParam,
4277 IMG_UINT32 ui32Param) 4290 IMG_UINT32 ui32Param,
4291 IMG_BOOL bDummy)
4278{ 4292{
4279 PVRSRV_KERNEL_SYNC_INFO *psSyncInfo; 4293 PVRSRV_KERNEL_SYNC_INFO *psSyncInfo;
4280 PVRSRV_ERROR eError; 4294 PVRSRV_ERROR eError;
4281 4295
4282 PVR_UNREFERENCED_PARAMETER(ui32Param); 4296 PVR_UNREFERENCED_PARAMETER(ui32Param);
4297 PVR_UNREFERENCED_PARAMETER(bDummy);
4283 4298
4284 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)pvParam; 4299 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)pvParam;
4285 4300
@@ -4396,7 +4411,7 @@ PVRSRVFreeSyncInfoBW(IMG_UINT32 ui32Bri
4396 return 0; 4411 return 0;
4397 } 4412 }
4398 4413
4399 eError = ResManFreeResByPtr(psSyncInfo->hResItem); 4414 eError = ResManFreeResByPtr(psSyncInfo->hResItem, CLEANUP_WITH_POLL);
4400 if (eError != PVRSRV_OK) 4415 if (eError != PVRSRV_OK)
4401 { 4416 {
4402 PVR_DPF((PVR_DBG_ERROR, "PVRSRVFreeSyncInfoBW: ResManFreeResByPtr failed")); 4417 PVR_DPF((PVR_DBG_ERROR, "PVRSRVFreeSyncInfoBW: ResManFreeResByPtr failed"));
diff --git a/drivers/gpu/pvr/buffer_manager.c b/drivers/gpu/pvr/buffer_manager.c
index a8240585fb3..7b3cd7a1545 100644
--- a/drivers/gpu/pvr/buffer_manager.c
+++ b/drivers/gpu/pvr/buffer_manager.c
@@ -526,6 +526,7 @@ static IMG_VOID
526FreeBuf (BM_BUF *pBuf, IMG_UINT32 ui32Flags, IMG_BOOL bFromAllocator) 526FreeBuf (BM_BUF *pBuf, IMG_UINT32 ui32Flags, IMG_BOOL bFromAllocator)
527{ 527{
528 BM_MAPPING *pMapping; 528 BM_MAPPING *pMapping;
529 PVRSRV_DEVICE_NODE *psDeviceNode;
529 530
530 PVR_DPF ((PVR_DBG_MESSAGE, 531 PVR_DPF ((PVR_DBG_MESSAGE,
531 "FreeBuf: pBuf=0x%x: DevVAddr=%08X CpuVAddr=0x%x CpuPAddr=%08X", 532 "FreeBuf: pBuf=0x%x: DevVAddr=%08X CpuVAddr=0x%x CpuPAddr=%08X",
@@ -535,6 +536,12 @@ FreeBuf (BM_BUF *pBuf, IMG_UINT32 ui32Flags, IMG_BOOL bFromAllocator)
535 536
536 pMapping = pBuf->pMapping; 537 pMapping = pBuf->pMapping;
537 538
539 psDeviceNode = pMapping->pBMHeap->pBMContext->psDeviceNode;
540 if (psDeviceNode->pfnCacheInvalidate)
541 {
542 psDeviceNode->pfnCacheInvalidate(psDeviceNode);
543 }
544
538 if(ui32Flags & PVRSRV_MEM_USER_SUPPLIED_DEVVADDR) 545 if(ui32Flags & PVRSRV_MEM_USER_SUPPLIED_DEVVADDR)
539 { 546 {
540 547
@@ -695,7 +702,7 @@ BM_DestroyContext(IMG_HANDLE hBMContext,
695 else 702 else
696 { 703 {
697 704
698 eError = ResManFreeResByPtr(pBMContext->hResItem); 705 eError = ResManFreeResByPtr(pBMContext->hResItem, CLEANUP_WITH_POLL);
699 if(eError != PVRSRV_OK) 706 if(eError != PVRSRV_OK)
700 { 707 {
701 PVR_DPF ((PVR_DBG_ERROR, "BM_DestroyContext: ResManFreeResByPtr failed %d",eError)); 708 PVR_DPF ((PVR_DBG_ERROR, "BM_DestroyContext: ResManFreeResByPtr failed %d",eError));
@@ -745,13 +752,15 @@ static PVRSRV_ERROR BM_DestroyContextCallBack_AnyVaCb(BM_HEAP *psBMHeap, va_list
745} 752}
746 753
747 754
748static PVRSRV_ERROR BM_DestroyContextCallBack(IMG_PVOID pvParam, 755static PVRSRV_ERROR BM_DestroyContextCallBack(IMG_PVOID pvParam,
749 IMG_UINT32 ui32Param) 756 IMG_UINT32 ui32Param,
757 IMG_BOOL bDummy)
750{ 758{
751 BM_CONTEXT *pBMContext = pvParam; 759 BM_CONTEXT *pBMContext = pvParam;
752 PVRSRV_DEVICE_NODE *psDeviceNode; 760 PVRSRV_DEVICE_NODE *psDeviceNode;
753 PVRSRV_ERROR eError; 761 PVRSRV_ERROR eError;
754 PVR_UNREFERENCED_PARAMETER(ui32Param); 762 PVR_UNREFERENCED_PARAMETER(ui32Param);
763 PVR_UNREFERENCED_PARAMETER(bDummy);
755 764
756 765
757 766
@@ -969,7 +978,7 @@ BM_CreateContext(PVRSRV_DEVICE_NODE *psDeviceNode,
969 return (IMG_HANDLE)pBMContext; 978 return (IMG_HANDLE)pBMContext;
970 979
971cleanup: 980cleanup:
972 (IMG_VOID)BM_DestroyContextCallBack(pBMContext, 0); 981 (IMG_VOID)BM_DestroyContextCallBack(pBMContext, 0, CLEANUP_WITH_POLL);
973 982
974 return IMG_NULL; 983 return IMG_NULL;
975} 984}
@@ -1723,7 +1732,9 @@ DevMemoryFree (BM_MAPPING *pMapping)
1723 psDeviceNode->pfnMMUFree (pMapping->pBMHeap->pMMUHeap, pMapping->DevVAddr, IMG_CAST_TO_DEVVADDR_UINT(pMapping->uSize)); 1732 psDeviceNode->pfnMMUFree (pMapping->pBMHeap->pMMUHeap, pMapping->DevVAddr, IMG_CAST_TO_DEVVADDR_UINT(pMapping->uSize));
1724} 1733}
1725 1734
1735#ifndef XPROC_WORKAROUND_NUM_SHAREABLES
1726#define XPROC_WORKAROUND_NUM_SHAREABLES 200 1736#define XPROC_WORKAROUND_NUM_SHAREABLES 200
1737#endif
1727 1738
1728#define XPROC_WORKAROUND_BAD_SHAREINDEX 0773407734 1739#define XPROC_WORKAROUND_BAD_SHAREINDEX 0773407734
1729 1740
diff --git a/drivers/gpu/pvr/device.h b/drivers/gpu/pvr/device.h
index 86f37c6cd4e..9df2c734bc6 100644
--- a/drivers/gpu/pvr/device.h
+++ b/drivers/gpu/pvr/device.h
@@ -246,7 +246,9 @@ typedef struct _PVRSRV_DEVICE_NODE_
246 IMG_VOID (*pfnDeviceCommandComplete)(struct _PVRSRV_DEVICE_NODE_ *psDeviceNode); 246 IMG_VOID (*pfnDeviceCommandComplete)(struct _PVRSRV_DEVICE_NODE_ *psDeviceNode);
247 247
248 IMG_BOOL bReProcessDeviceCommandComplete; 248 IMG_BOOL bReProcessDeviceCommandComplete;
249 249
250 IMG_VOID (*pfnCacheInvalidate)(struct _PVRSRV_DEVICE_NODE_ *psDeviceNode);
251
250 252
251 DEVICE_MEMORY_INFO sDevMemoryInfo; 253 DEVICE_MEMORY_INFO sDevMemoryInfo;
252 254
diff --git a/drivers/gpu/pvr/deviceclass.c b/drivers/gpu/pvr/deviceclass.c
index 0e4b51a57e0..7b565dd8168 100644
--- a/drivers/gpu/pvr/deviceclass.c
+++ b/drivers/gpu/pvr/deviceclass.c
@@ -258,7 +258,7 @@ PVRSRV_ERROR PVRSRVRegisterDCDeviceKM (PVRSRV_DC_SRV2DISP_KMJTABLE *psFuncTable,
258 *psDCInfo->psFuncTable = *psFuncTable; 258 *psDCInfo->psFuncTable = *psFuncTable;
259 259
260 260
261 if(OSAllocMem( PVRSRV_OS_PAGEABLE_HEAP, 261 if(OSAllocMem( PVRSRV_OS_NON_PAGEABLE_HEAP,
262 sizeof(PVRSRV_DEVICE_NODE), 262 sizeof(PVRSRV_DEVICE_NODE),
263 (IMG_VOID **)&psDeviceNode, IMG_NULL, 263 (IMG_VOID **)&psDeviceNode, IMG_NULL,
264 "Device Node") != PVRSRV_OK) 264 "Device Node") != PVRSRV_OK)
@@ -420,7 +420,7 @@ PVRSRV_ERROR PVRSRVRegisterBCDeviceKM (PVRSRV_BC_SRV2BUFFER_KMJTABLE *psFuncTabl
420 *psBCInfo->psFuncTable = *psFuncTable; 420 *psBCInfo->psFuncTable = *psFuncTable;
421 421
422 422
423 if(OSAllocMem( PVRSRV_OS_PAGEABLE_HEAP, 423 if(OSAllocMem( PVRSRV_OS_NON_PAGEABLE_HEAP,
424 sizeof(PVRSRV_DEVICE_NODE), 424 sizeof(PVRSRV_DEVICE_NODE),
425 (IMG_VOID **)&psDeviceNode, IMG_NULL, 425 (IMG_VOID **)&psDeviceNode, IMG_NULL,
426 "Device Node") != PVRSRV_OK) 426 "Device Node") != PVRSRV_OK)
@@ -540,19 +540,21 @@ PVRSRV_ERROR PVRSRVCloseDCDeviceKM (IMG_HANDLE hDeviceKM,
540 psDCPerContextInfo = (PVRSRV_DISPLAYCLASS_PERCONTEXT_INFO *)hDeviceKM; 540 psDCPerContextInfo = (PVRSRV_DISPLAYCLASS_PERCONTEXT_INFO *)hDeviceKM;
541 541
542 542
543 eError = ResManFreeResByPtr(psDCPerContextInfo->hResItem); 543 eError = ResManFreeResByPtr(psDCPerContextInfo->hResItem, CLEANUP_WITH_POLL);
544 544
545 return eError; 545 return eError;
546} 546}
547 547
548 548
549static PVRSRV_ERROR CloseDCDeviceCallBack(IMG_PVOID pvParam, 549static PVRSRV_ERROR CloseDCDeviceCallBack(IMG_PVOID pvParam,
550 IMG_UINT32 ui32Param) 550 IMG_UINT32 ui32Param,
551 IMG_BOOL bDummy)
551{ 552{
552 PVRSRV_DISPLAYCLASS_PERCONTEXT_INFO *psDCPerContextInfo; 553 PVRSRV_DISPLAYCLASS_PERCONTEXT_INFO *psDCPerContextInfo;
553 PVRSRV_DISPLAYCLASS_INFO *psDCInfo; 554 PVRSRV_DISPLAYCLASS_INFO *psDCInfo;
554 555
555 PVR_UNREFERENCED_PARAMETER(ui32Param); 556 PVR_UNREFERENCED_PARAMETER(ui32Param);
557 PVR_UNREFERENCED_PARAMETER(bDummy);
556 558
557 psDCPerContextInfo = (PVRSRV_DISPLAYCLASS_PERCONTEXT_INFO *)pvParam; 559 psDCPerContextInfo = (PVRSRV_DISPLAYCLASS_PERCONTEXT_INFO *)pvParam;
558 psDCInfo = psDCPerContextInfo->psDCInfo; 560 psDCInfo = psDCPerContextInfo->psDCInfo;
@@ -812,7 +814,7 @@ PVRSRV_ERROR PVRSRVDestroyDCSwapChainKM(IMG_HANDLE hSwapChainRef)
812 814
813 psSwapChainRef = hSwapChainRef; 815 psSwapChainRef = hSwapChainRef;
814 816
815 eError = ResManFreeResByPtr(psSwapChainRef->hResItem); 817 eError = ResManFreeResByPtr(psSwapChainRef->hResItem, CLEANUP_WITH_POLL);
816 818
817 return eError; 819 return eError;
818} 820}
@@ -880,13 +882,16 @@ static PVRSRV_ERROR DestroyDCSwapChain(PVRSRV_DC_SWAPCHAIN *psSwapChain)
880} 882}
881 883
882 884
883static PVRSRV_ERROR DestroyDCSwapChainRefCallBack(IMG_PVOID pvParam, IMG_UINT32 ui32Param) 885static PVRSRV_ERROR DestroyDCSwapChainRefCallBack(IMG_PVOID pvParam,
886 IMG_UINT32 ui32Param,
887 IMG_BOOL bDummy)
884{ 888{
885 PVRSRV_DC_SWAPCHAIN_REF *psSwapChainRef = (PVRSRV_DC_SWAPCHAIN_REF *) pvParam; 889 PVRSRV_DC_SWAPCHAIN_REF *psSwapChainRef = (PVRSRV_DC_SWAPCHAIN_REF *) pvParam;
886 PVRSRV_ERROR eError = PVRSRV_OK; 890 PVRSRV_ERROR eError = PVRSRV_OK;
887 IMG_UINT32 i; 891 IMG_UINT32 i;
888 892
889 PVR_UNREFERENCED_PARAMETER(ui32Param); 893 PVR_UNREFERENCED_PARAMETER(ui32Param);
894 PVR_UNREFERENCED_PARAMETER(bDummy);
890 895
891 for (i = 0; i < psSwapChainRef->psSwapChain->ui32BufferCount; i++) 896 for (i = 0; i < psSwapChainRef->psSwapChain->ui32BufferCount; i++)
892 { 897 {
@@ -1705,20 +1710,22 @@ PVRSRV_ERROR PVRSRVCloseBCDeviceKM (IMG_HANDLE hDeviceKM,
1705 psBCPerContextInfo = (PVRSRV_BUFFERCLASS_PERCONTEXT_INFO *)hDeviceKM; 1710 psBCPerContextInfo = (PVRSRV_BUFFERCLASS_PERCONTEXT_INFO *)hDeviceKM;
1706 1711
1707 1712
1708 eError = ResManFreeResByPtr(psBCPerContextInfo->hResItem); 1713 eError = ResManFreeResByPtr(psBCPerContextInfo->hResItem, CLEANUP_WITH_POLL);
1709 1714
1710 return eError; 1715 return eError;
1711} 1716}
1712 1717
1713 1718
1714static PVRSRV_ERROR CloseBCDeviceCallBack(IMG_PVOID pvParam, 1719static PVRSRV_ERROR CloseBCDeviceCallBack(IMG_PVOID pvParam,
1715 IMG_UINT32 ui32Param) 1720 IMG_UINT32 ui32Param,
1721 IMG_BOOL bDummy)
1716{ 1722{
1717 PVRSRV_BUFFERCLASS_PERCONTEXT_INFO *psBCPerContextInfo; 1723 PVRSRV_BUFFERCLASS_PERCONTEXT_INFO *psBCPerContextInfo;
1718 PVRSRV_BUFFERCLASS_INFO *psBCInfo; 1724 PVRSRV_BUFFERCLASS_INFO *psBCInfo;
1719 IMG_UINT32 i; 1725 IMG_UINT32 i;
1720 1726
1721 PVR_UNREFERENCED_PARAMETER(ui32Param); 1727 PVR_UNREFERENCED_PARAMETER(ui32Param);
1728 PVR_UNREFERENCED_PARAMETER(bDummy);
1722 1729
1723 psBCPerContextInfo = (PVRSRV_BUFFERCLASS_PERCONTEXT_INFO *)pvParam; 1730 psBCPerContextInfo = (PVRSRV_BUFFERCLASS_PERCONTEXT_INFO *)pvParam;
1724 1731
diff --git a/drivers/gpu/pvr/devicemem.c b/drivers/gpu/pvr/devicemem.c
index 3016736c5c1..adf8e774880 100644
--- a/drivers/gpu/pvr/devicemem.c
+++ b/drivers/gpu/pvr/devicemem.c
@@ -662,11 +662,14 @@ static PVRSRV_ERROR FreeMemCallBackCommon(PVRSRV_KERNEL_MEM_INFO *psMemInfo,
662 return eError; 662 return eError;
663} 663}
664 664
665static PVRSRV_ERROR FreeDeviceMemCallBack(IMG_PVOID pvParam, 665static PVRSRV_ERROR FreeDeviceMemCallBack(IMG_PVOID pvParam,
666 IMG_UINT32 ui32Param) 666 IMG_UINT32 ui32Param,
667 IMG_BOOL bDummy)
667{ 668{
668 PVRSRV_KERNEL_MEM_INFO *psMemInfo = (PVRSRV_KERNEL_MEM_INFO *)pvParam; 669 PVRSRV_KERNEL_MEM_INFO *psMemInfo = (PVRSRV_KERNEL_MEM_INFO *)pvParam;
669 670
671 PVR_UNREFERENCED_PARAMETER(bDummy);
672
670 return FreeMemCallBackCommon(psMemInfo, ui32Param, IMG_TRUE); 673 return FreeMemCallBackCommon(psMemInfo, ui32Param, IMG_TRUE);
671} 674}
672 675
@@ -686,12 +689,12 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVFreeDeviceMemKM(IMG_HANDLE hDevCookie,
686 689
687 if (psMemInfo->sMemBlk.hResItem != IMG_NULL) 690 if (psMemInfo->sMemBlk.hResItem != IMG_NULL)
688 { 691 {
689 eError = ResManFreeResByPtr(psMemInfo->sMemBlk.hResItem); 692 eError = ResManFreeResByPtr(psMemInfo->sMemBlk.hResItem, CLEANUP_WITH_POLL);
690 } 693 }
691 else 694 else
692 { 695 {
693 696
694 eError = FreeDeviceMemCallBack(psMemInfo, 0); 697 eError = FreeDeviceMemCallBack(psMemInfo, 0, CLEANUP_WITH_POLL);
695 } 698 }
696 699
697 return eError; 700 return eError;
@@ -849,15 +852,18 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVUnwrapExtMemoryKM (PVRSRV_KERNEL_MEM_INFO *psMem
849 return PVRSRV_ERROR_INVALID_PARAMS; 852 return PVRSRV_ERROR_INVALID_PARAMS;
850 } 853 }
851 854
852 return ResManFreeResByPtr(psMemInfo->sMemBlk.hResItem); 855 return ResManFreeResByPtr(psMemInfo->sMemBlk.hResItem, CLEANUP_WITH_POLL);
853} 856}
854 857
855 858
856static PVRSRV_ERROR UnwrapExtMemoryCallBack(IMG_PVOID pvParam, 859static PVRSRV_ERROR UnwrapExtMemoryCallBack(IMG_PVOID pvParam,
857 IMG_UINT32 ui32Param) 860 IMG_UINT32 ui32Param,
861 IMG_BOOL bDummy)
858{ 862{
859 PVRSRV_KERNEL_MEM_INFO *psMemInfo = (PVRSRV_KERNEL_MEM_INFO *)pvParam; 863 PVRSRV_KERNEL_MEM_INFO *psMemInfo = (PVRSRV_KERNEL_MEM_INFO *)pvParam;
860 864
865 PVR_UNREFERENCED_PARAMETER(bDummy);
866
861 return FreeMemCallBackCommon(psMemInfo, ui32Param, IMG_TRUE); 867 return FreeMemCallBackCommon(psMemInfo, ui32Param, IMG_TRUE);
862} 868}
863 869
@@ -1101,17 +1107,19 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVUnmapDeviceMemoryKM (PVRSRV_KERNEL_MEM_INFO *psM
1101 return PVRSRV_ERROR_INVALID_PARAMS; 1107 return PVRSRV_ERROR_INVALID_PARAMS;
1102 } 1108 }
1103 1109
1104 return ResManFreeResByPtr(psMemInfo->sMemBlk.hResItem); 1110 return ResManFreeResByPtr(psMemInfo->sMemBlk.hResItem, CLEANUP_WITH_POLL);
1105} 1111}
1106 1112
1107 1113
1108static PVRSRV_ERROR UnmapDeviceMemoryCallBack(IMG_PVOID pvParam, 1114static PVRSRV_ERROR UnmapDeviceMemoryCallBack(IMG_PVOID pvParam,
1109 IMG_UINT32 ui32Param) 1115 IMG_UINT32 ui32Param,
1116 IMG_BOOL bDummy)
1110{ 1117{
1111 PVRSRV_ERROR eError; 1118 PVRSRV_ERROR eError;
1112 RESMAN_MAP_DEVICE_MEM_DATA *psMapData = pvParam; 1119 RESMAN_MAP_DEVICE_MEM_DATA *psMapData = pvParam;
1113 1120
1114 PVR_UNREFERENCED_PARAMETER(ui32Param); 1121 PVR_UNREFERENCED_PARAMETER(ui32Param);
1122 PVR_UNREFERENCED_PARAMETER(bDummy);
1115 1123
1116 if(psMapData->psMemInfo->sMemBlk.psIntSysPAddr) 1124 if(psMapData->psMemInfo->sMemBlk.psIntSysPAddr)
1117 { 1125 {
@@ -1350,17 +1358,19 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVUnmapDeviceClassMemoryKM(PVRSRV_KERNEL_MEM_INFO
1350 return PVRSRV_ERROR_INVALID_PARAMS; 1358 return PVRSRV_ERROR_INVALID_PARAMS;
1351 } 1359 }
1352 1360
1353 return ResManFreeResByPtr(psMemInfo->sMemBlk.hResItem); 1361 return ResManFreeResByPtr(psMemInfo->sMemBlk.hResItem, CLEANUP_WITH_POLL);
1354} 1362}
1355 1363
1356 1364
1357static PVRSRV_ERROR UnmapDeviceClassMemoryCallBack(IMG_PVOID pvParam, 1365static PVRSRV_ERROR UnmapDeviceClassMemoryCallBack(IMG_PVOID pvParam,
1358 IMG_UINT32 ui32Param) 1366 IMG_UINT32 ui32Param,
1367 IMG_BOOL bDummy)
1359{ 1368{
1360 PVRSRV_DC_MAPINFO *psDCMapInfo = pvParam; 1369 PVRSRV_DC_MAPINFO *psDCMapInfo = pvParam;
1361 PVRSRV_KERNEL_MEM_INFO *psMemInfo; 1370 PVRSRV_KERNEL_MEM_INFO *psMemInfo;
1362 1371
1363 PVR_UNREFERENCED_PARAMETER(ui32Param); 1372 PVR_UNREFERENCED_PARAMETER(ui32Param);
1373 PVR_UNREFERENCED_PARAMETER(bDummy);
1364 1374
1365 psMemInfo = psDCMapInfo->psMemInfo; 1375 psMemInfo = psDCMapInfo->psMemInfo;
1366 1376
@@ -1378,9 +1388,6 @@ static PVRSRV_ERROR UnmapDeviceClassMemoryCallBack(IMG_PVOID pvParam,
1378#endif 1388#endif
1379 1389
1380 (psDCMapInfo->psDeviceClassBuffer->ui32MemMapRefCount)--; 1390 (psDCMapInfo->psDeviceClassBuffer->ui32MemMapRefCount)--;
1381 PVR_TRACE(("decrementing (0x%p) psDCMapInfo->psDeviceClassBuffer->ui32MemMapRefCount... == %d",
1382 psDCMapInfo->psDeviceClassBuffer,
1383 psDCMapInfo->psDeviceClassBuffer->ui32MemMapRefCount));
1384 1391
1385 OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, sizeof(PVRSRV_DC_MAPINFO), psDCMapInfo, IMG_NULL); 1392 OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, sizeof(PVRSRV_DC_MAPINFO), psDCMapInfo, IMG_NULL);
1386 1393
@@ -1588,10 +1595,6 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVMapDeviceClassMemoryKM(PVRSRV_PER_PROCESS_DATA *
1588 &UnmapDeviceClassMemoryCallBack); 1595 &UnmapDeviceClassMemoryCallBack);
1589 1596
1590 (psDeviceClassBuffer->ui32MemMapRefCount)++; 1597 (psDeviceClassBuffer->ui32MemMapRefCount)++;
1591 PVR_TRACE(("incrementing (0x%p) psDeviceClassBuffer->ui32MemMapRefCount... == %d",
1592 psDeviceClassBuffer,
1593 psDeviceClassBuffer->ui32MemMapRefCount));
1594
1595 psMemInfo->ui32RefCount++; 1598 psMemInfo->ui32RefCount++;
1596 1599
1597 psMemInfo->memType = PVRSRV_MEMTYPE_DEVICECLASS; 1600 psMemInfo->memType = PVRSRV_MEMTYPE_DEVICECLASS;
diff --git a/drivers/gpu/pvr/event.c b/drivers/gpu/pvr/event.c
index e8797c4ecb9..888871b3a92 100644
--- a/drivers/gpu/pvr/event.c
+++ b/drivers/gpu/pvr/event.c
@@ -140,7 +140,7 @@ PVRSRV_ERROR LinuxEventObjectDelete(IMG_HANDLE hOSEventObjectList, IMG_HANDLE hO
140#if defined(DEBUG) 140#if defined(DEBUG)
141 PVR_DPF((PVR_DBG_MESSAGE, "LinuxEventObjectListDelete: Event object waits: %u", psLinuxEventObject->ui32Stats)); 141 PVR_DPF((PVR_DBG_MESSAGE, "LinuxEventObjectListDelete: Event object waits: %u", psLinuxEventObject->ui32Stats));
142#endif 142#endif
143 if(ResManFreeResByPtr(psLinuxEventObject->hResItem) != PVRSRV_OK) 143 if(ResManFreeResByPtr(psLinuxEventObject->hResItem, CLEANUP_WITH_POLL) != PVRSRV_OK)
144 { 144 {
145 return PVRSRV_ERROR_UNABLE_TO_DESTROY_EVENT; 145 return PVRSRV_ERROR_UNABLE_TO_DESTROY_EVENT;
146 } 146 }
@@ -152,13 +152,14 @@ PVRSRV_ERROR LinuxEventObjectDelete(IMG_HANDLE hOSEventObjectList, IMG_HANDLE hO
152 152
153} 153}
154 154
155static PVRSRV_ERROR LinuxEventObjectDeleteCallback(IMG_PVOID pvParam, IMG_UINT32 ui32Param) 155static PVRSRV_ERROR LinuxEventObjectDeleteCallback(IMG_PVOID pvParam, IMG_UINT32 ui32Param, IMG_BOOL bForceCleanup)
156{ 156{
157 PVRSRV_LINUX_EVENT_OBJECT *psLinuxEventObject = pvParam; 157 PVRSRV_LINUX_EVENT_OBJECT *psLinuxEventObject = pvParam;
158 PVRSRV_LINUX_EVENT_OBJECT_LIST *psLinuxEventObjectList = psLinuxEventObject->psLinuxEventObjectList; 158 PVRSRV_LINUX_EVENT_OBJECT_LIST *psLinuxEventObjectList = psLinuxEventObject->psLinuxEventObjectList;
159 unsigned long ulLockFlags; 159 unsigned long ulLockFlags;
160 160
161 PVR_UNREFERENCED_PARAMETER(ui32Param); 161 PVR_UNREFERENCED_PARAMETER(ui32Param);
162 PVR_UNREFERENCED_PARAMETER(bForceCleanup);
162 163
163 write_lock_irqsave(&psLinuxEventObjectList->sLock, ulLockFlags); 164 write_lock_irqsave(&psLinuxEventObjectList->sLock, ulLockFlags);
164 list_del(&psLinuxEventObject->sList); 165 list_del(&psLinuxEventObject->sList);
diff --git a/drivers/gpu/pvr/img_defs.h b/drivers/gpu/pvr/img_defs.h
index 3ef43aad611..8ca49d2d076 100644
--- a/drivers/gpu/pvr/img_defs.h
+++ b/drivers/gpu/pvr/img_defs.h
@@ -109,6 +109,9 @@ typedef char TCHAR, *PTCHAR, *PTSTR;
109#define IMG_FORMAT_PRINTF(x,y) 109#define IMG_FORMAT_PRINTF(x,y)
110#endif 110#endif
111 111
112#define CLEANUP_WITH_POLL IMG_FALSE
113#define FORCE_CLEANUP IMG_TRUE
114
112#if defined (_WIN64) 115#if defined (_WIN64)
113#define IMG_UNDEF (~0ULL) 116#define IMG_UNDEF (~0ULL)
114#else 117#else
diff --git a/drivers/gpu/pvr/img_types.h b/drivers/gpu/pvr/img_types.h
index 4401f4dd92c..3800afb5644 100644
--- a/drivers/gpu/pvr/img_types.h
+++ b/drivers/gpu/pvr/img_types.h
@@ -1,6 +1,6 @@
1/********************************************************************** 1/**********************************************************************
2 * 2 *
3 * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved. 3 * Copyright (C) Imagination Technologies Ltd. All rights reserved.
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License, 6 * under the terms and conditions of the GNU General Public License,
@@ -104,6 +104,13 @@ typedef void** IMG_HVOID, * IMG_PHVOID;
104typedef IMG_UINT32 IMG_SID; 104typedef IMG_UINT32 IMG_SID;
105 105
106typedef IMG_UINT32 IMG_EVENTSID; 106typedef IMG_UINT32 IMG_EVENTSID;
107
108#if defined(SUPPORT_SID_INTERFACE)
109 typedef IMG_SID IMG_S_HANDLE;
110#else
111 typedef IMG_HANDLE IMG_S_HANDLE;
112#endif
113
107typedef IMG_PVOID IMG_CPU_VIRTADDR; 114typedef IMG_PVOID IMG_CPU_VIRTADDR;
108 115
109typedef struct _IMG_DEV_VIRTADDR 116typedef struct _IMG_DEV_VIRTADDR
diff --git a/drivers/gpu/pvr/mem.c b/drivers/gpu/pvr/mem.c
index f71644e572f..5b5d1ac541a 100644
--- a/drivers/gpu/pvr/mem.c
+++ b/drivers/gpu/pvr/mem.c
@@ -29,12 +29,14 @@
29 29
30 30
31static PVRSRV_ERROR 31static PVRSRV_ERROR
32FreeSharedSysMemCallBack(IMG_PVOID pvParam, 32FreeSharedSysMemCallBack(IMG_PVOID pvParam,
33 IMG_UINT32 ui32Param) 33 IMG_UINT32 ui32Param,
34 IMG_BOOL bDummy)
34{ 35{
35 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo = pvParam; 36 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo = pvParam;
36 37
37 PVR_UNREFERENCED_PARAMETER(ui32Param); 38 PVR_UNREFERENCED_PARAMETER(ui32Param);
39 PVR_UNREFERENCED_PARAMETER(bDummy);
38 40
39 OSFreePages(psKernelMemInfo->ui32Flags, 41 OSFreePages(psKernelMemInfo->ui32Flags,
40 psKernelMemInfo->uAllocSize, 42 psKernelMemInfo->uAllocSize,
@@ -111,11 +113,11 @@ PVRSRVFreeSharedSysMemoryKM(PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo)
111 113
112 if(psKernelMemInfo->sMemBlk.hResItem) 114 if(psKernelMemInfo->sMemBlk.hResItem)
113 { 115 {
114 eError = ResManFreeResByPtr(psKernelMemInfo->sMemBlk.hResItem); 116 eError = ResManFreeResByPtr(psKernelMemInfo->sMemBlk.hResItem, CLEANUP_WITH_POLL);
115 } 117 }
116 else 118 else
117 { 119 {
118 eError = FreeSharedSysMemCallBack(psKernelMemInfo, 0); 120 eError = FreeSharedSysMemCallBack(psKernelMemInfo, 0, CLEANUP_WITH_POLL);
119 } 121 }
120 122
121 return eError; 123 return eError;
diff --git a/drivers/gpu/pvr/module.c b/drivers/gpu/pvr/module.c
index cb05ea76cbf..f689f363d4c 100644
--- a/drivers/gpu/pvr/module.c
+++ b/drivers/gpu/pvr/module.c
@@ -28,7 +28,9 @@
28 #include <linux/config.h> 28 #include <linux/config.h>
29#endif 29#endif
30 30
31#if !defined(SUPPORT_DRI_DRM) 31#if defined(SUPPORT_DRI_DRM)
32#define PVR_MOD_STATIC
33#else
32 34
33 #if defined(LDM_PLATFORM) 35 #if defined(LDM_PLATFORM)
34 #define PVR_LDM_PLATFORM_MODULE 36 #define PVR_LDM_PLATFORM_MODULE
@@ -39,6 +41,13 @@
39 #define PVR_LDM_MODULE 41 #define PVR_LDM_MODULE
40 #endif 42 #endif
41 #endif 43 #endif
44#define PVR_MOD_STATIC static
45#endif
46
47#if defined(PVR_LDM_PLATFORM_PRE_REGISTERED)
48#if !defined(NO_HARDWARE)
49#define PVR_USE_PRE_REGISTERED_PLATFORM_DEV
50#endif
42#endif 51#endif
43 52
44#include <linux/init.h> 53#include <linux/init.h>
@@ -152,7 +161,6 @@ static IMG_UINT32 gPVRPowerLevel;
152#define LDM_DEV struct pci_dev 161#define LDM_DEV struct pci_dev
153#define LDM_DRV struct pci_driver 162#define LDM_DRV struct pci_driver
154#endif 163#endif
155
156#if defined(PVR_LDM_PLATFORM_MODULE) 164#if defined(PVR_LDM_PLATFORM_MODULE)
157static int PVRSRVDriverRemove(LDM_DEV *device); 165static int PVRSRVDriverRemove(LDM_DEV *device);
158static int PVRSRVDriverProbe(LDM_DEV *device); 166static int PVRSRVDriverProbe(LDM_DEV *device);
@@ -167,16 +175,23 @@ static int PVRSRVDriverResume(LDM_DEV *device);
167 175
168#if defined(PVR_LDM_PCI_MODULE) 176#if defined(PVR_LDM_PCI_MODULE)
169struct pci_device_id powervr_id_table[] __devinitdata = { 177struct pci_device_id powervr_id_table[] __devinitdata = {
170 { PCI_DEVICE(SYS_SGX_DEV_VENDOR_ID, SYS_SGX_DEV_DEVICE_ID) }, 178 {PCI_DEVICE(SYS_SGX_DEV_VENDOR_ID, SYS_SGX_DEV_DEVICE_ID)},
171#if defined (SYS_SGX_DEV1_DEVICE_ID) 179#if defined (SYS_SGX_DEV1_DEVICE_ID)
172 { PCI_DEVICE(SYS_SGX_DEV_VENDOR_ID, SYS_SGX_DEV1_DEVICE_ID) }, 180 {PCI_DEVICE(SYS_SGX_DEV_VENDOR_ID, SYS_SGX_DEV1_DEVICE_ID)},
173#endif 181#endif
174 { 0 } 182 {0}
175}; 183};
176 184
177MODULE_DEVICE_TABLE(pci, powervr_id_table); 185MODULE_DEVICE_TABLE(pci, powervr_id_table);
178#endif 186#endif
179 187
188#if defined(PVR_USE_PRE_REGISTERED_PLATFORM_DEV)
189static struct platform_device_id powervr_id_table[] __devinitdata = {
190 {SYS_SGX_DEV_NAME, 0},
191 {}
192};
193#endif
194
180static LDM_DRV powervr_driver = { 195static LDM_DRV powervr_driver = {
181#if defined(PVR_LDM_PLATFORM_MODULE) 196#if defined(PVR_LDM_PLATFORM_MODULE)
182 .driver = { 197 .driver = {
@@ -185,6 +200,8 @@ static LDM_DRV powervr_driver = {
185#endif 200#endif
186#if defined(PVR_LDM_PCI_MODULE) 201#if defined(PVR_LDM_PCI_MODULE)
187 .name = DRVNAME, 202 .name = DRVNAME,
203#endif
204#if defined(PVR_LDM_PCI_MODULE) || defined(PVR_USE_PRE_REGISTERED_PLATFORM_DEV)
188 .id_table = powervr_id_table, 205 .id_table = powervr_id_table,
189#endif 206#endif
190 .probe = PVRSRVDriverProbe, 207 .probe = PVRSRVDriverProbe,
@@ -201,9 +218,9 @@ static LDM_DRV powervr_driver = {
201 218
202LDM_DEV *gpsPVRLDMDev; 219LDM_DEV *gpsPVRLDMDev;
203 220
204#if defined(MODULE) && defined(PVR_LDM_PLATFORM_MODULE) 221#if defined(MODULE) && defined(PVR_LDM_PLATFORM_MODULE) && \
205 222 !defined(PVR_USE_PRE_REGISTERED_PLATFORM_DEV)
206static IMG_VOID PVRSRVDeviceRelease(struct device unref__ *pDevice) 223static void PVRSRVDeviceRelease(struct device unref__ *pDevice)
207{ 224{
208} 225}
209 226
@@ -214,8 +231,7 @@ static struct platform_device powervr_device = {
214 .release = PVRSRVDeviceRelease 231 .release = PVRSRVDeviceRelease
215 } 232 }
216}; 233};
217 234#endif
218#endif
219 235
220#if defined(PVR_LDM_PLATFORM_MODULE) 236#if defined(PVR_LDM_PLATFORM_MODULE)
221static int PVRSRVDriverProbe(LDM_DEV *pDevice) 237static int PVRSRVDriverProbe(LDM_DEV *pDevice)
@@ -273,7 +289,7 @@ static void __devexit PVRSRVDriverRemove(LDM_DEV *pDevice)
273 } 289 }
274 } 290 }
275#endif 291#endif
276 (IMG_VOID)SysDeinitialise(psSysData); 292 (void) SysDeinitialise(psSysData);
277 293
278 gpsPVRLDMDev = IMG_NULL; 294 gpsPVRLDMDev = IMG_NULL;
279 295
@@ -291,23 +307,25 @@ static void __devexit PVRSRVDriverRemove(LDM_DEV *pDevice)
291 return; 307 return;
292#endif 308#endif
293} 309}
310#endif
294 311
295 312
296static IMG_VOID PVRSRVDriverShutdown(LDM_DEV *pDevice) 313#if defined(PVR_LDM_MODULE) || defined(PVR_DRI_DRM_PLATFORM_DEV)
314PVR_MOD_STATIC void PVRSRVDriverShutdown(LDM_DEV *pDevice)
297{ 315{
298 PVR_TRACE(("PVRSRVDriverShutdown(pDevice=%p)", pDevice)); 316 PVR_TRACE(("PVRSRVDriverShutdown(pDevice=%p)", pDevice));
299 317
300 (IMG_VOID) PVRSRVSetPowerStateKM(PVRSRV_SYS_POWER_STATE_D3); 318 (void) PVRSRVSetPowerStateKM(PVRSRV_SYS_POWER_STATE_D3);
301} 319}
302 320
303#endif 321#endif
304 322
305 323
306#if defined(PVR_LDM_MODULE) || defined(SUPPORT_DRI_DRM) 324#if defined(PVR_LDM_MODULE) || defined(SUPPORT_DRI_DRM)
307#if defined(SUPPORT_DRI_DRM) 325#if defined(SUPPORT_DRI_DRM) && !defined(PVR_DRI_DRM_PLATFORM_DEV)
308int PVRSRVDriverSuspend(struct drm_device *pDevice, pm_message_t state) 326int PVRSRVDriverSuspend(struct drm_device *pDevice, pm_message_t state)
309#else 327#else
310static int PVRSRVDriverSuspend(LDM_DEV *pDevice, pm_message_t state) 328PVR_MOD_STATIC int PVRSRVDriverSuspend(LDM_DEV *pDevice, pm_message_t state)
311#endif 329#endif
312{ 330{
313#if !(defined(DEBUG) && defined(PVR_MANUAL_POWER_CONTROL) && !defined(SUPPORT_DRI_DRM)) 331#if !(defined(DEBUG) && defined(PVR_MANUAL_POWER_CONTROL) && !defined(SUPPORT_DRI_DRM))
@@ -322,10 +340,10 @@ static int PVRSRVDriverSuspend(LDM_DEV *pDevice, pm_message_t state)
322} 340}
323 341
324 342
325#if defined(SUPPORT_DRI_DRM) 343#if defined(SUPPORT_DRI_DRM) && !defined(PVR_DRI_DRM_PLATFORM_DEV)
326int PVRSRVDriverResume(struct drm_device *pDevice) 344int PVRSRVDriverResume(struct drm_device *pDevice)
327#else 345#else
328static int PVRSRVDriverResume(LDM_DEV *pDevice) 346PVR_MOD_STATIC int PVRSRVDriverResume(LDM_DEV *pDevice)
329#endif 347#endif
330{ 348{
331#if !(defined(DEBUG) && defined(PVR_MANUAL_POWER_CONTROL) && !defined(SUPPORT_DRI_DRM)) 349#if !(defined(DEBUG) && defined(PVR_MANUAL_POWER_CONTROL) && !defined(SUPPORT_DRI_DRM))
@@ -492,9 +510,9 @@ static int PVRSRVRelease(struct inode unref__ * pInode, struct file *pFile)
492 510
493 511
494#if defined(SUPPORT_DRI_DRM) 512#if defined(SUPPORT_DRI_DRM)
495int PVRCore_Init(IMG_VOID) 513int PVRCore_Init(void)
496#else 514#else
497static int __init PVRCore_Init(IMG_VOID) 515static int __init PVRCore_Init(void)
498#endif 516#endif
499{ 517{
500 int error; 518 int error;
@@ -546,7 +564,7 @@ static int __init PVRCore_Init(IMG_VOID)
546 goto init_failed; 564 goto init_failed;
547 } 565 }
548 566
549#if defined(MODULE) 567#if defined(MODULE) && !defined(PVR_USE_PRE_REGISTERED_PLATFORM_DEV)
550 if ((error = platform_device_register(&powervr_device)) != 0) 568 if ((error = platform_device_register(&powervr_device)) != 0)
551 { 569 {
552 platform_driver_unregister(&powervr_driver); 570 platform_driver_unregister(&powervr_driver);
@@ -638,7 +656,7 @@ sys_deinit:
638#endif 656#endif
639 657
640#if defined (PVR_LDM_PLATFORM_MODULE) 658#if defined (PVR_LDM_PLATFORM_MODULE)
641#if defined (MODULE) 659#if defined(MODULE) && !defined(PVR_USE_PRE_REGISTERED_PLATFORM_DEV)
642 platform_device_unregister(&powervr_device); 660 platform_device_unregister(&powervr_device);
643#endif 661#endif
644 platform_driver_unregister(&powervr_driver); 662 platform_driver_unregister(&powervr_driver);
@@ -652,7 +670,7 @@ sys_deinit:
652 psSysData = SysAcquireDataNoCheck(); 670 psSysData = SysAcquireDataNoCheck();
653 if (psSysData != IMG_NULL) 671 if (psSysData != IMG_NULL)
654 { 672 {
655 (IMG_VOID)SysDeinitialise(psSysData); 673 (void) SysDeinitialise(psSysData);
656 } 674 }
657 } 675 }
658#endif 676#endif
@@ -674,11 +692,14 @@ void PVRCore_Cleanup(void)
674static void __exit PVRCore_Cleanup(void) 692static void __exit PVRCore_Cleanup(void)
675#endif 693#endif
676{ 694{
695#if !defined(PVR_LDM_MODULE)
677 SYS_DATA *psSysData; 696 SYS_DATA *psSysData;
678 697#endif
679 PVR_TRACE(("PVRCore_Cleanup")); 698 PVR_TRACE(("PVRCore_Cleanup"));
680 699
700#if !defined(PVR_LDM_MODULE)
681 SysAcquireData(&psSysData); 701 SysAcquireData(&psSysData);
702#endif
682 703
683#if defined(PVR_LDM_MODULE) 704#if defined(PVR_LDM_MODULE)
684 device_destroy(psPvrClass, MKDEV(AssignedMajorNumber, 0)); 705 device_destroy(psPvrClass, MKDEV(AssignedMajorNumber, 0));
@@ -707,7 +728,7 @@ static void __exit PVRCore_Cleanup(void)
707#endif 728#endif
708 729
709#if defined (PVR_LDM_PLATFORM_MODULE) 730#if defined (PVR_LDM_PLATFORM_MODULE)
710#if defined (MODULE) 731#if defined(MODULE) && !defined(PVR_USE_PRE_REGISTERED_PLATFORM_DEV)
711 platform_device_unregister(&powervr_device); 732 platform_device_unregister(&powervr_device);
712#endif 733#endif
713 platform_driver_unregister(&powervr_driver); 734 platform_driver_unregister(&powervr_driver);
@@ -741,6 +762,6 @@ static void __exit PVRCore_Cleanup(void)
741} 762}
742 763
743#if !defined(SUPPORT_DRI_DRM) 764#if !defined(SUPPORT_DRI_DRM)
744late_initcall(PVRCore_Init); 765module_init(PVRCore_Init);
745module_exit(PVRCore_Cleanup); 766module_exit(PVRCore_Cleanup);
746#endif 767#endif
diff --git a/drivers/gpu/pvr/omap4/sysconfig.c b/drivers/gpu/pvr/omap4/sysconfig.c
index f08bf8e13fc..5c82be77d46 100644
--- a/drivers/gpu/pvr/omap4/sysconfig.c
+++ b/drivers/gpu/pvr/omap4/sysconfig.c
@@ -24,28 +24,18 @@
24 * 24 *
25 ******************************************************************************/ 25 ******************************************************************************/
26 26
27#include "sysconfig.h"
27#include "services_headers.h" 28#include "services_headers.h"
28#include "kerneldisplay.h" 29#include "kerneldisplay.h"
29#include "oemfuncs.h" 30#include "oemfuncs.h"
30#include "sgxinfo.h" 31#include "sgxinfo.h"
31#include "sgxinfokm.h" 32#include "sgxinfokm.h"
32#include "syslocal.h" 33#include "syslocal.h"
33#include "sysconfig.h"
34
35#include <linux/platform_device.h>
36#include <plat/omap_device.h>
37#include <plat/omap-pm.h>
38 34
39#include "ocpdefs.h" 35#include "ocpdefs.h"
40 36
41#if !defined(NO_HARDWARE) && \ 37#if defined(LDM_PLATFORM) && !defined(PVR_DRI_DRM_NOT_PCI)
42 defined(SYS_USING_INTERRUPTS) && \ 38#include <plat/omap_device.h>
43 defined(SGX540)
44#define SGX_OCP_REGS_ENABLED
45#endif
46
47#if defined(LDM_PLATFORM) && !defined(SUPPORT_DRI_DRM)
48extern struct platform_device *gpsPVRLDMDev;
49#endif 39#endif
50 40
51SYS_DATA* gpsSysData = (SYS_DATA*)IMG_NULL; 41SYS_DATA* gpsSysData = (SYS_DATA*)IMG_NULL;
@@ -60,10 +50,14 @@ static PVRSRV_DEVICE_NODE *gpsSGXDevNode;
60 50
61#define DEVICE_SGX_INTERRUPT (1 << 0) 51#define DEVICE_SGX_INTERRUPT (1 << 0)
62 52
63#if defined(NO_HARDWARE) 53#if defined(NO_HARDWARE) || defined(SGX_OCP_REGS_ENABLED)
64static IMG_CPU_VIRTADDR gsSGXRegsCPUVAddr; 54static IMG_CPU_VIRTADDR gsSGXRegsCPUVAddr;
65#endif 55#endif
66 56
57#if defined(LDM_PLATFORM) && !defined(PVR_DRI_DRM_NOT_PCI)
58extern struct platform_device *gpsPVRLDMDev;
59#endif
60
67IMG_UINT32 PVRSRV_BridgeDispatchKM(IMG_UINT32 Ioctl, 61IMG_UINT32 PVRSRV_BridgeDispatchKM(IMG_UINT32 Ioctl,
68 IMG_BYTE *pInBuf, 62 IMG_BYTE *pInBuf,
69 IMG_UINT32 InBufLen, 63 IMG_UINT32 InBufLen,
@@ -73,25 +67,19 @@ IMG_UINT32 PVRSRV_BridgeDispatchKM(IMG_UINT32 Ioctl,
73 67
74#if defined(SGX_OCP_REGS_ENABLED) 68#if defined(SGX_OCP_REGS_ENABLED)
75 69
76#define SYS_OMAP4430_OCP_REGS_SYS_PHYS_BASE (SYS_OMAP4430_SGX_REGS_SYS_PHYS_BASE + EUR_CR_OCP_REVISION)
77#define SYS_OMAP4430_OCP_REGS_SIZE 0x110
78
79static IMG_CPU_VIRTADDR gpvOCPRegsLinAddr; 70static IMG_CPU_VIRTADDR gpvOCPRegsLinAddr;
80 71
81static PVRSRV_ERROR EnableSGXClocksWrap(SYS_DATA *psSysData) 72static PVRSRV_ERROR EnableSGXClocksWrap(SYS_DATA *psSysData)
82{ 73{
83 PVRSRV_ERROR eError = EnableSGXClocks(psSysData); 74 PVRSRV_ERROR eError = EnableSGXClocks(psSysData);
84 75
76#if !defined(SGX_OCP_NO_INT_BYPASS)
85 if(eError == PVRSRV_OK) 77 if(eError == PVRSRV_OK)
86 { 78 {
87 OSWriteHWReg(gpvOCPRegsLinAddr, 79 OSWriteHWReg(gpvOCPRegsLinAddr, EUR_CR_OCP_SYSCONFIG, 0x14);
88 EUR_CR_OCP_SYSCONFIG - EUR_CR_OCP_REVISION, 80 OSWriteHWReg(gpvOCPRegsLinAddr, EUR_CR_OCP_DEBUG_CONFIG, EUR_CR_OCP_DEBUG_CONFIG_THALIA_INT_BYPASS_MASK);
89 0x14);
90 OSWriteHWReg(gpvOCPRegsLinAddr,
91 EUR_CR_OCP_DEBUG_CONFIG - EUR_CR_OCP_REVISION,
92 EUR_CR_OCP_DEBUG_CONFIG_THALIA_INT_BYPASS_MASK);
93 } 81 }
94 82#endif
95 return eError; 83 return eError;
96} 84}
97 85
@@ -112,7 +100,11 @@ static INLINE PVRSRV_ERROR EnableSystemClocksWrap(SYS_DATA *psSysData)
112 if(eError == PVRSRV_OK) 100 if(eError == PVRSRV_OK)
113 { 101 {
114 102
115 EnableSGXClocksWrap(psSysData); 103 eError = EnableSGXClocksWrap(psSysData);
104 if (eError != PVRSRV_OK)
105 {
106 DisableSystemClocks(psSysData);
107 }
116 } 108 }
117#endif 109#endif
118 110
@@ -124,6 +116,11 @@ static PVRSRV_ERROR SysLocateDevices(SYS_DATA *psSysData)
124#if defined(NO_HARDWARE) 116#if defined(NO_HARDWARE)
125 PVRSRV_ERROR eError; 117 PVRSRV_ERROR eError;
126 IMG_CPU_PHYADDR sCpuPAddr; 118 IMG_CPU_PHYADDR sCpuPAddr;
119#else
120#if defined(PVR_LINUX_DYNAMIC_SGX_RESOURCE_INFO)
121 struct resource *dev_res;
122 int dev_irq;
123#endif
127#endif 124#endif
128 125
129 PVR_UNREFERENCED_PARAMETER(psSysData); 126 PVR_UNREFERENCED_PARAMETER(psSysData);
@@ -134,7 +131,9 @@ static PVRSRV_ERROR SysLocateDevices(SYS_DATA *psSysData)
134#if defined(NO_HARDWARE) 131#if defined(NO_HARDWARE)
135 132
136 133
137 eError = OSBaseAllocContigMemory(SYS_OMAP4430_SGX_REGS_SIZE, 134 gsSGXDeviceMap.ui32RegsSize = SYS_OMAP4430_SGX_REGS_SIZE;
135
136 eError = OSBaseAllocContigMemory(gsSGXDeviceMap.ui32RegsSize,
138 &gsSGXRegsCPUVAddr, 137 &gsSGXRegsCPUVAddr,
139 &sCpuPAddr); 138 &sCpuPAddr);
140 if(eError != PVRSRV_OK) 139 if(eError != PVRSRV_OK)
@@ -143,7 +142,6 @@ static PVRSRV_ERROR SysLocateDevices(SYS_DATA *psSysData)
143 } 142 }
144 gsSGXDeviceMap.sRegsCpuPBase = sCpuPAddr; 143 gsSGXDeviceMap.sRegsCpuPBase = sCpuPAddr;
145 gsSGXDeviceMap.sRegsSysPBase = SysCpuPAddrToSysPAddr(gsSGXDeviceMap.sRegsCpuPBase); 144 gsSGXDeviceMap.sRegsSysPBase = SysCpuPAddrToSysPAddr(gsSGXDeviceMap.sRegsCpuPBase);
146 gsSGXDeviceMap.ui32RegsSize = SYS_OMAP4430_SGX_REGS_SIZE;
147#if defined(__linux__) 145#if defined(__linux__)
148 146
149 gsSGXDeviceMap.pvRegsCpuVBase = gsSGXRegsCPUVAddr; 147 gsSGXDeviceMap.pvRegsCpuVBase = gsSGXRegsCPUVAddr;
@@ -152,7 +150,7 @@ static PVRSRV_ERROR SysLocateDevices(SYS_DATA *psSysData)
152 gsSGXDeviceMap.pvRegsCpuVBase = IMG_NULL; 150 gsSGXDeviceMap.pvRegsCpuVBase = IMG_NULL;
153#endif 151#endif
154 152
155 OSMemSet(gsSGXRegsCPUVAddr, 0, SYS_OMAP4430_SGX_REGS_SIZE); 153 OSMemSet(gsSGXRegsCPUVAddr, 0, gsSGXDeviceMap.ui32RegsSize);
156 154
157 155
158 156
@@ -160,13 +158,56 @@ static PVRSRV_ERROR SysLocateDevices(SYS_DATA *psSysData)
160 gsSGXDeviceMap.ui32IRQ = 0; 158 gsSGXDeviceMap.ui32IRQ = 0;
161 159
162#else 160#else
161#if defined(PVR_LINUX_DYNAMIC_SGX_RESOURCE_INFO)
162
163 dev_res = platform_get_resource(gpsPVRLDMDev, IORESOURCE_MEM, 0);
164 if (dev_res == NULL)
165 {
166 PVR_DPF((PVR_DBG_ERROR, "%s: platform_get_resource failed", __FUNCTION__));
167 return PVRSRV_ERROR_INVALID_DEVICE;
168 }
169
170 dev_irq = platform_get_irq(gpsPVRLDMDev, 0);
171 if (dev_irq < 0)
172 {
173 PVR_DPF((PVR_DBG_ERROR, "%s: platform_get_irq failed (%d)", __FUNCTION__, -dev_irq));
174 return PVRSRV_ERROR_INVALID_DEVICE;
175 }
176
177 gsSGXDeviceMap.sRegsSysPBase.uiAddr = dev_res->start;
178 gsSGXDeviceMap.sRegsCpuPBase =
179 SysSysPAddrToCpuPAddr(gsSGXDeviceMap.sRegsSysPBase);
180 PVR_TRACE(("SGX register base: 0x%lx", (unsigned long)gsSGXDeviceMap.sRegsCpuPBase.uiAddr));
163 181
182 gsSGXDeviceMap.ui32RegsSize = (unsigned int)(dev_res->end - dev_res->start);
183 PVR_TRACE(("SGX register size: %d",gsSGXDeviceMap.ui32RegsSize));
184
185 gsSGXDeviceMap.ui32IRQ = dev_irq;
186 PVR_TRACE(("SGX IRQ: %d", gsSGXDeviceMap.ui32IRQ));
187#else
164 gsSGXDeviceMap.sRegsSysPBase.uiAddr = SYS_OMAP4430_SGX_REGS_SYS_PHYS_BASE; 188 gsSGXDeviceMap.sRegsSysPBase.uiAddr = SYS_OMAP4430_SGX_REGS_SYS_PHYS_BASE;
165 gsSGXDeviceMap.sRegsCpuPBase = SysSysPAddrToCpuPAddr(gsSGXDeviceMap.sRegsSysPBase); 189 gsSGXDeviceMap.sRegsCpuPBase = SysSysPAddrToCpuPAddr(gsSGXDeviceMap.sRegsSysPBase);
166 gsSGXDeviceMap.ui32RegsSize = SYS_OMAP4430_SGX_REGS_SIZE; 190 gsSGXDeviceMap.ui32RegsSize = SYS_OMAP4430_SGX_REGS_SIZE;
167 191
168 gsSGXDeviceMap.ui32IRQ = SYS_OMAP4430_SGX_IRQ; 192 gsSGXDeviceMap.ui32IRQ = SYS_OMAP4430_SGX_IRQ;
169 193
194#endif
195#if defined(SGX_OCP_REGS_ENABLED)
196 gsSGXRegsCPUVAddr = OSMapPhysToLin(gsSGXDeviceMap.sRegsCpuPBase,
197 gsSGXDeviceMap.ui32RegsSize,
198 PVRSRV_HAP_UNCACHED|PVRSRV_HAP_KERNEL_ONLY,
199 IMG_NULL);
200
201 if (gsSGXRegsCPUVAddr == IMG_NULL)
202 {
203 PVR_DPF((PVR_DBG_ERROR,"SysLocateDevices: Failed to map SGX registers"));
204 return PVRSRV_ERROR_BAD_MAPPING;
205 }
206
207
208 gsSGXDeviceMap.pvRegsCpuVBase = gsSGXRegsCPUVAddr;
209 gpvOCPRegsLinAddr = gsSGXRegsCPUVAddr;
210#endif
170#endif 211#endif
171 212
172#if defined(PDUMP) 213#if defined(PDUMP)
@@ -184,7 +225,7 @@ static PVRSRV_ERROR SysLocateDevices(SYS_DATA *psSysData)
184} 225}
185 226
186 227
187IMG_CHAR *SysCreateVersionString(IMG_CPU_PHYADDR sRegRegion) 228static IMG_CHAR *SysCreateVersionString(void)
188{ 229{
189 static IMG_CHAR aszVersionString[100]; 230 static IMG_CHAR aszVersionString[100];
190 SYS_DATA *psSysData; 231 SYS_DATA *psSysData;
@@ -193,8 +234,8 @@ IMG_CHAR *SysCreateVersionString(IMG_CPU_PHYADDR sRegRegion)
193#if !defined(NO_HARDWARE) 234#if !defined(NO_HARDWARE)
194 IMG_VOID *pvRegsLinAddr; 235 IMG_VOID *pvRegsLinAddr;
195 236
196 pvRegsLinAddr = OSMapPhysToLin(sRegRegion, 237 pvRegsLinAddr = OSMapPhysToLin(gsSGXDeviceMap.sRegsCpuPBase,
197 SYS_OMAP4430_SGX_REGS_SIZE, 238 gsSGXDeviceMap.ui32RegsSize,
198 PVRSRV_HAP_UNCACHED|PVRSRV_HAP_KERNEL_ONLY, 239 PVRSRV_HAP_UNCACHED|PVRSRV_HAP_KERNEL_ONLY,
199 IMG_NULL); 240 IMG_NULL);
200 if(!pvRegsLinAddr) 241 if(!pvRegsLinAddr)
@@ -286,17 +327,6 @@ PVRSRV_ERROR SysInitialise(IMG_VOID)
286 return eError; 327 return eError;
287 } 328 }
288 329
289#if !defined(PVR_NO_OMAP_TIMER)
290 TimerRegPhysBase.uiAddr = SYS_OMAP4430_GP11TIMER_REGS_SYS_PHYS_BASE;
291 gpsSysData->pvSOCTimerRegisterKM = IMG_NULL;
292 gpsSysData->hSOCTimerRegisterOSMemHandle = 0;
293 OSReservePhys(TimerRegPhysBase,
294 4,
295 PVRSRV_HAP_MULTI_PROCESS|PVRSRV_HAP_UNCACHED,
296 (IMG_VOID **)&gpsSysData->pvSOCTimerRegisterKM,
297 &gpsSysData->hSOCTimerRegisterOSMemHandle);
298#endif
299
300#if !defined(SGX_DYNAMIC_TIMING_INFO) 330#if !defined(SGX_DYNAMIC_TIMING_INFO)
301 331
302 psTimingInfo = &gsSGXDeviceMap.sTimingInfo; 332 psTimingInfo = &gsSGXDeviceMap.sTimingInfo;
@@ -329,28 +359,6 @@ PVRSRV_ERROR SysInitialise(IMG_VOID)
329 } 359 }
330 SYS_SPECIFIC_DATA_SET(&gsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_LOCATEDEV); 360 SYS_SPECIFIC_DATA_SET(&gsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_LOCATEDEV);
331 361
332#if defined(SGX_OCP_REGS_ENABLED)
333 {
334 IMG_SYS_PHYADDR sOCPRegsSysPBase;
335 IMG_CPU_PHYADDR sOCPRegsCpuPBase;
336
337 sOCPRegsSysPBase.uiAddr = SYS_OMAP4430_OCP_REGS_SYS_PHYS_BASE;
338 sOCPRegsCpuPBase = SysSysPAddrToCpuPAddr(sOCPRegsSysPBase);
339
340 gpvOCPRegsLinAddr = OSMapPhysToLin(sOCPRegsCpuPBase,
341 SYS_OMAP4430_OCP_REGS_SIZE,
342 PVRSRV_HAP_UNCACHED|PVRSRV_HAP_KERNEL_ONLY,
343 IMG_NULL);
344
345 if (gpvOCPRegsLinAddr == IMG_NULL)
346 {
347 PVR_DPF((PVR_DBG_ERROR,"SysInitialise: Failed to map OCP registers"));
348 return PVRSRV_ERROR_BAD_MAPPING;
349 }
350 SYS_SPECIFIC_DATA_SET(&gsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_OCPREGS);
351 }
352#endif
353
354 eError = SysPMRuntimeRegister(); 362 eError = SysPMRuntimeRegister();
355 if (eError != PVRSRV_OK) 363 if (eError != PVRSRV_OK)
356 { 364 {
@@ -419,8 +427,10 @@ PVRSRV_ERROR SysInitialise(IMG_VOID)
419 psDeviceNode = psDeviceNode->psNext; 427 psDeviceNode = psDeviceNode->psNext;
420 } 428 }
421 429
430#if defined(LDM_PLATFORM) && !defined(PVR_DRI_DRM_NOT_PCI)
422 omap_device_set_rate(&gpsPVRLDMDev->dev, 431 omap_device_set_rate(&gpsPVRLDMDev->dev,
423 &gpsPVRLDMDev->dev, SYS_SGX_CLOCK_SPEED); 432 &gpsPVRLDMDev->dev, SYS_SGX_CLOCK_SPEED);
433#endif
424 434
425 eError = EnableSystemClocksWrap(gpsSysData); 435 eError = EnableSystemClocksWrap(gpsSysData);
426 if (eError != PVRSRV_OK) 436 if (eError != PVRSRV_OK)
@@ -457,6 +467,24 @@ PVRSRV_ERROR SysInitialise(IMG_VOID)
457 DisableSGXClocks(gpsSysData); 467 DisableSGXClocks(gpsSysData);
458#endif 468#endif
459 469
470#if !defined(PVR_NO_OMAP_TIMER)
471#if defined(PVR_OMAP_TIMER_BASE_IN_SYS_SPEC_DATA)
472 TimerRegPhysBase = gsSysSpecificData.sTimerRegPhysBase;
473#else
474 TimerRegPhysBase.uiAddr = SYS_OMAP4430_GP11TIMER_REGS_SYS_PHYS_BASE;
475#endif
476 gpsSysData->pvSOCTimerRegisterKM = IMG_NULL;
477 gpsSysData->hSOCTimerRegisterOSMemHandle = 0;
478 if (TimerRegPhysBase.uiAddr != 0)
479 {
480 OSReservePhys(TimerRegPhysBase,
481 4,
482 PVRSRV_HAP_MULTI_PROCESS|PVRSRV_HAP_UNCACHED,
483 (IMG_VOID **)&gpsSysData->pvSOCTimerRegisterKM,
484 &gpsSysData->hSOCTimerRegisterOSMemHandle);
485 }
486#endif
487
460 return PVRSRV_OK; 488 return PVRSRV_OK;
461} 489}
462 490
@@ -495,14 +523,14 @@ PVRSRV_ERROR SysFinalise(IMG_VOID)
495 523
496#if defined(__linux__) 524#if defined(__linux__)
497 525
498 gpsSysData->pszVersionString = SysCreateVersionString(gsSGXDeviceMap.sRegsCpuPBase); 526 gpsSysData->pszVersionString = SysCreateVersionString();
499 if (!gpsSysData->pszVersionString) 527 if (!gpsSysData->pszVersionString)
500 { 528 {
501 PVR_DPF((PVR_DBG_ERROR,"SysFinalise: Failed to create a system version string")); 529 PVR_DPF((PVR_DBG_ERROR,"SysFinalise: Failed to create a system version string"));
502 } 530 }
503 else 531 else
504 { 532 {
505 PVR_DPF((PVR_DBG_WARNING, "SysFinalise: Version string: %s", gpsSysData->pszVersionString)); 533 PVR_TRACE(("SysFinalise: Version string: %s", gpsSysData->pszVersionString));
506 } 534 }
507#endif 535#endif
508 536
@@ -521,6 +549,14 @@ PVRSRV_ERROR SysDeinitialise (SYS_DATA *psSysData)
521{ 549{
522 PVRSRV_ERROR eError; 550 PVRSRV_ERROR eError;
523 551
552 if(gpsSysData->pvSOCTimerRegisterKM)
553 {
554 OSUnReservePhys(gpsSysData->pvSOCTimerRegisterKM,
555 4,
556 PVRSRV_HAP_MULTI_PROCESS|PVRSRV_HAP_UNCACHED,
557 gpsSysData->hSOCTimerRegisterOSMemHandle);
558 }
559
524#if defined(SYS_USING_INTERRUPTS) 560#if defined(SYS_USING_INTERRUPTS)
525 if (SYS_SPECIFIC_DATA_TEST(gpsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_LISR)) 561 if (SYS_SPECIFIC_DATA_TEST(gpsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_LISR))
526 { 562 {
@@ -571,22 +607,11 @@ PVRSRV_ERROR SysDeinitialise (SYS_DATA *psSysData)
571 if (eError != PVRSRV_OK) 607 if (eError != PVRSRV_OK)
572 { 608 {
573 PVR_DPF((PVR_DBG_ERROR,"SysDeinitialise: Failed to unregister with OSPM!")); 609 PVR_DPF((PVR_DBG_ERROR,"SysDeinitialise: Failed to unregister with OSPM!"));
574 (IMG_VOID)SysDeinitialise(gpsSysData);
575 gpsSysData = IMG_NULL; 610 gpsSysData = IMG_NULL;
576 return eError; 611 return eError;
577 } 612 }
578 } 613 }
579 614
580#if defined(SGX_OCP_REGS_ENABLED)
581 if (SYS_SPECIFIC_DATA_TEST(gpsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_OCPREGS))
582 {
583 OSUnMapPhysToLin(gpvOCPRegsLinAddr,
584 SYS_OMAP4430_OCP_REGS_SIZE,
585 PVRSRV_HAP_UNCACHED|PVRSRV_HAP_KERNEL_ONLY,
586 IMG_NULL);
587 }
588#endif
589
590 615
591 616
592 if (SYS_SPECIFIC_DATA_TEST(gpsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_SYSCLOCKS)) 617 if (SYS_SPECIFIC_DATA_TEST(gpsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_SYSCLOCKS))
@@ -604,21 +629,26 @@ PVRSRV_ERROR SysDeinitialise (SYS_DATA *psSysData)
604 } 629 }
605 } 630 }
606 631
607 if(gpsSysData->pvSOCTimerRegisterKM)
608 {
609 OSUnReservePhys(gpsSysData->pvSOCTimerRegisterKM,
610 4,
611 PVRSRV_HAP_MULTI_PROCESS|PVRSRV_HAP_UNCACHED,
612 gpsSysData->hSOCTimerRegisterOSMemHandle);
613 }
614
615 SysDeinitialiseCommon(gpsSysData); 632 SysDeinitialiseCommon(gpsSysData);
616 633
617#if defined(NO_HARDWARE) 634#if defined(NO_HARDWARE) || defined(SGX_OCP_REGS_ENABLED)
618 if(SYS_SPECIFIC_DATA_TEST(gpsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_LOCATEDEV)) 635 if(gsSGXRegsCPUVAddr != IMG_NULL)
619 { 636 {
637#if defined(NO_HARDWARE)
620 638
621 OSBaseFreeContigMemory(SYS_OMAP4430_SGX_REGS_SIZE, gsSGXRegsCPUVAddr, gsSGXDeviceMap.sRegsCpuPBase); 639 OSBaseFreeContigMemory(SYS_OMAP4430_SGX_REGS_SIZE, gsSGXRegsCPUVAddr, gsSGXDeviceMap.sRegsCpuPBase);
640#else
641#if defined(SGX_OCP_REGS_ENABLED)
642 OSUnMapPhysToLin(gsSGXRegsCPUVAddr,
643 gsSGXDeviceMap.ui32RegsSize,
644 PVRSRV_HAP_UNCACHED|PVRSRV_HAP_KERNEL_ONLY,
645 IMG_NULL);
646
647 gpvOCPRegsLinAddr = IMG_NULL;
648#endif
649#endif
650 gsSGXRegsCPUVAddr = IMG_NULL;
651 gsSGXDeviceMap.pvRegsCpuVBase = gsSGXRegsCPUVAddr;
622 } 652 }
623#endif 653#endif
624 654
@@ -740,14 +770,41 @@ IMG_UINT32 SysGetInterruptSource(SYS_DATA *psSysData,
740 770
741IMG_VOID SysClearInterrupts(SYS_DATA* psSysData, IMG_UINT32 ui32ClearBits) 771IMG_VOID SysClearInterrupts(SYS_DATA* psSysData, IMG_UINT32 ui32ClearBits)
742{ 772{
743 PVR_UNREFERENCED_PARAMETER(psSysData);
744 PVR_UNREFERENCED_PARAMETER(ui32ClearBits); 773 PVR_UNREFERENCED_PARAMETER(ui32ClearBits);
745 774#if defined(NO_HARDWARE)
775 PVR_UNREFERENCED_PARAMETER(psSysData);
776#else
777#if defined(SGX_OCP_NO_INT_BYPASS)
778 OSWriteHWReg(gpvOCPRegsLinAddr, EUR_CR_OCP_IRQSTATUS_2, 0x1);
779#endif
746 780
747 OSReadHWReg(((PVRSRV_SGXDEV_INFO *)gpsSGXDevNode->pvDevice)->pvRegsBaseKM, 781 OSReadHWReg(((PVRSRV_SGXDEV_INFO *)gpsSGXDevNode->pvDevice)->pvRegsBaseKM, EUR_CR_EVENT_HOST_CLEAR);
748 EUR_CR_EVENT_HOST_CLEAR); 782#endif
749} 783}
750 784
785#if defined(SGX_OCP_NO_INT_BYPASS)
786IMG_VOID SysEnableSGXInterrupts(SYS_DATA *psSysData)
787{
788 SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *)psSysData->pvSysSpecificData;
789 if (SYS_SPECIFIC_DATA_TEST(psSysSpecData, SYS_SPECIFIC_DATA_ENABLE_LISR) && !SYS_SPECIFIC_DATA_TEST(psSysSpecData, SYS_SPECIFIC_DATA_IRQ_ENABLED))
790 {
791 OSWriteHWReg(gpvOCPRegsLinAddr, EUR_CR_OCP_IRQSTATUS_2, 0x1);
792 OSWriteHWReg(gpvOCPRegsLinAddr, EUR_CR_OCP_IRQENABLE_SET_2, 0x1);
793 SYS_SPECIFIC_DATA_SET(psSysSpecData, SYS_SPECIFIC_DATA_IRQ_ENABLED);
794 }
795}
796
797IMG_VOID SysDisableSGXInterrupts(SYS_DATA *psSysData)
798{
799 SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *)psSysData->pvSysSpecificData;
800
801 if (SYS_SPECIFIC_DATA_TEST(psSysSpecData, SYS_SPECIFIC_DATA_IRQ_ENABLED))
802 {
803 OSWriteHWReg(gpvOCPRegsLinAddr, EUR_CR_OCP_IRQENABLE_CLR_2, 0x1);
804 SYS_SPECIFIC_DATA_CLEAR(psSysSpecData, SYS_SPECIFIC_DATA_IRQ_ENABLED);
805 }
806}
807#endif
751 808
752PVRSRV_ERROR SysSystemPrePowerState(PVRSRV_SYS_POWER_STATE eNewPowerState) 809PVRSRV_ERROR SysSystemPrePowerState(PVRSRV_SYS_POWER_STATE eNewPowerState)
753{ 810{
diff --git a/drivers/gpu/pvr/omap4/sysconfig.h b/drivers/gpu/pvr/omap4/sysconfig.h
index 46930b54da9..8e84def99c0 100644
--- a/drivers/gpu/pvr/omap4/sysconfig.h
+++ b/drivers/gpu/pvr/omap4/sysconfig.h
@@ -27,8 +27,6 @@
27#if !defined(__SOCCONFIG_H__) 27#if !defined(__SOCCONFIG_H__)
28#define __SOCCONFIG_H__ 28#define __SOCCONFIG_H__
29 29
30#include "syscommon.h"
31
32#define VS_PRODUCT_NAME "OMAP4" 30#define VS_PRODUCT_NAME "OMAP4"
33 31
34#if defined(SGX540) && (SGX_CORE_REV == 120) 32#if defined(SGX540) && (SGX_CORE_REV == 120)
@@ -51,9 +49,13 @@
51 49
52#define SYS_OMAP4430_SGX_IRQ 53 50#define SYS_OMAP4430_SGX_IRQ 53
53 51
54#define SYS_OMAP4430_GP11TIMER_ENABLE_SYS_PHYS_BASE 0x48088038 52#define SYS_OMAP4430_GP11TIMER_ENABLE_SYS_PHYS_BASE 0x48088038
55#define SYS_OMAP4430_GP11TIMER_REGS_SYS_PHYS_BASE 0x4808803C 53#define SYS_OMAP4430_GP11TIMER_REGS_SYS_PHYS_BASE 0x4808803C
56#define SYS_OMAP4430_GP11TIMER_TSICR_SYS_PHYS_BASE 0x48088054 54#define SYS_OMAP4430_GP11TIMER_TSICR_SYS_PHYS_BASE 0x48088054
55
56#if defined(__linux__)
57#define SYS_SGX_DEV_NAME "omap_gpu"
58#endif
57 59
58 60
59#endif 61#endif
diff --git a/drivers/gpu/pvr/omap4/syslocal.h b/drivers/gpu/pvr/omap4/syslocal.h
index bc9a078fc43..e07c51fda75 100644
--- a/drivers/gpu/pvr/omap4/syslocal.h
+++ b/drivers/gpu/pvr/omap4/syslocal.h
@@ -48,16 +48,52 @@
48#endif 48#endif
49#endif 49#endif
50 50
51
52#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35))
53#if !defined(LDM_PLATFORM)
54#error "LDM_PLATFORM must be set"
55#endif
56#define PVR_LINUX_DYNAMIC_SGX_RESOURCE_INFO
57#include <linux/platform_device.h>
58#endif
59
60#if ((defined(DEBUG) || defined(TIMING)) && \
61 (LINUX_VERSION_CODE == KERNEL_VERSION(2,6,34))) && \
62 !defined(PVR_NO_OMAP_TIMER)
63#define PVR_OMAP4_TIMING_PRCM
64#endif
65
66#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35))
67#include <plat/gpu.h>
68#if !defined(PVR_NO_OMAP_TIMER)
69#define PVR_OMAP_USE_DM_TIMER_API
70#include <plat/dmtimer.h>
71#endif
72#endif
73
74#if !defined(PVR_NO_OMAP_TIMER)
75#define PVR_OMAP_TIMER_BASE_IN_SYS_SPEC_DATA
76#endif
51#endif 77#endif
52 78
79#if !defined(NO_HARDWARE) && \
80 defined(SYS_USING_INTERRUPTS) && \
81 defined(SGX540)
82#define SGX_OCP_REGS_ENABLED
83#endif
84
85#if defined(__linux__)
86#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)) && defined(SGX_OCP_REGS_ENABLED)
87#define SGX_OCP_NO_INT_BYPASS
88#endif
89#endif
90
53#if defined (__cplusplus) 91#if defined (__cplusplus)
54extern "C" { 92extern "C" {
55#endif 93#endif
56 94
57 95
58 96
59IMG_CHAR *SysCreateVersionString(IMG_CPU_PHYADDR sRegRegion);
60
61IMG_VOID DisableSystemClocks(SYS_DATA *psSysData); 97IMG_VOID DisableSystemClocks(SYS_DATA *psSysData);
62PVRSRV_ERROR EnableSystemClocks(SYS_DATA *psSysData); 98PVRSRV_ERROR EnableSystemClocks(SYS_DATA *psSysData);
63 99
@@ -78,6 +114,9 @@ PVRSRV_ERROR EnableSGXClocks(SYS_DATA *psSysData);
78#define SYS_SPECIFIC_DATA_PM_DISABLE_SYSCLOCKS 0x00000400 114#define SYS_SPECIFIC_DATA_PM_DISABLE_SYSCLOCKS 0x00000400
79#define SYS_SPECIFIC_DATA_ENABLE_OCPREGS 0x00000800 115#define SYS_SPECIFIC_DATA_ENABLE_OCPREGS 0x00000800
80#define SYS_SPECIFIC_DATA_ENABLE_PM_RUNTIME 0x00001000 116#define SYS_SPECIFIC_DATA_ENABLE_PM_RUNTIME 0x00001000
117#if defined(SGX_OCP_REGS_ENABLED) && defined(SGX_OCP_NO_INT_BYPASS)
118#define SYS_SPECIFIC_DATA_IRQ_ENABLED 0x00002000
119#endif
81 120
82#define SYS_SPECIFIC_DATA_SET(psSysSpecData, flag) ((IMG_VOID)((psSysSpecData)->ui32SysSpecificData |= (flag))) 121#define SYS_SPECIFIC_DATA_SET(psSysSpecData, flag) ((IMG_VOID)((psSysSpecData)->ui32SysSpecificData |= (flag)))
83 122
@@ -90,6 +129,9 @@ typedef struct _SYS_SPECIFIC_DATA_TAG_
90 IMG_UINT32 ui32SysSpecificData; 129 IMG_UINT32 ui32SysSpecificData;
91 PVRSRV_DEVICE_NODE *psSGXDevNode; 130 PVRSRV_DEVICE_NODE *psSGXDevNode;
92 IMG_BOOL bSGXInitComplete; 131 IMG_BOOL bSGXInitComplete;
132#if defined(PVR_OMAP_TIMER_BASE_IN_SYS_SPEC_DATA)
133 IMG_CPU_PHYADDR sTimerRegPhysBase;
134#endif
93#if !defined(__linux__) 135#if !defined(__linux__)
94 IMG_BOOL bSGXClocksEnabled; 136 IMG_BOOL bSGXClocksEnabled;
95#endif 137#endif
@@ -107,19 +149,26 @@ typedef struct _SYS_SPECIFIC_DATA_TAG_
107 atomic_t sNotifyLockCPU; 149 atomic_t sNotifyLockCPU;
108 IMG_BOOL bCallVDD2PostFunc; 150 IMG_BOOL bCallVDD2PostFunc;
109#endif 151#endif
110 struct clk *psCORE_CK;
111 struct clk *psSGX_FCK;
112 struct clk *psSGX_ICK;
113 struct clk *psMPU_CK;
114#if defined(DEBUG) || defined(TIMING) 152#if defined(DEBUG) || defined(TIMING)
115 struct clk *psGPT11_FCK; 153 struct clk *psGPT11_FCK;
116 struct clk *psGPT11_ICK; 154 struct clk *psGPT11_ICK;
117#endif 155#endif
156#if defined(PVR_OMAP_USE_DM_TIMER_API)
157 struct omap_dm_timer *psGPTimer;
158#endif
118#endif 159#endif
119} SYS_SPECIFIC_DATA; 160} SYS_SPECIFIC_DATA;
120 161
121extern SYS_SPECIFIC_DATA *gpsSysSpecificData; 162extern SYS_SPECIFIC_DATA *gpsSysSpecificData;
122 163
164#if defined(SGX_OCP_REGS_ENABLED) && defined(SGX_OCP_NO_INT_BYPASS)
165IMG_VOID SysEnableSGXInterrupts(SYS_DATA* psSysData);
166IMG_VOID SysDisableSGXInterrupts(SYS_DATA* psSysData);
167#else
168#define SysEnableSGXInterrupts(psSysData)
169#define SysDisableSGXInterrupts(psSysData)
170#endif
171
123#if defined(SYS_CUSTOM_POWERLOCK_WRAP) 172#if defined(SYS_CUSTOM_POWERLOCK_WRAP)
124IMG_BOOL WrapSystemPowerChange(SYS_SPECIFIC_DATA *psSysSpecData); 173IMG_BOOL WrapSystemPowerChange(SYS_SPECIFIC_DATA *psSysSpecData);
125IMG_VOID UnwrapSystemPowerChange(SYS_SPECIFIC_DATA *psSysSpecData); 174IMG_VOID UnwrapSystemPowerChange(SYS_SPECIFIC_DATA *psSysSpecData);
diff --git a/drivers/gpu/pvr/omap4/sysutils_linux.c b/drivers/gpu/pvr/omap4/sysutils_linux.c
index 52ae877f05e..f7c3ac11424 100644
--- a/drivers/gpu/pvr/omap4/sysutils_linux.c
+++ b/drivers/gpu/pvr/omap4/sysutils_linux.c
@@ -41,16 +41,6 @@
41#include <linux/platform_device.h> 41#include <linux/platform_device.h>
42#include <linux/pm_runtime.h> 42#include <linux/pm_runtime.h>
43 43
44#if !defined(PVR_LINUX_USING_WORKQUEUES)
45#error "PVR_LINUX_USING_WORKQUEUES must be defined"
46#endif
47
48#if ((defined(DEBUG) || defined(TIMING)) && \
49 (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,34))) && \
50 !defined(PVR_NO_OMAP_TIMER)
51#define PVR_OMAP4_TIMING_PRCM
52#endif
53
54#define ONE_MHZ 1000000 44#define ONE_MHZ 1000000
55#define HZ_TO_MHZ(m) ((m) / ONE_MHZ) 45#define HZ_TO_MHZ(m) ((m) / ONE_MHZ)
56 46
@@ -60,7 +50,7 @@
60#define SGX_PARENT_CLOCK "core_ck" 50#define SGX_PARENT_CLOCK "core_ck"
61#endif 51#endif
62 52
63#if defined(LDM_PLATFORM) && !defined(SUPPORT_DRI_DRM) 53#if defined(LDM_PLATFORM) && !defined(PVR_DRI_DRM_NOT_PCI)
64extern struct platform_device *gpsPVRLDMDev; 54extern struct platform_device *gpsPVRLDMDev;
65#endif 55#endif
66 56
@@ -134,17 +124,9 @@ IMG_VOID SysGetSGXTimingInformation(SGX_TIMING_INFORMATION *psTimingInfo)
134{ 124{
135 IMG_UINT32 rate; 125 IMG_UINT32 rate;
136 126
137#if defined(NO_HARDWARE)
138 rate = SYS_SGX_CLOCK_SPEED; 127 rate = SYS_SGX_CLOCK_SPEED;
139#else 128#if !defined(NO_HARDWARE)
140 PVR_ASSERT(atomic_read(&gpsSysSpecificData->sSGXClocksEnabled) != 0); 129 PVR_ASSERT(atomic_read(&gpsSysSpecificData->sSGXClocksEnabled) != 0);
141
142#if defined(OMAP4_PRCM_ENABLE)
143 rate = clk_get_rate(gpsSysSpecificData->psSGX_FCK);
144#else
145 rate = SYS_SGX_CLOCK_SPEED;
146#endif
147 PVR_ASSERT(rate != 0);
148#endif 130#endif
149 psTimingInfo->ui32CoreClockSpeed = rate; 131 psTimingInfo->ui32CoreClockSpeed = rate;
150 psTimingInfo->ui32HWRecoveryFreq = scale_prop_to_SGX_clock(SYS_SGX_HWRECOVERY_TIMEOUT_FREQ, rate); 132 psTimingInfo->ui32HWRecoveryFreq = scale_prop_to_SGX_clock(SYS_SGX_HWRECOVERY_TIMEOUT_FREQ, rate);
@@ -161,11 +143,6 @@ PVRSRV_ERROR EnableSGXClocks(SYS_DATA *psSysData)
161{ 143{
162#if !defined(NO_HARDWARE) 144#if !defined(NO_HARDWARE)
163 SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData; 145 SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
164#if defined(OMAP4_PRCM_ENABLE)
165 long lNewRate;
166 long lRate;
167 IMG_INT res;
168#endif
169 146
170 147
171 if (atomic_read(&psSysSpecData->sSGXClocksEnabled) != 0) 148 if (atomic_read(&psSysSpecData->sSGXClocksEnabled) != 0)
@@ -175,61 +152,18 @@ PVRSRV_ERROR EnableSGXClocks(SYS_DATA *psSysData)
175 152
176 PVR_DPF((PVR_DBG_MESSAGE, "EnableSGXClocks: Enabling SGX Clocks")); 153 PVR_DPF((PVR_DBG_MESSAGE, "EnableSGXClocks: Enabling SGX Clocks"));
177 154
178#if defined(LDM_PLATFORM) && !defined(SUPPORT_DRI_DRM) 155#if defined(LDM_PLATFORM) && !defined(PVR_DRI_DRM_NOT_PCI)
179 pm_runtime_get_sync(&gpsPVRLDMDev->dev);
180#endif
181
182#if defined(OMAP4_PRCM_ENABLE)
183
184#if defined(DEBUG)
185 {
186 IMG_UINT32 rate = clk_get_rate(psSysSpecData->psMPU_CK);
187 PVR_DPF((PVR_DBG_MESSAGE, "EnableSGXClocks: CPU Clock is %dMhz", HZ_TO_MHZ(rate)));
188 }
189#endif
190
191 res = clk_enable(psSysSpecData->psSGX_FCK);
192 if (res < 0)
193 { 156 {
194 PVR_DPF((PVR_DBG_ERROR, "EnableSGXClocks: Couldn't enable SGX functional clock (%d)", res));
195 return PVRSRV_ERROR_UNABLE_TO_ENABLE_CLOCK;
196 }
197 157
198 res = clk_enable(psSysSpecData->psSGX_ICK); 158 int res = pm_runtime_get_sync(&gpsPVRLDMDev->dev);
199 if (res < 0)
200 {
201 PVR_DPF((PVR_DBG_ERROR, "EnableSGXClocks: Couldn't enable SGX interface clock (%d)", res));
202
203 clk_disable(psSysSpecData->psSGX_FCK);
204 return PVRSRV_ERROR_UNABLE_TO_ENABLE_CLOCK;
205 }
206
207 lNewRate = clk_round_rate(psSysSpecData->psSGX_FCK, SYS_SGX_CLOCK_SPEED + ONE_MHZ);
208 if (lNewRate <= 0)
209 {
210 PVR_DPF((PVR_DBG_ERROR, "EnableSGXClocks: Couldn't round SGX functional clock rate"));
211 return PVRSRV_ERROR_UNABLE_TO_ROUND_CLOCK_RATE;
212 }
213
214
215 lRate = clk_get_rate(psSysSpecData->psSGX_FCK);
216 if (lRate != lNewRate)
217 {
218 res = clk_set_rate(psSysSpecData->psSGX_FCK, lNewRate);
219 if (res < 0) 159 if (res < 0)
220 { 160 {
221 PVR_DPF((PVR_DBG_WARNING, "EnableSGXClocks: Couldn't set SGX functional clock rate (%d)", res)); 161 PVR_DPF((PVR_DBG_ERROR, "EnableSGXClocks: pm_runtime_get_sync failed (%d)", -res));
162 return PVRSRV_ERROR_UNABLE_TO_ENABLE_CLOCK;
222 } 163 }
223 } 164 }
224
225#if defined(DEBUG)
226 {
227 IMG_UINT32 rate = clk_get_rate(psSysSpecData->psSGX_FCK);
228 PVR_DPF((PVR_DBG_MESSAGE, "EnableSGXClocks: SGX Functional Clock is %dMhz", HZ_TO_MHZ(rate)));
229 }
230#endif 165#endif
231 166 SysEnableSGXInterrupts(psSysData);
232#endif
233 167
234 168
235 atomic_set(&psSysSpecData->sSGXClocksEnabled, 1); 169 atomic_set(&psSysSpecData->sSGXClocksEnabled, 1);
@@ -254,21 +188,17 @@ IMG_VOID DisableSGXClocks(SYS_DATA *psSysData)
254 188
255 PVR_DPF((PVR_DBG_MESSAGE, "DisableSGXClocks: Disabling SGX Clocks")); 189 PVR_DPF((PVR_DBG_MESSAGE, "DisableSGXClocks: Disabling SGX Clocks"));
256 190
257#if defined(LDM_PLATFORM) && !defined(SUPPORT_DRI_DRM) 191 SysDisableSGXInterrupts(psSysData);
258 pm_runtime_put_sync(&gpsPVRLDMDev->dev);
259#endif
260 192
261#if defined(OMAP4_PRCM_ENABLE) 193#if defined(LDM_PLATFORM) && !defined(PVR_DRI_DRM_NOT_PCI)
262 if (psSysSpecData->psSGX_ICK)
263 { 194 {
264 clk_disable(psSysSpecData->psSGX_ICK); 195 int res = pm_runtime_put_sync(&gpsPVRLDMDev->dev);
265 } 196 if (res < 0)
266 197 {
267 if (psSysSpecData->psSGX_FCK) 198 PVR_DPF((PVR_DBG_ERROR, "DisableSGXClocks: pm_runtime_put_sync failed (%d)", -res));
268 { 199 }
269 clk_disable(psSysSpecData->psSGX_FCK);
270 } 200 }
271#endif 201#endif
272 202
273 203
274 atomic_set(&psSysSpecData->sSGXClocksEnabled, 0); 204 atomic_set(&psSysSpecData->sSGXClocksEnabled, 0);
@@ -278,86 +208,78 @@ IMG_VOID DisableSGXClocks(SYS_DATA *psSysData)
278#endif 208#endif
279} 209}
280 210
281PVRSRV_ERROR EnableSystemClocks(SYS_DATA *psSysData) 211#if (defined(DEBUG) || defined(TIMING)) && !defined(PVR_NO_OMAP_TIMER)
212#if defined(PVR_OMAP_USE_DM_TIMER_API)
213#define GPTIMER_TO_USE 11
214static PVRSRV_ERROR AcquireGPTimer(SYS_SPECIFIC_DATA *psSysSpecData)
282{ 215{
283 SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData; 216 PVR_ASSERT(psSysSpecData->psGPTimer == NULL);
284#if (defined(OMAP4_PRCM_ENABLE) || defined(PVR_OMAP4_TIMING_PRCM))
285 struct clk *psCLK;
286 IMG_INT res;
287#endif
288#if defined(PVR_OMAP4_TIMING_PRCM)
289 struct clk *sys_ck;
290 IMG_INT rate;
291#endif
292 PVRSRV_ERROR eError;
293 217
294#if (defined(DEBUG) || defined(TIMING)) && !defined(PVR_NO_OMAP_TIMER)
295 IMG_CPU_PHYADDR TimerRegPhysBase;
296 IMG_HANDLE hTimerEnable;
297 IMG_UINT32 *pui32TimerEnable;
298#endif
299 218
300 PVR_TRACE(("EnableSystemClocks: Enabling System Clocks")); 219 psSysSpecData->psGPTimer = omap_dm_timer_request_specific(GPTIMER_TO_USE);
220 if (psSysSpecData->psGPTimer == NULL)
221 {
301 222
302 if (!psSysSpecData->bSysClocksOneTimeInit) 223 PVR_DPF((PVR_DBG_WARNING, "%s: omap_dm_timer_request_specific failed", __FUNCTION__));
224 return PVRSRV_ERROR_CLOCK_REQUEST_FAILED;
225 }
226
227
228 omap_dm_timer_set_source(psSysSpecData->psGPTimer, OMAP_TIMER_SRC_SYS_CLK);
229 omap_dm_timer_enable(psSysSpecData->psGPTimer);
230
231
232 omap_dm_timer_set_load_start(psSysSpecData->psGPTimer, 1, 0);
233
234 omap_dm_timer_start(psSysSpecData->psGPTimer);
235
236
237 psSysSpecData->sTimerRegPhysBase.uiAddr = SYS_OMAP4430_GP11TIMER_REGS_SYS_PHYS_BASE;
238
239 return PVRSRV_OK;
240}
241
242static void ReleaseGPTimer(SYS_SPECIFIC_DATA *psSysSpecData)
243{
244 if (psSysSpecData->psGPTimer != NULL)
303 { 245 {
304 mutex_init(&psSysSpecData->sPowerLock);
305 246
306 atomic_set(&psSysSpecData->sSGXClocksEnabled, 0); 247 (void) omap_dm_timer_stop(psSysSpecData->psGPTimer);
307 248
308#if defined(OMAP4_PRCM_ENABLE) 249 omap_dm_timer_disable(psSysSpecData->psGPTimer);
309 psCLK = clk_get(NULL, SGX_PARENT_CLOCK);
310 if (IS_ERR(psCLK))
311 {
312 PVR_DPF((PVR_DBG_ERROR, "EnableSsystemClocks: Couldn't get Core Clock"));
313 goto ExitError;
314 }
315 psSysSpecData->psCORE_CK = psCLK;
316 250
317 psCLK = clk_get(NULL, "sgx_fck"); 251 omap_dm_timer_free(psSysSpecData->psGPTimer);
318 if (IS_ERR(psCLK))
319 {
320 PVR_DPF((PVR_DBG_ERROR, "EnableSsystemClocks: Couldn't get SGX Functional Clock"));
321 goto ExitError;
322 }
323 psSysSpecData->psSGX_FCK = psCLK;
324 252
325 psCLK = clk_get(NULL, "sgx_ick"); 253 psSysSpecData->sTimerRegPhysBase.uiAddr = 0;
326 if (IS_ERR(psCLK))
327 {
328 PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get SGX Interface Clock"));
329 goto ExitError;
330 }
331 psSysSpecData->psSGX_ICK = psCLK;
332 254
333#if defined(DEBUG) 255 psSysSpecData->psGPTimer = NULL;
334 psCLK = clk_get(NULL, "mpu_ck"); 256 }
335 if (IS_ERR(psCLK)) 257
336 { 258}
337 PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get MPU Clock")); 259#else
338 goto ExitError; 260static PVRSRV_ERROR AcquireGPTimer(SYS_SPECIFIC_DATA *psSysSpecData)
339 } 261{
340 psSysSpecData->psMPU_CK = psCLK; 262#if defined(PVR_OMAP4_TIMING_PRCM)
263 struct clk *psCLK;
264 IMG_INT res;
265 struct clk *sys_ck;
266 IMG_INT rate;
341#endif 267#endif
342 res = clk_set_parent(psSysSpecData->psSGX_FCK, psSysSpecData->psCORE_CK); 268 PVRSRV_ERROR eError;
343 if (res < 0)
344 {
345 PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't set SGX parent clock (%d)", res));
346 goto ExitError;
347 }
348#endif
349 269
350 psSysSpecData->bSysClocksOneTimeInit = IMG_TRUE; 270 IMG_CPU_PHYADDR sTimerRegPhysBase;
351 } 271 IMG_HANDLE hTimerEnable;
272 IMG_UINT32 *pui32TimerEnable;
273
274 PVR_ASSERT(psSysSpecData->sTimerRegPhysBase.uiAddr == 0);
352 275
353#if (defined(DEBUG) || defined(TIMING)) && !defined(PVR_NO_OMAP_TIMER)
354#if defined(PVR_OMAP4_TIMING_PRCM) 276#if defined(PVR_OMAP4_TIMING_PRCM)
355 277
356 psCLK = clk_get(NULL, "gpt11_fck"); 278 psCLK = clk_get(NULL, "gpt11_fck");
357 if (IS_ERR(psCLK)) 279 if (IS_ERR(psCLK))
358 { 280 {
359 PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get GPTIMER11 functional clock")); 281 PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get GPTIMER11 functional clock"));
360 goto ExitUnRegisterConstraintNotifications; 282 goto ExitError;
361 } 283 }
362 psSysSpecData->psGPT11_FCK = psCLK; 284 psSysSpecData->psGPT11_FCK = psCLK;
363 285
@@ -365,7 +287,7 @@ PVRSRV_ERROR EnableSystemClocks(SYS_DATA *psSysData)
365 if (IS_ERR(psCLK)) 287 if (IS_ERR(psCLK))
366 { 288 {
367 PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get GPTIMER11 interface clock")); 289 PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get GPTIMER11 interface clock"));
368 goto ExitUnRegisterConstraintNotifications; 290 goto ExitError;
369 } 291 }
370 psSysSpecData->psGPT11_ICK = psCLK; 292 psSysSpecData->psGPT11_ICK = psCLK;
371 293
@@ -373,7 +295,7 @@ PVRSRV_ERROR EnableSystemClocks(SYS_DATA *psSysData)
373 if (IS_ERR(sys_ck)) 295 if (IS_ERR(sys_ck))
374 { 296 {
375 PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get System clock")); 297 PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get System clock"));
376 goto ExitUnRegisterConstraintNotifications; 298 goto ExitError;
377 } 299 }
378 300
379 if(clk_get_parent(psSysSpecData->psGPT11_FCK) != sys_ck) 301 if(clk_get_parent(psSysSpecData->psGPT11_FCK) != sys_ck)
@@ -383,7 +305,7 @@ PVRSRV_ERROR EnableSystemClocks(SYS_DATA *psSysData)
383 if (res < 0) 305 if (res < 0)
384 { 306 {
385 PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't set GPTIMER11 parent clock (%d)", res)); 307 PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't set GPTIMER11 parent clock (%d)", res));
386 goto ExitUnRegisterConstraintNotifications; 308 goto ExitError;
387 } 309 }
388 } 310 }
389 311
@@ -394,7 +316,7 @@ PVRSRV_ERROR EnableSystemClocks(SYS_DATA *psSysData)
394 if (res < 0) 316 if (res < 0)
395 { 317 {
396 PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't enable GPTIMER11 functional clock (%d)", res)); 318 PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't enable GPTIMER11 functional clock (%d)", res));
397 goto ExitUnRegisterConstraintNotifications; 319 goto ExitError;
398 } 320 }
399 321
400 res = clk_enable(psSysSpecData->psGPT11_ICK); 322 res = clk_enable(psSysSpecData->psGPT11_ICK);
@@ -406,8 +328,8 @@ PVRSRV_ERROR EnableSystemClocks(SYS_DATA *psSysData)
406#endif 328#endif
407 329
408 330
409 TimerRegPhysBase.uiAddr = SYS_OMAP4430_GP11TIMER_TSICR_SYS_PHYS_BASE; 331 sTimerRegPhysBase.uiAddr = SYS_OMAP4430_GP11TIMER_TSICR_SYS_PHYS_BASE;
410 pui32TimerEnable = OSMapPhysToLin(TimerRegPhysBase, 332 pui32TimerEnable = OSMapPhysToLin(sTimerRegPhysBase,
411 4, 333 4,
412 PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED, 334 PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
413 &hTimerEnable); 335 &hTimerEnable);
@@ -432,8 +354,8 @@ PVRSRV_ERROR EnableSystemClocks(SYS_DATA *psSysData)
432 hTimerEnable); 354 hTimerEnable);
433 355
434 356
435 TimerRegPhysBase.uiAddr = SYS_OMAP4430_GP11TIMER_ENABLE_SYS_PHYS_BASE; 357 sTimerRegPhysBase.uiAddr = SYS_OMAP4430_GP11TIMER_ENABLE_SYS_PHYS_BASE;
436 pui32TimerEnable = OSMapPhysToLin(TimerRegPhysBase, 358 pui32TimerEnable = OSMapPhysToLin(sTimerRegPhysBase,
437 4, 359 4,
438 PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED, 360 PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
439 &hTimerEnable); 361 &hTimerEnable);
@@ -452,48 +374,36 @@ PVRSRV_ERROR EnableSystemClocks(SYS_DATA *psSysData)
452 PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED, 374 PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
453 hTimerEnable); 375 hTimerEnable);
454 376
455#endif 377 psSysSpecData->sTimerRegPhysBase = sTimerRegPhysBase;
456 378
457 eError = PVRSRV_OK; 379 eError = PVRSRV_OK;
380
458 goto Exit; 381 goto Exit;
459 382
460#if (defined(DEBUG) || defined(TIMING)) && !defined(PVR_NO_OMAP_TIMER)
461ExitDisableGPT11ICK: 383ExitDisableGPT11ICK:
462#if defined(PVR_OMAP4_TIMING_PRCM) 384#if defined(PVR_OMAP4_TIMING_PRCM)
463 clk_disable(psSysSpecData->psGPT11_ICK); 385 clk_disable(psSysSpecData->psGPT11_ICK);
464ExitDisableGPT11FCK: 386ExitDisableGPT11FCK:
465 clk_disable(psSysSpecData->psGPT11_FCK); 387 clk_disable(psSysSpecData->psGPT11_FCK);
466ExitUnRegisterConstraintNotifications:
467#endif
468#endif
469#if defined(OMAP4_PRCM_ENABLE)
470ExitError: 388ExitError:
471#endif 389#endif
472 eError = PVRSRV_ERROR_DISABLE_CLOCK_FAILURE; 390 eError = PVRSRV_ERROR_CLOCK_REQUEST_FAILED;
473Exit: 391Exit:
474 return eError; 392 return eError;
475} 393}
476 394
477IMG_VOID DisableSystemClocks(SYS_DATA *psSysData) 395static void ReleaseGPTimer(SYS_SPECIFIC_DATA *psSysSpecData)
478{ 396{
479#if (defined(DEBUG) || defined(TIMING)) && !defined(PVR_NO_OMAP_TIMER)
480#if defined(PVR_OMAP4_TIMING_PRCM)
481 SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
482#endif
483 IMG_CPU_PHYADDR TimerRegPhysBase;
484 IMG_HANDLE hTimerDisable; 397 IMG_HANDLE hTimerDisable;
485 IMG_UINT32 *pui32TimerDisable; 398 IMG_UINT32 *pui32TimerDisable;
486#endif
487 399
488 PVR_TRACE(("DisableSystemClocks: Disabling System Clocks")); 400 if (psSysSpecData->sTimerRegPhysBase.uiAddr == 0)
489 401 {
490 402 return;
491 DisableSGXClocks(psSysData); 403 }
492 404
493#if (defined(DEBUG) || defined(TIMING)) && !defined(PVR_NO_OMAP_TIMER)
494 405
495 TimerRegPhysBase.uiAddr = SYS_OMAP4430_GP11TIMER_ENABLE_SYS_PHYS_BASE; 406 pui32TimerDisable = OSMapPhysToLin(psSysSpecData->sTimerRegPhysBase,
496 pui32TimerDisable = OSMapPhysToLin(TimerRegPhysBase,
497 4, 407 4,
498 PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED, 408 PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
499 &hTimerDisable); 409 &hTimerDisable);
@@ -512,17 +422,61 @@ IMG_VOID DisableSystemClocks(SYS_DATA *psSysData)
512 hTimerDisable); 422 hTimerDisable);
513 } 423 }
514 424
425 psSysSpecData->sTimerRegPhysBase.uiAddr = 0;
426
515#if defined(PVR_OMAP4_TIMING_PRCM) 427#if defined(PVR_OMAP4_TIMING_PRCM)
516 clk_disable(psSysSpecData->psGPT11_ICK); 428 clk_disable(psSysSpecData->psGPT11_ICK);
517 429
518 clk_disable(psSysSpecData->psGPT11_FCK); 430 clk_disable(psSysSpecData->psGPT11_FCK);
519#endif 431#endif
432}
433#endif
434#else
435static PVRSRV_ERROR AcquireGPTimer(SYS_SPECIFIC_DATA *psSysSpecData)
436{
437 PVR_UNREFERENCED_PARAMETER(psSysSpecData);
438
439 return PVRSRV_OK;
440}
441static void ReleaseGPTimer(SYS_SPECIFIC_DATA *psSysSpecData)
442{
443 PVR_UNREFERENCED_PARAMETER(psSysSpecData);
444}
520#endif 445#endif
446
447PVRSRV_ERROR EnableSystemClocks(SYS_DATA *psSysData)
448{
449 SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
450
451 PVR_TRACE(("EnableSystemClocks: Enabling System Clocks"));
452
453 if (!psSysSpecData->bSysClocksOneTimeInit)
454 {
455 mutex_init(&psSysSpecData->sPowerLock);
456
457 atomic_set(&psSysSpecData->sSGXClocksEnabled, 0);
458
459 psSysSpecData->bSysClocksOneTimeInit = IMG_TRUE;
460 }
461
462 return AcquireGPTimer(psSysSpecData);
463}
464
465IMG_VOID DisableSystemClocks(SYS_DATA *psSysData)
466{
467 SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
468
469 PVR_TRACE(("DisableSystemClocks: Disabling System Clocks"));
470
471
472 DisableSGXClocks(psSysData);
473
474 ReleaseGPTimer(psSysSpecData);
521} 475}
522 476
523PVRSRV_ERROR SysPMRuntimeRegister(void) 477PVRSRV_ERROR SysPMRuntimeRegister(void)
524{ 478{
525#if defined(LDM_PLATFORM) && !defined(SUPPORT_DRI_DRM) 479#if defined(LDM_PLATFORM) && !defined(PVR_DRI_DRM_NOT_PCI)
526 pm_runtime_enable(&gpsPVRLDMDev->dev); 480 pm_runtime_enable(&gpsPVRLDMDev->dev);
527#endif 481#endif
528 return PVRSRV_OK; 482 return PVRSRV_OK;
@@ -530,7 +484,7 @@ PVRSRV_ERROR SysPMRuntimeRegister(void)
530 484
531PVRSRV_ERROR SysPMRuntimeUnregister(void) 485PVRSRV_ERROR SysPMRuntimeUnregister(void)
532{ 486{
533#if defined(LDM_PLATFORM) && !defined(SUPPORT_DRI_DRM) 487#if defined(LDM_PLATFORM) && !defined(PVR_DRI_DRM_NOT_PCI)
534 pm_runtime_disable(&gpsPVRLDMDev->dev); 488 pm_runtime_disable(&gpsPVRLDMDev->dev);
535#endif 489#endif
536 return PVRSRV_OK; 490 return PVRSRV_OK;
diff --git a/drivers/gpu/pvr/osfunc.c b/drivers/gpu/pvr/osfunc.c
index 9a264d23a87..2bcf0ed40ce 100644
--- a/drivers/gpu/pvr/osfunc.c
+++ b/drivers/gpu/pvr/osfunc.c
@@ -115,6 +115,15 @@ PVRSRV_ERROR OSAllocMem_Impl(IMG_UINT32 ui32Flags, IMG_UINT32 ui32Size, IMG_PVOI
115 return PVRSRV_OK; 115 return PVRSRV_OK;
116} 116}
117 117
118#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,24))
119
120static inline int is_vmalloc_addr(const void *pvCpuVAddr)
121{
122 unsigned long lAddr = (unsigned long)pvCpuVAddr;
123 return lAddr >= VMALLOC_START && lAddr < VMALLOC_END;
124}
125
126#endif
118 127
119#if !defined(DEBUG_LINUX_MEMORY_ALLOCATIONS) 128#if !defined(DEBUG_LINUX_MEMORY_ALLOCATIONS)
120PVRSRV_ERROR OSFreeMem_Impl(IMG_UINT32 ui32Flags, IMG_UINT32 ui32Size, IMG_PVOID pvCpuVAddr, IMG_HANDLE hBlockAlloc) 129PVRSRV_ERROR OSFreeMem_Impl(IMG_UINT32 ui32Flags, IMG_UINT32 ui32Size, IMG_PVOID pvCpuVAddr, IMG_HANDLE hBlockAlloc)
@@ -2950,6 +2959,29 @@ IMG_VOID OSFlushCPUCacheKM(IMG_VOID)
2950#endif 2959#endif
2951} 2960}
2952 2961
2962static inline size_t pvr_dmac_range_len(const void *pvStart, const void *pvEnd)
2963{
2964 return (size_t)((char *)pvEnd - (char *)pvStart);
2965}
2966
2967static void pvr_dmac_inv_range(const void *pvStart, const void *pvEnd)
2968{
2969#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,34))
2970 dmac_inv_range(pvStart, pvEnd);
2971#else
2972 dmac_map_area(pvStart, pvr_dmac_range_len(pvStart, pvEnd), DMA_FROM_DEVICE);
2973#endif
2974}
2975
2976static void pvr_dmac_clean_range(const void *pvStart, const void *pvEnd)
2977{
2978#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,34))
2979 dmac_clean_range(pvStart, pvEnd);
2980#else
2981 dmac_map_area(pvStart, pvr_dmac_range_len(pvStart, pvEnd), DMA_TO_DEVICE);
2982#endif
2983}
2984
2953IMG_BOOL OSFlushCPUCacheRangeKM(IMG_HANDLE hOSMemHandle, 2985IMG_BOOL OSFlushCPUCacheRangeKM(IMG_HANDLE hOSMemHandle,
2954 IMG_VOID *pvRangeAddrStart, 2986 IMG_VOID *pvRangeAddrStart,
2955 IMG_UINT32 ui32Length) 2987 IMG_UINT32 ui32Length)
@@ -2963,7 +2995,7 @@ IMG_BOOL OSCleanCPUCacheRangeKM(IMG_HANDLE hOSMemHandle,
2963 IMG_UINT32 ui32Length) 2995 IMG_UINT32 ui32Length)
2964{ 2996{
2965 return CheckExecuteCacheOp(hOSMemHandle, pvRangeAddrStart, ui32Length, 2997 return CheckExecuteCacheOp(hOSMemHandle, pvRangeAddrStart, ui32Length,
2966 dmac_clean_range, outer_clean_range); 2998 pvr_dmac_clean_range, outer_clean_range);
2967} 2999}
2968 3000
2969IMG_BOOL OSInvalidateCPUCacheRangeKM(IMG_HANDLE hOSMemHandle, 3001IMG_BOOL OSInvalidateCPUCacheRangeKM(IMG_HANDLE hOSMemHandle,
@@ -2971,7 +3003,7 @@ IMG_BOOL OSInvalidateCPUCacheRangeKM(IMG_HANDLE hOSMemHandle,
2971 IMG_UINT32 ui32Length) 3003 IMG_UINT32 ui32Length)
2972{ 3004{
2973 return CheckExecuteCacheOp(hOSMemHandle, pvRangeAddrStart, ui32Length, 3005 return CheckExecuteCacheOp(hOSMemHandle, pvRangeAddrStart, ui32Length,
2974 dmac_inv_range, outer_inv_range); 3006 pvr_dmac_inv_range, outer_inv_range);
2975} 3007}
2976 3008
2977#else 3009#else
@@ -2993,7 +3025,8 @@ IMG_BOOL OSFlushCPUCacheRangeKM(IMG_HANDLE hOSMemHandle,
2993 IMG_VOID *pvRangeAddrStart, 3025 IMG_VOID *pvRangeAddrStart,
2994 IMG_UINT32 ui32Length) 3026 IMG_UINT32 ui32Length)
2995{ 3027{
2996 dma_cache_wback_inv((IMG_UINTPTR_T)pvRangeAddrStart, ui32Length); 3028 if (ui32Length)
3029 dma_cache_wback_inv((IMG_UINTPTR_T)pvRangeAddrStart, ui32Length);
2997 return IMG_TRUE; 3030 return IMG_TRUE;
2998} 3031}
2999 3032
@@ -3001,7 +3034,8 @@ IMG_BOOL OSCleanCPUCacheRangeKM(IMG_HANDLE hOSMemHandle,
3001 IMG_VOID *pvRangeAddrStart, 3034 IMG_VOID *pvRangeAddrStart,
3002 IMG_UINT32 ui32Length) 3035 IMG_UINT32 ui32Length)
3003{ 3036{
3004 dma_cache_wback((IMG_UINTPTR_T)pvRangeAddrStart, ui32Length); 3037 if (ui32Length)
3038 dma_cache_wback((IMG_UINTPTR_T)pvRangeAddrStart, ui32Length);
3005 return IMG_TRUE; 3039 return IMG_TRUE;
3006} 3040}
3007 3041
@@ -3009,7 +3043,8 @@ IMG_BOOL OSInvalidateCPUCacheRangeKM(IMG_HANDLE hOSMemHandle,
3009 IMG_VOID *pvRangeAddrStart, 3043 IMG_VOID *pvRangeAddrStart,
3010 IMG_UINT32 ui32Length) 3044 IMG_UINT32 ui32Length)
3011{ 3045{
3012 dma_cache_inv((IMG_UINTPTR_T)pvRangeAddrStart, ui32Length); 3046 if (ui32Length)
3047 dma_cache_inv((IMG_UINTPTR_T)pvRangeAddrStart, ui32Length);
3013 return IMG_TRUE; 3048 return IMG_TRUE;
3014} 3049}
3015 3050
diff --git a/drivers/gpu/pvr/pdump/dbgdriv.c b/drivers/gpu/pvr/pdump/dbgdriv.c
index a1ca244f5f7..f8f635fd1e6 100644
--- a/drivers/gpu/pvr/pdump/dbgdriv.c
+++ b/drivers/gpu/pvr/pdump/dbgdriv.c
@@ -707,7 +707,7 @@ void MonoOut(IMG_CHAR * pszString,IMG_BOOL bNewLine)
707 PVR_UNREFERENCED_PARAMETER(bNewLine); 707 PVR_UNREFERENCED_PARAMETER(bNewLine);
708 708
709#else 709#else
710 IMG_UINT32 i; 710 IMG_UINT32 i;
711 IMG_CHAR * pScreen; 711 IMG_CHAR * pScreen;
712 712
713 pScreen = (IMG_CHAR *) DBGDRIV_MONOBASE; 713 pScreen = (IMG_CHAR *) DBGDRIV_MONOBASE;
@@ -842,10 +842,10 @@ static IMG_UINT32 WriteExpandingBuffer(PDBG_STREAM psStream,IMG_UINT8 * pui8InBu
842} 842}
843 843
844IMG_VOID * IMG_CALLCONV DBGDrivCreateStream(IMG_CHAR * pszName, 844IMG_VOID * IMG_CALLCONV DBGDrivCreateStream(IMG_CHAR * pszName,
845 IMG_UINT32 ui32CapMode, 845 IMG_UINT32 ui32CapMode,
846 IMG_UINT32 ui32OutMode, 846 IMG_UINT32 ui32OutMode,
847 IMG_UINT32 ui32Flags, 847 IMG_UINT32 ui32Flags,
848 IMG_UINT32 ui32Size) 848 IMG_UINT32 ui32Size)
849{ 849{
850 PDBG_STREAM psStream; 850 PDBG_STREAM psStream;
851 PDBG_STREAM psInitStream; 851 PDBG_STREAM psInitStream;
diff --git a/drivers/gpu/pvr/pdump/dbgdriv.h b/drivers/gpu/pvr/pdump/dbgdriv.h
index a285d0d919b..dc75f88f160 100644
--- a/drivers/gpu/pvr/pdump/dbgdriv.h
+++ b/drivers/gpu/pvr/pdump/dbgdriv.h
@@ -29,9 +29,9 @@
29 29
30#define BUFFER_SIZE 64*PAGESIZE 30#define BUFFER_SIZE 64*PAGESIZE
31 31
32#define DBGDRIV_VERSION 0x100 32#define DBGDRIV_VERSION 0x100
33#define MAX_PROCESSES 2 33#define MAX_PROCESSES 2
34#define BLOCK_USED 0x01 34#define BLOCK_USED 0x01
35#define BLOCK_LOCKED 0x02 35#define BLOCK_LOCKED 0x02
36#define DBGDRIV_MONOBASE 0x000B0000 36#define DBGDRIV_MONOBASE 0x000B0000
37 37
@@ -39,10 +39,10 @@
39extern IMG_VOID * g_pvAPIMutex; 39extern IMG_VOID * g_pvAPIMutex;
40 40
41IMG_VOID * IMG_CALLCONV DBGDrivCreateStream(IMG_CHAR * pszName, 41IMG_VOID * IMG_CALLCONV DBGDrivCreateStream(IMG_CHAR * pszName,
42 IMG_UINT32 ui32CapMode, 42 IMG_UINT32 ui32CapMode,
43 IMG_UINT32 ui32OutMode, 43 IMG_UINT32 ui32OutMode,
44 IMG_UINT32 ui32Flags, 44 IMG_UINT32 ui32Flags,
45 IMG_UINT32 ui32Pages); 45 IMG_UINT32 ui32Pages);
46IMG_VOID IMG_CALLCONV DBGDrivDestroyStream(PDBG_STREAM psStream); 46IMG_VOID IMG_CALLCONV DBGDrivDestroyStream(PDBG_STREAM psStream);
47IMG_VOID * IMG_CALLCONV DBGDrivFindStream(IMG_CHAR * pszName, IMG_BOOL bResetStream); 47IMG_VOID * IMG_CALLCONV DBGDrivFindStream(IMG_CHAR * pszName, IMG_BOOL bResetStream);
48IMG_UINT32 IMG_CALLCONV DBGDrivWriteString(PDBG_STREAM psStream,IMG_CHAR * pszString,IMG_UINT32 ui32Level); 48IMG_UINT32 IMG_CALLCONV DBGDrivWriteString(PDBG_STREAM psStream,IMG_CHAR * pszString,IMG_UINT32 ui32Level);
diff --git a/drivers/gpu/pvr/pdump/dbgdriv_ioctl.h b/drivers/gpu/pvr/pdump/dbgdriv_ioctl.h
index 8cef6ac78a8..68492495115 100644
--- a/drivers/gpu/pvr/pdump/dbgdriv_ioctl.h
+++ b/drivers/gpu/pvr/pdump/dbgdriv_ioctl.h
@@ -1,6 +1,6 @@
1/********************************************************************** 1/**********************************************************************
2 * 2 *
3 * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved. 3 * Copyright (C) Imagination Technologies Ltd. All rights reserved.
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License, 6 * under the terms and conditions of the GNU General Public License,
diff --git a/drivers/gpu/pvr/pdump/handle.c b/drivers/gpu/pvr/pdump/handle.c
index dceeab886c1..8ba44df7055 100644
--- a/drivers/gpu/pvr/pdump/handle.c
+++ b/drivers/gpu/pvr/pdump/handle.c
@@ -1,6 +1,6 @@
1/********************************************************************** 1/**********************************************************************
2 * 2 *
3 * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved. 3 * Copyright (C) Imagination Technologies Ltd. All rights reserved.
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License, 6 * under the terms and conditions of the GNU General Public License,
@@ -68,7 +68,7 @@ PDBG_STREAM SID2PStream(IMG_SID hStream)
68 } 68 }
69 else 69 else
70 { 70 {
71 return (PDBG_STREAM)IMG_NULL; 71 return (PDBG_STREAM)IMG_NULL;
72 } 72 }
73} 73}
74 74
diff --git a/drivers/gpu/pvr/pdump/hostfunc.c b/drivers/gpu/pvr/pdump/hostfunc.c
index 64b20cc37b8..5eb8e1cc91a 100644
--- a/drivers/gpu/pvr/pdump/hostfunc.c
+++ b/drivers/gpu/pvr/pdump/hostfunc.c
@@ -1,6 +1,6 @@
1/********************************************************************** 1/**********************************************************************
2 * 2 *
3 * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved. 3 * Copyright (C) Imagination Technologies Ltd. All rights reserved.
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License, 6 * under the terms and conditions of the GNU General Public License,
@@ -29,13 +29,17 @@
29#include <linux/module.h> 29#include <linux/module.h>
30#include <linux/fs.h> 30#include <linux/fs.h>
31#include <linux/kernel.h> 31#include <linux/kernel.h>
32#include <linux/slab.h>
32#include <linux/mm.h> 33#include <linux/mm.h>
33#include <linux/string.h> 34#include <linux/string.h>
34#include <asm/page.h> 35#include <asm/page.h>
35#include <linux/vmalloc.h> 36#include <linux/vmalloc.h>
37#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,15))
36#include <linux/mutex.h> 38#include <linux/mutex.h>
39#else
40#include <asm/semaphore.h>
41#endif
37#include <linux/hardirq.h> 42#include <linux/hardirq.h>
38#include <linux/slab.h>
39 43
40#if defined(SUPPORT_DBGDRV_EVENT_OBJECTS) 44#if defined(SUPPORT_DBGDRV_EVENT_OBJECTS)
41#include <linux/sched.h> 45#include <linux/sched.h>
@@ -51,13 +55,13 @@
51#include "hostfunc.h" 55#include "hostfunc.h"
52#include "dbgdriv.h" 56#include "dbgdriv.h"
53 57
54#if defined(DEBUG) && !defined(SUPPORT_DRI_DRM) 58#if defined(MODULE) && defined(DEBUG) && !defined(SUPPORT_DRI_DRM)
55IMG_UINT32 gPVRDumpDebugLevel = (DBGPRIV_FATAL | DBGPRIV_ERROR | DBGPRIV_WARNING); 59IMG_UINT32 gPVRDebugLevel = (DBGPRIV_FATAL | DBGPRIV_ERROR | DBGPRIV_WARNING);
56 60
57#define PVR_STRING_TERMINATOR '\0' 61#define PVR_STRING_TERMINATOR '\0'
58#define PVR_IS_FILE_SEPARATOR(character) ( ((character) == '\\') || ((character) == '/') ) 62#define PVR_IS_FILE_SEPARATOR(character) ( ((character) == '\\') || ((character) == '/') )
59 63
60void PVRSRVDumpDebugPrintf ( 64void PVRSRVDebugPrintf (
61 IMG_UINT32 ui32DebugLevel, 65 IMG_UINT32 ui32DebugLevel,
62 const IMG_CHAR* pszFileName, 66 const IMG_CHAR* pszFileName,
63 IMG_UINT32 ui32Line, 67 IMG_UINT32 ui32Line,
@@ -79,7 +83,7 @@ void PVRSRVDumpDebugPrintf (
79 83
80 bTrace = (IMG_BOOL)(ui32DebugLevel & DBGPRIV_CALLTRACE) ? IMG_TRUE : IMG_FALSE; 84 bTrace = (IMG_BOOL)(ui32DebugLevel & DBGPRIV_CALLTRACE) ? IMG_TRUE : IMG_FALSE;
81 85
82 if (gPVRDumpDebugLevel & ui32DebugLevel) 86 if (gPVRDebugLevel & ui32DebugLevel)
83 { 87 {
84 va_list vaArgs; 88 va_list vaArgs;
85 static char szBuffer[256]; 89 static char szBuffer[256];
@@ -131,7 +135,7 @@ void PVRSRVDumpDebugPrintf (
131 vsprintf (&szBuffer[strlen(szBuffer)], pszFormat, vaArgs); 135 vsprintf (&szBuffer[strlen(szBuffer)], pszFormat, vaArgs);
132 136
133 137
134 if (bTrace == IMG_FALSE) 138 if (bTrace == IMG_FALSE)
135 { 139 {
136 sprintf (&szBuffer[strlen(szBuffer)], " [%d, %s]", (int)ui32Line, pszFileName); 140 sprintf (&szBuffer[strlen(szBuffer)], " [%d, %s]", (int)ui32Line, pszFileName);
137 } 141 }
diff --git a/drivers/gpu/pvr/pdump/hostfunc.h b/drivers/gpu/pvr/pdump/hostfunc.h
index 42733d7c131..acfc439db0a 100644
--- a/drivers/gpu/pvr/pdump/hostfunc.h
+++ b/drivers/gpu/pvr/pdump/hostfunc.h
@@ -1,6 +1,6 @@
1/********************************************************************** 1/**********************************************************************
2 * 2 *
3 * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved. 3 * Copyright (C) Imagination Technologies Ltd. All rights reserved.
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License, 6 * under the terms and conditions of the GNU General Public License,
diff --git a/drivers/gpu/pvr/pdump/hotkey.c b/drivers/gpu/pvr/pdump/hotkey.c
index 48853c79537..2d82b6cf6d9 100644
--- a/drivers/gpu/pvr/pdump/hotkey.c
+++ b/drivers/gpu/pvr/pdump/hotkey.c
@@ -1,6 +1,6 @@
1/********************************************************************** 1/**********************************************************************
2 * 2 *
3 * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved. 3 * Copyright (C) Imagination Technologies Ltd. All rights reserved.
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License, 6 * under the terms and conditions of the GNU General Public License,
diff --git a/drivers/gpu/pvr/pdump/hotkey.h b/drivers/gpu/pvr/pdump/hotkey.h
index d9c9458da74..942d2daa3a9 100644
--- a/drivers/gpu/pvr/pdump/hotkey.h
+++ b/drivers/gpu/pvr/pdump/hotkey.h
@@ -1,6 +1,6 @@
1/********************************************************************** 1/**********************************************************************
2 * 2 *
3 * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved. 3 * Copyright (C) Imagination Technologies Ltd. All rights reserved.
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License, 6 * under the terms and conditions of the GNU General Public License,
diff --git a/drivers/gpu/pvr/pdump/ioctl.c b/drivers/gpu/pvr/pdump/ioctl.c
index e646c4f9324..1d291468526 100644
--- a/drivers/gpu/pvr/pdump/ioctl.c
+++ b/drivers/gpu/pvr/pdump/ioctl.c
@@ -1,6 +1,6 @@
1/********************************************************************** 1/**********************************************************************
2 * 2 *
3 * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved. 3 * Copyright (C) Imagination Technologies Ltd. All rights reserved.
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License, 6 * under the terms and conditions of the GNU General Public License,
@@ -194,7 +194,7 @@ static IMG_UINT32 DBGDIOCDrivWrite2(IMG_VOID * pvInBuffer, IMG_VOID * pvOutBuffe
194{ 194{
195 IMG_UINT32 * pui32BytesCopied; 195 IMG_UINT32 * pui32BytesCopied;
196 PDBG_IN_WRITE psInParams; 196 PDBG_IN_WRITE psInParams;
197 PDBG_STREAM psStream; 197 PDBG_STREAM psStream;
198 198
199 psInParams = (PDBG_IN_WRITE) pvInBuffer; 199 psInParams = (PDBG_IN_WRITE) pvInBuffer;
200 pui32BytesCopied = (IMG_UINT32 *) pvOutBuffer; 200 pui32BytesCopied = (IMG_UINT32 *) pvOutBuffer;
diff --git a/drivers/gpu/pvr/pdump/linuxsrv.h b/drivers/gpu/pvr/pdump/linuxsrv.h
index 671622fa8b4..4888cd04214 100644
--- a/drivers/gpu/pvr/pdump/linuxsrv.h
+++ b/drivers/gpu/pvr/pdump/linuxsrv.h
@@ -1,6 +1,6 @@
1/********************************************************************** 1/**********************************************************************
2 * 2 *
3 * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved. 3 * Copyright (C) Imagination Technologies Ltd. All rights reserved.
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License, 6 * under the terms and conditions of the GNU General Public License,
@@ -31,7 +31,7 @@ typedef struct tagIOCTL_PACKAGE
31{ 31{
32 IMG_UINT32 ui32Cmd; 32 IMG_UINT32 ui32Cmd;
33 IMG_UINT32 ui32Size; 33 IMG_UINT32 ui32Size;
34 IMG_VOID *pInBuffer; 34 IMG_VOID *pInBuffer;
35 IMG_UINT32 ui32InBufferSize; 35 IMG_UINT32 ui32InBufferSize;
36 IMG_VOID *pOutBuffer; 36 IMG_VOID *pOutBuffer;
37 IMG_UINT32 ui32OutBufferSize; 37 IMG_UINT32 ui32OutBufferSize;
diff --git a/drivers/gpu/pvr/pdump/main.c b/drivers/gpu/pvr/pdump/main.c
index 69c0d9b1a97..45d041b087f 100644
--- a/drivers/gpu/pvr/pdump/main.c
+++ b/drivers/gpu/pvr/pdump/main.c
@@ -1,6 +1,6 @@
1/********************************************************************** 1/**********************************************************************
2 * 2 *
3 * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved. 3 * Copyright (C) Imagination Technologies Ltd. All rights reserved.
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License, 6 * under the terms and conditions of the GNU General Public License,
@@ -116,7 +116,7 @@ IMG_VOID DBGDrvGetServiceTable(IMG_VOID **fn_table)
116#if defined(SUPPORT_DRI_DRM) 116#if defined(SUPPORT_DRI_DRM)
117void dbgdrv_cleanup(void) 117void dbgdrv_cleanup(void)
118#else 118#else
119void __exit dbgdrv_cleanup_module(void) 119static void __exit dbgdrv_cleanup(void)
120#endif 120#endif
121{ 121{
122#if !defined(SUPPORT_DRI_DRM) 122#if !defined(SUPPORT_DRI_DRM)
@@ -136,7 +136,7 @@ void __exit dbgdrv_cleanup_module(void)
136#if defined(SUPPORT_DRI_DRM) 136#if defined(SUPPORT_DRI_DRM)
137IMG_INT dbgdrv_init(void) 137IMG_INT dbgdrv_init(void)
138#else 138#else
139int __init dbgdrv_init_module(void) 139static int __init dbgdrv_init(void)
140#endif 140#endif
141{ 141{
142#if (defined(LDM_PLATFORM) || defined(LDM_PCI)) && !defined(SUPPORT_DRI_DRM) 142#if (defined(LDM_PLATFORM) || defined(LDM_PCI)) && !defined(SUPPORT_DRI_DRM)
@@ -240,6 +240,7 @@ long dbgdrv_ioctl(struct file *file, unsigned int ioctlCmd, unsigned long arg)
240 goto init_failed; 240 goto init_failed;
241 } 241 }
242 242
243
243 cmd = MAKEIOCTLINDEX(pIP->ui32Cmd) - DEBUG_SERVICE_IOCTL_BASE - 1; 244 cmd = MAKEIOCTLINDEX(pIP->ui32Cmd) - DEBUG_SERVICE_IOCTL_BASE - 1;
244 245
245 if(pIP->ui32Cmd == DEBUG_SERVICE_READ) 246 if(pIP->ui32Cmd == DEBUG_SERVICE_READ)
@@ -310,5 +311,7 @@ IMG_VOID DefineHotKey (IMG_UINT32 ui32ScanCode, IMG_UINT32 ui32ShiftState, PHOTK
310 311
311EXPORT_SYMBOL(DBGDrvGetServiceTable); 312EXPORT_SYMBOL(DBGDrvGetServiceTable);
312 313
313module_init(dbgdrv_init_module); 314#if !defined(SUPPORT_DRI_DRM)
314module_exit(dbgdrv_cleanup_module); 315subsys_initcall(dbgdrv_init);
316module_exit(dbgdrv_cleanup);
317#endif
diff --git a/drivers/gpu/pvr/perproc.c b/drivers/gpu/pvr/perproc.c
index 1753388b1bb..eb73166bb32 100644
--- a/drivers/gpu/pvr/perproc.c
+++ b/drivers/gpu/pvr/perproc.c
@@ -127,7 +127,10 @@ PVRSRV_ERROR PVRSRVPerProcessDataConnect(IMG_UINT32 ui32PID, IMG_UINT32 ui32Flag
127 IMG_HANDLE hBlockAlloc; 127 IMG_HANDLE hBlockAlloc;
128 PVRSRV_ERROR eError = PVRSRV_OK; 128 PVRSRV_ERROR eError = PVRSRV_OK;
129 129
130 PVR_ASSERT(psHashTab != IMG_NULL); 130 if (psHashTab == IMG_NULL)
131 {
132 return PVRSRV_ERROR_INIT_FAILURE;
133 }
131 134
132 135
133 psPerProc = (PVRSRV_PER_PROCESS_DATA *)HASH_Retrieve(psHashTab, (IMG_UINTPTR_T)ui32PID); 136 psPerProc = (PVRSRV_PER_PROCESS_DATA *)HASH_Retrieve(psHashTab, (IMG_UINTPTR_T)ui32PID);
diff --git a/drivers/gpu/pvr/pvr_bridge_km.h b/drivers/gpu/pvr/pvr_bridge_km.h
index c1fd04cb312..1175b76c194 100644
--- a/drivers/gpu/pvr/pvr_bridge_km.h
+++ b/drivers/gpu/pvr/pvr_bridge_km.h
@@ -109,7 +109,7 @@ PVRSRV_ERROR IMG_CALLCONV _PVRSRVAllocDeviceMemKM(IMG_HANDLE hDevCookie,
109#if defined(PVRSRV_LOG_MEMORY_ALLOCS) 109#if defined(PVRSRV_LOG_MEMORY_ALLOCS)
110 #define PVRSRVAllocDeviceMemKM(devCookie, perProc, devMemHeap, flags, size, alignment, memInfo, logStr) \ 110 #define PVRSRVAllocDeviceMemKM(devCookie, perProc, devMemHeap, flags, size, alignment, memInfo, logStr) \
111 (PVR_TRACE(("PVRSRVAllocDeviceMemKM(" #devCookie ", " #perProc ", " #devMemHeap ", " #flags ", " #size \ 111 (PVR_TRACE(("PVRSRVAllocDeviceMemKM(" #devCookie ", " #perProc ", " #devMemHeap ", " #flags ", " #size \
112 ", " #alignment "," #memInfo "): " logStr " (size = 0x%;x)", size)),\ 112 ", " #alignment "," #memInfo "): " logStr " (size = 0x%x)", size)),\
113 _PVRSRVAllocDeviceMemKM(devCookie, perProc, devMemHeap, flags, size, alignment, memInfo)) 113 _PVRSRVAllocDeviceMemKM(devCookie, perProc, devMemHeap, flags, size, alignment, memInfo))
114#else 114#else
115 #define PVRSRVAllocDeviceMemKM(devCookie, perProc, devMemHeap, flags, size, alignment, memInfo, logStr) \ 115 #define PVRSRVAllocDeviceMemKM(devCookie, perProc, devMemHeap, flags, size, alignment, memInfo, logStr) \
diff --git a/drivers/gpu/pvr/pvr_debug.c b/drivers/gpu/pvr/pvr_debug.c
index 091f6590e70..2e64fe6ed36 100644
--- a/drivers/gpu/pvr/pvr_debug.c
+++ b/drivers/gpu/pvr/pvr_debug.c
@@ -1,6 +1,6 @@
1/********************************************************************** 1/**********************************************************************
2 * 2 *
3 * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved. 3 * Copyright (C) Imagination Technologies Ltd. All rights reserved.
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License, 6 * under the terms and conditions of the GNU General Public License,
@@ -312,7 +312,8 @@ IMG_VOID PVRSRVDebugPrintf (
312 IMG_CHAR* pszTruncBackInter; 312 IMG_CHAR* pszTruncBackInter;
313 313
314 314
315 pszFileName = pszFullFileName + strlen(DEBUG_LOG_PATH_TRUNCATE)+1; 315 if (strlen(pszFullFileName) > strlen(DEBUG_LOG_PATH_TRUNCATE)+1)
316 pszFileName = pszFullFileName + strlen(DEBUG_LOG_PATH_TRUNCATE)+1;
316 317
317 318
318 strncpy(szFileNameRewrite, pszFileName,PVR_MAX_FILEPATH_LEN); 319 strncpy(szFileNameRewrite, pszFileName,PVR_MAX_FILEPATH_LEN);
diff --git a/drivers/gpu/pvr/pvrversion.h b/drivers/gpu/pvr/pvrversion.h
index 8c4505e2832..0e6e0e48929 100644
--- a/drivers/gpu/pvr/pvrversion.h
+++ b/drivers/gpu/pvr/pvrversion.h
@@ -30,8 +30,8 @@
30#define PVRVERSION_MAJ 1 30#define PVRVERSION_MAJ 1
31#define PVRVERSION_MIN 7 31#define PVRVERSION_MIN 7
32#define PVRVERSION_BRANCH 17 32#define PVRVERSION_BRANCH 17
33#define PVRVERSION_BUILD 3957 33#define PVRVERSION_BUILD 4403
34#define PVRVERSION_STRING "1.7.17.3957" 34#define PVRVERSION_STRING "1.7.17.4403"
35#define PVRVERSION_FILE "eurasiacon.pj" 35#define PVRVERSION_FILE "eurasiacon.pj"
36 36
37#endif 37#endif
diff --git a/drivers/gpu/pvr/resman.c b/drivers/gpu/pvr/resman.c
index 5230952be84..b3a4534c809 100644
--- a/drivers/gpu/pvr/resman.c
+++ b/drivers/gpu/pvr/resman.c
@@ -122,7 +122,7 @@ static IMPLEMENT_LIST_INSERT(RESMAN_CONTEXT)
122 122
123#define PRINT_RESLIST(x, y, z) 123#define PRINT_RESLIST(x, y, z)
124 124
125static PVRSRV_ERROR FreeResourceByPtr(RESMAN_ITEM *psItem, IMG_BOOL bExecuteCallback); 125static PVRSRV_ERROR FreeResourceByPtr(RESMAN_ITEM *psItem, IMG_BOOL bExecuteCallback, IMG_BOOL bForceCleanup);
126 126
127static PVRSRV_ERROR FreeResourceByCriteria(PRESMAN_CONTEXT psContext, 127static PVRSRV_ERROR FreeResourceByCriteria(PRESMAN_CONTEXT psContext,
128 IMG_UINT32 ui32SearchCriteria, 128 IMG_UINT32 ui32SearchCriteria,
@@ -379,7 +379,7 @@ PRESMAN_ITEM ResManRegisterRes(PRESMAN_CONTEXT psResManContext,
379 return(psNewResItem); 379 return(psNewResItem);
380} 380}
381 381
382PVRSRV_ERROR ResManFreeResByPtr(RESMAN_ITEM *psResItem) 382PVRSRV_ERROR ResManFreeResByPtr(RESMAN_ITEM *psResItem, IMG_BOOL bForceCleanup)
383{ 383{
384 PVRSRV_ERROR eError; 384 PVRSRV_ERROR eError;
385 385
@@ -401,7 +401,7 @@ PVRSRV_ERROR ResManFreeResByPtr(RESMAN_ITEM *psResItem)
401 VALIDATERESLIST(); 401 VALIDATERESLIST();
402 402
403 403
404 eError = FreeResourceByPtr(psResItem, IMG_TRUE); 404 eError = FreeResourceByPtr(psResItem, IMG_TRUE, bForceCleanup);
405 405
406 406
407 VALIDATERESLIST(); 407 VALIDATERESLIST();
@@ -478,7 +478,7 @@ PVRSRV_ERROR ResManDissociateRes(RESMAN_ITEM *psResItem,
478 } 478 }
479 else 479 else
480 { 480 {
481 eError = FreeResourceByPtr(psResItem, IMG_FALSE); 481 eError = FreeResourceByPtr(psResItem, IMG_FALSE, CLEANUP_WITH_POLL);
482 if(eError != PVRSRV_OK) 482 if(eError != PVRSRV_OK)
483 { 483 {
484 PVR_DPF((PVR_DBG_ERROR, "ResManDissociateRes: failed to free resource by pointer")); 484 PVR_DPF((PVR_DBG_ERROR, "ResManDissociateRes: failed to free resource by pointer"));
@@ -554,9 +554,10 @@ IMG_INTERNAL PVRSRV_ERROR ResManFindResourceByPtr(PRESMAN_CONTEXT psResManContex
554} 554}
555 555
556static PVRSRV_ERROR FreeResourceByPtr(RESMAN_ITEM *psItem, 556static PVRSRV_ERROR FreeResourceByPtr(RESMAN_ITEM *psItem,
557 IMG_BOOL bExecuteCallback) 557 IMG_BOOL bExecuteCallback,
558 IMG_BOOL bForceCleanup)
558{ 559{
559 PVRSRV_ERROR eError; 560 PVRSRV_ERROR eError = PVRSRV_OK;
560 561
561 PVR_ASSERT(psItem != IMG_NULL); 562 PVR_ASSERT(psItem != IMG_NULL);
562 563
@@ -591,7 +592,7 @@ static PVRSRV_ERROR FreeResourceByPtr(RESMAN_ITEM *psItem,
591 592
592 if (bExecuteCallback) 593 if (bExecuteCallback)
593 { 594 {
594 eError = psItem->pfnFreeResource(psItem->pvParam, psItem->ui32Param); 595 eError = psItem->pfnFreeResource(psItem->pvParam, psItem->ui32Param, bForceCleanup);
595 if (eError != PVRSRV_OK) 596 if (eError != PVRSRV_OK)
596 { 597 {
597 PVR_DPF((PVR_DBG_ERROR, "FreeResourceByPtr: ERROR calling FreeResource function")); 598 PVR_DPF((PVR_DBG_ERROR, "FreeResourceByPtr: ERROR calling FreeResource function"));
@@ -602,11 +603,7 @@ static PVRSRV_ERROR FreeResourceByPtr(RESMAN_ITEM *psItem,
602 ACQUIRE_SYNC_OBJ; 603 ACQUIRE_SYNC_OBJ;
603 604
604 605
605 eError = OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, sizeof(RESMAN_ITEM), psItem, IMG_NULL); 606 OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, sizeof(RESMAN_ITEM), psItem, IMG_NULL);
606 if (eError != PVRSRV_OK)
607 {
608 PVR_DPF((PVR_DBG_ERROR, "FreeResourceByPtr: ERROR freeing resource list item memory"));
609 }
610 607
611 return(eError); 608 return(eError);
612} 609}
@@ -667,7 +664,7 @@ static PVRSRV_ERROR FreeResourceByCriteria(PRESMAN_CONTEXT psResManContext,
667 ui32Param)) != IMG_NULL 664 ui32Param)) != IMG_NULL
668 && eError == PVRSRV_OK) 665 && eError == PVRSRV_OK)
669 { 666 {
670 eError = FreeResourceByPtr(psCurItem, bExecuteCallback); 667 eError = FreeResourceByPtr(psCurItem, bExecuteCallback, CLEANUP_WITH_POLL);
671 } 668 }
672 669
673 return eError; 670 return eError;
diff --git a/drivers/gpu/pvr/resman.h b/drivers/gpu/pvr/resman.h
index 11af49be72d..c20719fe446 100644
--- a/drivers/gpu/pvr/resman.h
+++ b/drivers/gpu/pvr/resman.h
@@ -76,7 +76,7 @@ enum {
76#define RESMAN_CRITERIA_PVOID_PARAM 0x00000002 76#define RESMAN_CRITERIA_PVOID_PARAM 0x00000002
77#define RESMAN_CRITERIA_UI32_PARAM 0x00000004 77#define RESMAN_CRITERIA_UI32_PARAM 0x00000004
78 78
79typedef PVRSRV_ERROR (*RESMAN_FREE_FN)(IMG_PVOID pvParam, IMG_UINT32 ui32Param); 79typedef PVRSRV_ERROR (*RESMAN_FREE_FN)(IMG_PVOID pvParam, IMG_UINT32 ui32Param, IMG_BOOL bForceCleanup);
80 80
81typedef struct _RESMAN_ITEM_ *PRESMAN_ITEM; 81typedef struct _RESMAN_ITEM_ *PRESMAN_ITEM;
82typedef struct _RESMAN_CONTEXT_ *PRESMAN_CONTEXT; 82typedef struct _RESMAN_CONTEXT_ *PRESMAN_CONTEXT;
@@ -90,7 +90,8 @@ PRESMAN_ITEM ResManRegisterRes(PRESMAN_CONTEXT hResManContext,
90 IMG_UINT32 ui32Param, 90 IMG_UINT32 ui32Param,
91 RESMAN_FREE_FN pfnFreeResource); 91 RESMAN_FREE_FN pfnFreeResource);
92 92
93PVRSRV_ERROR ResManFreeResByPtr(PRESMAN_ITEM psResItem); 93PVRSRV_ERROR ResManFreeResByPtr(PRESMAN_ITEM psResItem,
94 IMG_BOOL bForceCleanup);
94 95
95PVRSRV_ERROR ResManFreeResByCriteria(PRESMAN_CONTEXT hResManContext, 96PVRSRV_ERROR ResManFreeResByCriteria(PRESMAN_CONTEXT hResManContext,
96 IMG_UINT32 ui32SearchCriteria, 97 IMG_UINT32 ui32SearchCriteria,
diff --git a/drivers/gpu/pvr/services.h b/drivers/gpu/pvr/services.h
index 3539e26448a..c61313a5f11 100644
--- a/drivers/gpu/pvr/services.h
+++ b/drivers/gpu/pvr/services.h
@@ -1066,6 +1066,10 @@ IMG_IMPORT PVRSRV_ERROR IMG_CALLCONV PVRSRVDestroyMutex(PVRSRV_MUTEX_HANDLE hMut
1066IMG_IMPORT IMG_VOID IMG_CALLCONV PVRSRVLockMutex(PVRSRV_MUTEX_HANDLE hMutex); 1066IMG_IMPORT IMG_VOID IMG_CALLCONV PVRSRVLockMutex(PVRSRV_MUTEX_HANDLE hMutex);
1067IMG_IMPORT IMG_VOID IMG_CALLCONV PVRSRVUnlockMutex(PVRSRV_MUTEX_HANDLE hMutex); 1067IMG_IMPORT IMG_VOID IMG_CALLCONV PVRSRVUnlockMutex(PVRSRV_MUTEX_HANDLE hMutex);
1068 1068
1069IMG_IMPORT IMG_VOID IMG_CALLCONV PVRSRVLockProcessGlobalMutex(void);
1070IMG_IMPORT IMG_VOID IMG_CALLCONV PVRSRVUnlockProcessGlobalMutex(void);
1071
1072
1069struct _PVRSRV_SEMAPHORE_OPAQUE_STRUCT_; 1073struct _PVRSRV_SEMAPHORE_OPAQUE_STRUCT_;
1070typedef struct _PVRSRV_SEMAPHORE_OPAQUE_STRUCT_ *PVRSRV_SEMAPHORE_HANDLE; 1074typedef struct _PVRSRV_SEMAPHORE_OPAQUE_STRUCT_ *PVRSRV_SEMAPHORE_HANDLE;
1071 1075
diff --git a/drivers/gpu/pvr/servicesext.h b/drivers/gpu/pvr/servicesext.h
index 9a494b3dbcf..fdd63cb62fc 100644
--- a/drivers/gpu/pvr/servicesext.h
+++ b/drivers/gpu/pvr/servicesext.h
@@ -587,7 +587,13 @@ typedef enum _PVRSRV_PIXEL_FORMAT_ {
587 PVRSRV_PIXEL_FORMAT_C1_4KYUV420_2P_VU = 218, 587 PVRSRV_PIXEL_FORMAT_C1_4KYUV420_2P_VU = 218,
588 PVRSRV_PIXEL_FORMAT_P208 = 219, 588 PVRSRV_PIXEL_FORMAT_P208 = 219,
589 PVRSRV_PIXEL_FORMAT_A8P8 = 220, 589 PVRSRV_PIXEL_FORMAT_A8P8 = 220,
590 590
591 PVRSRV_PIXEL_FORMAT_A4 = 221,
592 PVRSRV_PIXEL_FORMAT_AYUV8888 = 222,
593 PVRSRV_PIXEL_FORMAT_RAW256 = 223,
594 PVRSRV_PIXEL_FORMAT_RAW512 = 224,
595 PVRSRV_PIXEL_FORMAT_RAW1024 = 225,
596
591 PVRSRV_PIXEL_FORMAT_FORCE_I32 = 0x7fffffff 597 PVRSRV_PIXEL_FORMAT_FORCE_I32 = 0x7fffffff
592 598
593} PVRSRV_PIXEL_FORMAT; 599} PVRSRV_PIXEL_FORMAT;
@@ -779,47 +785,6 @@ typedef struct ACCESS_INFO_TAG
779}ACCESS_INFO; 785}ACCESS_INFO;
780 786
781 787
782typedef struct PVRSRV_CURSOR_SHAPE_TAG
783{
784 IMG_UINT16 ui16Width;
785 IMG_UINT16 ui16Height;
786 IMG_INT16 i16XHot;
787 IMG_INT16 i16YHot;
788
789
790 IMG_VOID* pvMask;
791 IMG_INT16 i16MaskByteStride;
792
793
794 IMG_VOID* pvColour;
795 IMG_INT16 i16ColourByteStride;
796 PVRSRV_PIXEL_FORMAT eColourPixelFormat;
797} PVRSRV_CURSOR_SHAPE;
798
799#define PVRSRV_SET_CURSOR_VISIBILITY (1<<0)
800#define PVRSRV_SET_CURSOR_POSITION (1<<1)
801#define PVRSRV_SET_CURSOR_SHAPE (1<<2)
802#define PVRSRV_SET_CURSOR_ROTATION (1<<3)
803
804typedef struct PVRSRV_CURSOR_INFO_TAG
805{
806
807 IMG_UINT32 ui32Flags;
808
809
810 IMG_BOOL bVisible;
811
812
813 IMG_INT16 i16XPos;
814 IMG_INT16 i16YPos;
815
816
817 PVRSRV_CURSOR_SHAPE sCursorShape;
818
819
820 IMG_UINT32 ui32Rotation;
821
822} PVRSRV_CURSOR_INFO;
823 788
824#if defined(PDUMP_SUSPEND_IS_PER_THREAD) 789#if defined(PDUMP_SUSPEND_IS_PER_THREAD)
825typedef struct { 790typedef struct {
diff --git a/drivers/gpu/pvr/sgx/bridged_sgx_bridge.c b/drivers/gpu/pvr/sgx/bridged_sgx_bridge.c
index 03343e8ed14..9591c55a731 100644
--- a/drivers/gpu/pvr/sgx/bridged_sgx_bridge.c
+++ b/drivers/gpu/pvr/sgx/bridged_sgx_bridge.c
@@ -49,6 +49,7 @@
49#include "bridged_pvr_bridge.h" 49#include "bridged_pvr_bridge.h"
50#include "bridged_sgx_bridge.h" 50#include "bridged_sgx_bridge.h"
51#include "sgxutils.h" 51#include "sgxutils.h"
52#include "buffer_manager.h"
52#include "pdump_km.h" 53#include "pdump_km.h"
53 54
54static IMG_INT 55static IMG_INT
@@ -2185,7 +2186,8 @@ SGXUnregisterHWRenderContextBW(IMG_UINT32 ui32BridgeID,
2185 return 0; 2186 return 0;
2186 } 2187 }
2187 2188
2188 psRetOUT->eError = SGXUnregisterHWRenderContextKM(hHWRenderContextInt); 2189 psRetOUT->eError = SGXUnregisterHWRenderContextKM(hHWRenderContextInt,
2190 psSGXUnregHWRenderContextIN->bForceCleanup);
2189 if(psRetOUT->eError != PVRSRV_OK) 2191 if(psRetOUT->eError != PVRSRV_OK)
2190 { 2192 {
2191 return 0; 2193 return 0;
@@ -2270,7 +2272,8 @@ SGXUnregisterHWTransferContextBW(IMG_UINT32 ui32BridgeID,
2270 return 0; 2272 return 0;
2271 } 2273 }
2272 2274
2273 psRetOUT->eError = SGXUnregisterHWTransferContextKM(hHWTransferContextInt); 2275 psRetOUT->eError = SGXUnregisterHWTransferContextKM(hHWTransferContextInt,
2276 psSGXUnregHWTransferContextIN->bForceCleanup);
2274 if(psRetOUT->eError != PVRSRV_OK) 2277 if(psRetOUT->eError != PVRSRV_OK)
2275 { 2278 {
2276 return 0; 2279 return 0;
@@ -2352,7 +2355,8 @@ SGXUnregisterHW2DContextBW(IMG_UINT32 ui32BridgeID,
2352 return 0; 2355 return 0;
2353 } 2356 }
2354 2357
2355 psRetOUT->eError = SGXUnregisterHW2DContextKM(hHW2DContextInt); 2358 psRetOUT->eError = SGXUnregisterHW2DContextKM(hHW2DContextInt,
2359 psSGXUnregHW2DContextIN->bForceCleanup);
2356 if(psRetOUT->eError != PVRSRV_OK) 2360 if(psRetOUT->eError != PVRSRV_OK)
2357 { 2361 {
2358 return 0; 2362 return 0;
@@ -2386,7 +2390,7 @@ SGXFlushHWRenderTargetBW(IMG_UINT32 ui32BridgeID,
2386 return 0; 2390 return 0;
2387 } 2391 }
2388 2392
2389 SGXFlushHWRenderTargetKM(hDevCookieInt, psSGXFlushHWRenderTargetIN->sHWRTDataSetDevVAddr); 2393 psRetOUT->eError = SGXFlushHWRenderTargetKM(hDevCookieInt, psSGXFlushHWRenderTargetIN->sHWRTDataSetDevVAddr, IMG_FALSE);
2390 2394
2391 return 0; 2395 return 0;
2392} 2396}
diff --git a/drivers/gpu/pvr/sgx/mmu.c b/drivers/gpu/pvr/sgx/mmu.c
index 5a087cd449e..974973a5c28 100644
--- a/drivers/gpu/pvr/sgx/mmu.c
+++ b/drivers/gpu/pvr/sgx/mmu.c
@@ -79,6 +79,8 @@ typedef struct _MMU_PT_INFO_
79 79
80 IMG_VOID *hPTPageOSMemHandle; 80 IMG_VOID *hPTPageOSMemHandle;
81 IMG_CPU_VIRTADDR PTPageCpuVAddr; 81 IMG_CPU_VIRTADDR PTPageCpuVAddr;
82
83
82 IMG_UINT32 ui32ValidPTECount; 84 IMG_UINT32 ui32ValidPTECount;
83} MMU_PT_INFO; 85} MMU_PT_INFO;
84 86
@@ -2167,7 +2169,8 @@ MMU_UnmapPagesAndFreePTs (MMU_HEAP *psMMUHeap,
2167 2169
2168 2170
2169 2171
2170 if (ppsPTInfoList[0] && ppsPTInfoList[0]->ui32ValidPTECount == 0) 2172 if (ppsPTInfoList[0] && (ppsPTInfoList[0]->ui32ValidPTECount == 0)
2173 )
2171 { 2174 {
2172#if defined(FIX_HW_BRN_31620) 2175#if defined(FIX_HW_BRN_31620)
2173 if (BRN31620FreePageTable(psMMUHeap, ui32PDIndex) == IMG_TRUE) 2176 if (BRN31620FreePageTable(psMMUHeap, ui32PDIndex) == IMG_TRUE)
diff --git a/drivers/gpu/pvr/sgx/mmu.h b/drivers/gpu/pvr/sgx/mmu.h
index d224f649667..59b24c44ad8 100644
--- a/drivers/gpu/pvr/sgx/mmu.h
+++ b/drivers/gpu/pvr/sgx/mmu.h
@@ -145,6 +145,8 @@ IMG_VOID MMU_GetCacheFlushRange(MMU_CONTEXT *pMMUContext, IMG_UINT32 *pui32Range
145IMG_VOID MMU_GetPDPhysAddr(MMU_CONTEXT *pMMUContext, IMG_DEV_PHYADDR *psDevPAddr); 145IMG_VOID MMU_GetPDPhysAddr(MMU_CONTEXT *pMMUContext, IMG_DEV_PHYADDR *psDevPAddr);
146 146
147#endif 147#endif
148
149
148#if defined(PDUMP) 150#if defined(PDUMP)
149IMG_UINT32 MMU_GetPDumpContextID(IMG_HANDLE hDevMemContext); 151IMG_UINT32 MMU_GetPDumpContextID(IMG_HANDLE hDevMemContext);
150#endif 152#endif
diff --git a/drivers/gpu/pvr/sgx/pb.c b/drivers/gpu/pvr/sgx/pb.c
index d9825c726a3..ab6523a9927 100644
--- a/drivers/gpu/pvr/sgx/pb.c
+++ b/drivers/gpu/pvr/sgx/pb.c
@@ -47,8 +47,8 @@ static IMPLEMENT_LIST_REMOVE(PVRSRV_STUB_PBDESC)
47static PRESMAN_ITEM psResItemCreateSharedPB = IMG_NULL; 47static PRESMAN_ITEM psResItemCreateSharedPB = IMG_NULL;
48static PVRSRV_PER_PROCESS_DATA *psPerProcCreateSharedPB = IMG_NULL; 48static PVRSRV_PER_PROCESS_DATA *psPerProcCreateSharedPB = IMG_NULL;
49 49
50static PVRSRV_ERROR SGXCleanupSharedPBDescCallback(IMG_PVOID pvParam, IMG_UINT32 ui32Param); 50static PVRSRV_ERROR SGXCleanupSharedPBDescCallback(IMG_PVOID pvParam, IMG_UINT32 ui32Param, IMG_BOOL bDummy);
51static PVRSRV_ERROR SGXCleanupSharedPBDescCreateLockCallback(IMG_PVOID pvParam, IMG_UINT32 ui32Param); 51static PVRSRV_ERROR SGXCleanupSharedPBDescCreateLockCallback(IMG_PVOID pvParam, IMG_UINT32 ui32Param, IMG_BOOL bDummy);
52 52
53IMG_EXPORT PVRSRV_ERROR 53IMG_EXPORT PVRSRV_ERROR
54SGXFindSharedPBDescKM(PVRSRV_PER_PROCESS_DATA *psPerProc, 54SGXFindSharedPBDescKM(PVRSRV_PER_PROCESS_DATA *psPerProc,
@@ -217,22 +217,24 @@ SGXCleanupSharedPBDescKM(PVRSRV_STUB_PBDESC *psStubPBDescIn)
217 217
218 SGXCleanupRequest(psDeviceNode, 218 SGXCleanupRequest(psDeviceNode,
219 &sHWPBDescDevVAddr, 219 &sHWPBDescDevVAddr,
220 PVRSRV_CLEANUPCMD_PB); 220 PVRSRV_CLEANUPCMD_PB,
221 CLEANUP_WITH_POLL);
221 } 222 }
222 return PVRSRV_OK; 223 return PVRSRV_OK;
223 224
224} 225}
225 226
226static PVRSRV_ERROR SGXCleanupSharedPBDescCallback(IMG_PVOID pvParam, IMG_UINT32 ui32Param) 227static PVRSRV_ERROR SGXCleanupSharedPBDescCallback(IMG_PVOID pvParam, IMG_UINT32 ui32Param, IMG_BOOL bDummy)
227{ 228{
228 PVRSRV_STUB_PBDESC *psStubPBDesc = (PVRSRV_STUB_PBDESC *)pvParam; 229 PVRSRV_STUB_PBDESC *psStubPBDesc = (PVRSRV_STUB_PBDESC *)pvParam;
229 230
230 PVR_UNREFERENCED_PARAMETER(ui32Param); 231 PVR_UNREFERENCED_PARAMETER(ui32Param);
232 PVR_UNREFERENCED_PARAMETER(bDummy);
231 233
232 return SGXCleanupSharedPBDescKM(psStubPBDesc); 234 return SGXCleanupSharedPBDescKM(psStubPBDesc);
233} 235}
234 236
235static PVRSRV_ERROR SGXCleanupSharedPBDescCreateLockCallback(IMG_PVOID pvParam, IMG_UINT32 ui32Param) 237static PVRSRV_ERROR SGXCleanupSharedPBDescCreateLockCallback(IMG_PVOID pvParam, IMG_UINT32 ui32Param, IMG_BOOL bDummy)
236{ 238{
237#ifdef DEBUG 239#ifdef DEBUG
238 PVRSRV_PER_PROCESS_DATA *psPerProc = (PVRSRV_PER_PROCESS_DATA *)pvParam; 240 PVRSRV_PER_PROCESS_DATA *psPerProc = (PVRSRV_PER_PROCESS_DATA *)pvParam;
@@ -242,6 +244,7 @@ static PVRSRV_ERROR SGXCleanupSharedPBDescCreateLockCallback(IMG_PVOID pvParam,
242#endif 244#endif
243 245
244 PVR_UNREFERENCED_PARAMETER(ui32Param); 246 PVR_UNREFERENCED_PARAMETER(ui32Param);
247 PVR_UNREFERENCED_PARAMETER(bDummy);
245 248
246 psPerProcCreateSharedPB = IMG_NULL; 249 psPerProcCreateSharedPB = IMG_NULL;
247 psResItemCreateSharedPB = IMG_NULL; 250 psResItemCreateSharedPB = IMG_NULL;
@@ -255,7 +258,7 @@ SGXUnrefSharedPBDescKM(IMG_HANDLE hSharedPBDesc)
255{ 258{
256 PVR_ASSERT(hSharedPBDesc != IMG_NULL); 259 PVR_ASSERT(hSharedPBDesc != IMG_NULL);
257 260
258 return ResManFreeResByPtr(hSharedPBDesc); 261 return ResManFreeResByPtr(hSharedPBDesc, CLEANUP_WITH_POLL);
259} 262}
260 263
261 264
@@ -287,7 +290,7 @@ SGXAddSharedPBDescKM(PVRSRV_PER_PROCESS_DATA *psPerProc,
287 { 290 {
288 PVR_ASSERT(psResItemCreateSharedPB != IMG_NULL); 291 PVR_ASSERT(psResItemCreateSharedPB != IMG_NULL);
289 292
290 ResManFreeResByPtr(psResItemCreateSharedPB); 293 ResManFreeResByPtr(psResItemCreateSharedPB, CLEANUP_WITH_POLL);
291 294
292 PVR_ASSERT(psResItemCreateSharedPB == IMG_NULL); 295 PVR_ASSERT(psResItemCreateSharedPB == IMG_NULL);
293 PVR_ASSERT(psPerProcCreateSharedPB == IMG_NULL); 296 PVR_ASSERT(psPerProcCreateSharedPB == IMG_NULL);
diff --git a/drivers/gpu/pvr/sgx/sgxinit.c b/drivers/gpu/pvr/sgx/sgxinit.c
index f4d37fb1dab..edc56b60f78 100644
--- a/drivers/gpu/pvr/sgx/sgxinit.c
+++ b/drivers/gpu/pvr/sgx/sgxinit.c
@@ -1426,6 +1426,16 @@ PVRSRV_ERROR SGX_FreeMemTilingRange(PVRSRV_DEVICE_NODE *psDeviceNode,
1426} 1426}
1427#endif 1427#endif
1428 1428
1429static IMG_VOID SGXCacheInvalidate(PVRSRV_DEVICE_NODE *psDeviceNode)
1430{
1431 PVRSRV_SGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice;
1432
1433 #if defined(SGX_FEATURE_MP)
1434 psDevInfo->ui32CacheControl |= SGXMKIF_CC_INVAL_BIF_SL;
1435 #else
1436 PVR_UNREFERENCED_PARAMETER(psDevInfo);
1437 #endif
1438}
1429 1439
1430PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode) 1440PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode)
1431{ 1441{
@@ -1498,6 +1508,8 @@ PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode)
1498 1508
1499 psDeviceNode->pfnDeviceCommandComplete = &SGXCommandComplete; 1509 psDeviceNode->pfnDeviceCommandComplete = &SGXCommandComplete;
1500 1510
1511 psDeviceNode->pfnCacheInvalidate = SGXCacheInvalidate;
1512
1501 1513
1502 1514
1503 psDevMemoryInfo = &psDeviceNode->sDevMemoryInfo; 1515 psDevMemoryInfo = &psDeviceNode->sDevMemoryInfo;
diff --git a/drivers/gpu/pvr/sgx/sgxtransfer.c b/drivers/gpu/pvr/sgx/sgxtransfer.c
index d0d09bf8237..f125a3f26a3 100644
--- a/drivers/gpu/pvr/sgx/sgxtransfer.c
+++ b/drivers/gpu/pvr/sgx/sgxtransfer.c
@@ -61,6 +61,8 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
61 IMG_UINT32 ui32RealSrcSyncNum = 0; 61 IMG_UINT32 ui32RealSrcSyncNum = 0;
62 IMG_BOOL abDstSyncEnable[SGX_MAX_TRANSFER_SYNC_OPS]; 62 IMG_BOOL abDstSyncEnable[SGX_MAX_TRANSFER_SYNC_OPS];
63 IMG_UINT32 ui32RealDstSyncNum = 0; 63 IMG_UINT32 ui32RealDstSyncNum = 0;
64
65
64#if defined(PDUMP) 66#if defined(PDUMP)
65 IMG_BOOL bPersistentProcess = IMG_FALSE; 67 IMG_BOOL bPersistentProcess = IMG_FALSE;
66 68
@@ -76,6 +78,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
76 hDevMemContext = psKick->hDevMemContext; 78 hDevMemContext = psKick->hDevMemContext;
77#endif 79#endif
78 PVR_TTRACE(PVRSRV_TRACE_GROUP_TRANSFER, PVRSRV_TRACE_CLASS_FUNCTION_ENTER, TRANSFER_TOKEN_SUBMIT); 80 PVR_TTRACE(PVRSRV_TRACE_GROUP_TRANSFER, PVRSRV_TRACE_CLASS_FUNCTION_ENTER, TRANSFER_TOKEN_SUBMIT);
81
79 for (loop = 0; loop < SGX_MAX_TRANSFER_SYNC_OPS; loop++) 82 for (loop = 0; loop < SGX_MAX_TRANSFER_SYNC_OPS; loop++)
80 { 83 {
81 abSrcSyncEnable[loop] = IMG_TRUE; 84 abSrcSyncEnable[loop] = IMG_TRUE;
@@ -189,6 +192,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
189 192
190 psSharedTransferCmd->ui32NumSrcSyncs = ui32RealSrcSyncNum; 193 psSharedTransferCmd->ui32NumSrcSyncs = ui32RealSrcSyncNum;
191 psSharedTransferCmd->ui32NumDstSyncs = ui32RealDstSyncNum; 194 psSharedTransferCmd->ui32NumDstSyncs = ui32RealDstSyncNum;
195
192 if ((psKick->ui32Flags & SGXMKIF_TQFLAGS_KEEPPENDING) == 0UL) 196 if ((psKick->ui32Flags & SGXMKIF_TQFLAGS_KEEPPENDING) == 0UL)
193 { 197 {
194 IMG_UINT32 i = 0; 198 IMG_UINT32 i = 0;
@@ -196,11 +200,11 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
196 for (loop = 0; loop < psKick->ui32NumSrcSync; loop++) 200 for (loop = 0; loop < psKick->ui32NumSrcSync; loop++)
197 { 201 {
198 if (abSrcSyncEnable[loop]) 202 if (abSrcSyncEnable[loop])
199 { 203 {
200 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahSrcSyncInfo[loop]; 204 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahSrcSyncInfo[loop];
201 205
202 PVR_TTRACE_SYNC_OBJECT(PVRSRV_TRACE_GROUP_TRANSFER, TRANSFER_TOKEN_SRC_SYNC, 206 PVR_TTRACE_SYNC_OBJECT(PVRSRV_TRACE_GROUP_TRANSFER, TRANSFER_TOKEN_SRC_SYNC,
203 psSyncInfo, PVRSRV_SYNCOP_SAMPLE); 207 psSyncInfo, PVRSRV_SYNCOP_SAMPLE);
204 208
205 psSharedTransferCmd->asSrcSyncs[i].ui32WriteOpsPendingVal = psSyncInfo->psSyncData->ui32WriteOpsPending; 209 psSharedTransferCmd->asSrcSyncs[i].ui32WriteOpsPendingVal = psSyncInfo->psSyncData->ui32WriteOpsPending;
206 psSharedTransferCmd->asSrcSyncs[i].ui32ReadOpsPendingVal = psSyncInfo->psSyncData->ui32ReadOpsPending; 210 psSharedTransferCmd->asSrcSyncs[i].ui32ReadOpsPendingVal = psSyncInfo->psSyncData->ui32ReadOpsPending;
@@ -216,11 +220,11 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
216 for (loop = 0; loop < psKick->ui32NumDstSync; loop++) 220 for (loop = 0; loop < psKick->ui32NumDstSync; loop++)
217 { 221 {
218 if (abDstSyncEnable[loop]) 222 if (abDstSyncEnable[loop])
219 { 223 {
220 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahDstSyncInfo[loop]; 224 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahDstSyncInfo[loop];
221 225
222 PVR_TTRACE_SYNC_OBJECT(PVRSRV_TRACE_GROUP_TRANSFER, TRANSFER_TOKEN_DST_SYNC, 226 PVR_TTRACE_SYNC_OBJECT(PVRSRV_TRACE_GROUP_TRANSFER, TRANSFER_TOKEN_DST_SYNC,
223 psSyncInfo, PVRSRV_SYNCOP_SAMPLE); 227 psSyncInfo, PVRSRV_SYNCOP_SAMPLE);
224 228
225 psSharedTransferCmd->asDstSyncs[i].ui32WriteOpsPendingVal = psSyncInfo->psSyncData->ui32WriteOpsPending; 229 psSharedTransferCmd->asDstSyncs[i].ui32WriteOpsPendingVal = psSyncInfo->psSyncData->ui32WriteOpsPending;
226 psSharedTransferCmd->asDstSyncs[i].ui32ReadOpsPendingVal = psSyncInfo->psSyncData->ui32ReadOpsPending; 230 psSharedTransferCmd->asDstSyncs[i].ui32ReadOpsPendingVal = psSyncInfo->psSyncData->ui32ReadOpsPending;
@@ -228,8 +232,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
228 psSharedTransferCmd->asDstSyncs[i].sWriteOpsCompleteDevVAddr = psSyncInfo->sWriteOpsCompleteDevVAddr; 232 psSharedTransferCmd->asDstSyncs[i].sWriteOpsCompleteDevVAddr = psSyncInfo->sWriteOpsCompleteDevVAddr;
229 psSharedTransferCmd->asDstSyncs[i].sReadOpsCompleteDevVAddr = psSyncInfo->sReadOpsCompleteDevVAddr; 233 psSharedTransferCmd->asDstSyncs[i].sReadOpsCompleteDevVAddr = psSyncInfo->sReadOpsCompleteDevVAddr;
230 i++; 234 i++;
231 235 }
232 }
233 } 236 }
234 PVR_ASSERT(i == ui32RealDstSyncNum); 237 PVR_ASSERT(i == ui32RealDstSyncNum);
235 238
@@ -237,17 +240,17 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
237 for (loop = 0; loop < psKick->ui32NumSrcSync; loop++) 240 for (loop = 0; loop < psKick->ui32NumSrcSync; loop++)
238 { 241 {
239 if (abSrcSyncEnable[loop]) 242 if (abSrcSyncEnable[loop])
240 { 243 {
241 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahSrcSyncInfo[loop]; 244 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahSrcSyncInfo[loop];
242 psSyncInfo->psSyncData->ui32ReadOpsPending++; 245 psSyncInfo->psSyncData->ui32ReadOpsPending++;
243 } 246 }
244 } 247 }
245 for (loop = 0; loop < psKick->ui32NumDstSync; loop++) 248 for (loop = 0; loop < psKick->ui32NumDstSync; loop++)
246 { 249 {
247 if (abDstSyncEnable[loop]) 250 if (abDstSyncEnable[loop])
248 { 251 {
249 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahDstSyncInfo[loop]; 252 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahDstSyncInfo[loop];
250 psSyncInfo->psSyncData->ui32WriteOpsPending++; 253 psSyncInfo->psSyncData->ui32WriteOpsPending++;
251 } 254 }
252 } 255 }
253 } 256 }
@@ -272,74 +275,73 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
272 for (loop = 0; loop < psKick->ui32NumSrcSync; loop++) 275 for (loop = 0; loop < psKick->ui32NumSrcSync; loop++)
273 { 276 {
274 if (abSrcSyncEnable[loop]) 277 if (abSrcSyncEnable[loop])
275 { 278 {
276 psSyncInfo = psKick->ahSrcSyncInfo[loop]; 279 psSyncInfo = psKick->ahSrcSyncInfo[loop];
277 280
278 PDUMPCOMMENT("Hack src surface write op in transfer cmd\r\n"); 281 PDUMPCOMMENT("Hack src surface write op in transfer cmd\r\n");
279 PDUMPMEM(&psSyncInfo->psSyncData->ui32LastOpDumpVal, 282 PDUMPMEM(&psSyncInfo->psSyncData->ui32LastOpDumpVal,
280 psCCBMemInfo, 283 psCCBMemInfo,
281 psKick->ui32CCBDumpWOff + (IMG_UINT32)(offsetof(SGXMKIF_TRANSFERCMD_SHARED, asSrcSyncs) + i * sizeof(PVRSRV_DEVICE_SYNC_OBJECT) + offsetof(PVRSRV_DEVICE_SYNC_OBJECT, ui32WriteOpsPendingVal)), 284 psKick->ui32CCBDumpWOff + (IMG_UINT32)(offsetof(SGXMKIF_TRANSFERCMD_SHARED, asSrcSyncs) + i * sizeof(PVRSRV_DEVICE_SYNC_OBJECT) + offsetof(PVRSRV_DEVICE_SYNC_OBJECT, ui32WriteOpsPendingVal)),
282 sizeof(psSyncInfo->psSyncData->ui32LastOpDumpVal), 285 sizeof(psSyncInfo->psSyncData->ui32LastOpDumpVal),
283 psKick->ui32PDumpFlags, 286 psKick->ui32PDumpFlags,
284 MAKEUNIQUETAG(psCCBMemInfo)); 287 MAKEUNIQUETAG(psCCBMemInfo));
285 288
286 PDUMPCOMMENT("Hack src surface read op in transfer cmd\r\n"); 289 PDUMPCOMMENT("Hack src surface read op in transfer cmd\r\n");
287 PDUMPMEM(&psSyncInfo->psSyncData->ui32LastReadOpDumpVal, 290 PDUMPMEM(&psSyncInfo->psSyncData->ui32LastReadOpDumpVal,
288 psCCBMemInfo, 291 psCCBMemInfo,
289 psKick->ui32CCBDumpWOff + (IMG_UINT32)(offsetof(SGXMKIF_TRANSFERCMD_SHARED, asSrcSyncs) + i * sizeof(PVRSRV_DEVICE_SYNC_OBJECT) + offsetof(PVRSRV_DEVICE_SYNC_OBJECT, ui32ReadOpsPendingVal)), 292 psKick->ui32CCBDumpWOff + (IMG_UINT32)(offsetof(SGXMKIF_TRANSFERCMD_SHARED, asSrcSyncs) + i * sizeof(PVRSRV_DEVICE_SYNC_OBJECT) + offsetof(PVRSRV_DEVICE_SYNC_OBJECT, ui32ReadOpsPendingVal)),
290 sizeof(psSyncInfo->psSyncData->ui32LastReadOpDumpVal), 293 sizeof(psSyncInfo->psSyncData->ui32LastReadOpDumpVal),
291 psKick->ui32PDumpFlags, 294 psKick->ui32PDumpFlags,
292 MAKEUNIQUETAG(psCCBMemInfo)); 295 MAKEUNIQUETAG(psCCBMemInfo));
293
294 i++; 296 i++;
297 }
295 } 298 }
296 } 299
297 i = 0; 300 i = 0;
298 for (loop = 0; loop < psKick->ui32NumDstSync; loop++) 301 for (loop = 0; loop < psKick->ui32NumDstSync; loop++)
299 {
300 if (abDstSyncEnable[i])
301 { 302 {
302 psSyncInfo = psKick->ahDstSyncInfo[loop]; 303 if (abDstSyncEnable[i])
303 304 {
304 PDUMPCOMMENT("Hack dest surface write op in transfer cmd\r\n"); 305 psSyncInfo = psKick->ahDstSyncInfo[loop];
305 PDUMPMEM(&psSyncInfo->psSyncData->ui32LastOpDumpVal, 306
306 psCCBMemInfo, 307 PDUMPCOMMENT("Hack dest surface write op in transfer cmd\r\n");
308 PDUMPMEM(&psSyncInfo->psSyncData->ui32LastOpDumpVal,
309 psCCBMemInfo,
307 psKick->ui32CCBDumpWOff + (IMG_UINT32)(offsetof(SGXMKIF_TRANSFERCMD_SHARED, asDstSyncs) + i * sizeof(PVRSRV_DEVICE_SYNC_OBJECT) + offsetof(PVRSRV_DEVICE_SYNC_OBJECT, ui32WriteOpsPendingVal)), 310 psKick->ui32CCBDumpWOff + (IMG_UINT32)(offsetof(SGXMKIF_TRANSFERCMD_SHARED, asDstSyncs) + i * sizeof(PVRSRV_DEVICE_SYNC_OBJECT) + offsetof(PVRSRV_DEVICE_SYNC_OBJECT, ui32WriteOpsPendingVal)),
308 sizeof(psSyncInfo->psSyncData->ui32LastOpDumpVal), 311 sizeof(psSyncInfo->psSyncData->ui32LastOpDumpVal),
309 psKick->ui32PDumpFlags, 312 psKick->ui32PDumpFlags,
310 MAKEUNIQUETAG(psCCBMemInfo)); 313 MAKEUNIQUETAG(psCCBMemInfo));
311 314
312 PDUMPCOMMENT("Hack dest surface read op in transfer cmd\r\n"); 315 PDUMPCOMMENT("Hack dest surface read op in transfer cmd\r\n");
313 PDUMPMEM(&psSyncInfo->psSyncData->ui32LastReadOpDumpVal, 316 PDUMPMEM(&psSyncInfo->psSyncData->ui32LastReadOpDumpVal,
314 psCCBMemInfo, 317 psCCBMemInfo,
315 psKick->ui32CCBDumpWOff + (IMG_UINT32)(offsetof(SGXMKIF_TRANSFERCMD_SHARED, asDstSyncs) + i * sizeof(PVRSRV_DEVICE_SYNC_OBJECT) + offsetof(PVRSRV_DEVICE_SYNC_OBJECT, ui32ReadOpsPendingVal)), 318 psKick->ui32CCBDumpWOff + (IMG_UINT32)(offsetof(SGXMKIF_TRANSFERCMD_SHARED, asDstSyncs) + i * sizeof(PVRSRV_DEVICE_SYNC_OBJECT) + offsetof(PVRSRV_DEVICE_SYNC_OBJECT, ui32ReadOpsPendingVal)),
316 sizeof(psSyncInfo->psSyncData->ui32LastReadOpDumpVal), 319 sizeof(psSyncInfo->psSyncData->ui32LastReadOpDumpVal),
317 psKick->ui32PDumpFlags, 320 psKick->ui32PDumpFlags,
318 MAKEUNIQUETAG(psCCBMemInfo)); 321 MAKEUNIQUETAG(psCCBMemInfo));
319
320 i++; 322 i++;
323 }
321 } 324 }
322 }
323 325
324 326
325 for (loop = 0; loop < (psKick->ui32NumSrcSync); loop++) 327 for (loop = 0; loop < (psKick->ui32NumSrcSync); loop++)
326 { 328 {
327 if (abSrcSyncEnable[loop]) 329 if (abSrcSyncEnable[loop])
328 { 330 {
329 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahSrcSyncInfo[loop]; 331 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahSrcSyncInfo[loop];
330 psSyncInfo->psSyncData->ui32LastReadOpDumpVal++; 332 psSyncInfo->psSyncData->ui32LastReadOpDumpVal++;
333 }
331 } 334 }
332 }
333 335
334 for (loop = 0; loop < (psKick->ui32NumDstSync); loop++) 336 for (loop = 0; loop < (psKick->ui32NumDstSync); loop++)
335 {
336 if (abDstSyncEnable[loop])
337 { 337 {
338 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahDstSyncInfo[0]; 338 if (abDstSyncEnable[loop])
339 psSyncInfo->psSyncData->ui32LastOpDumpVal++; 339 {
340 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahDstSyncInfo[0];
341 psSyncInfo->psSyncData->ui32LastOpDumpVal++;
342 }
340 } 343 }
341 } 344 }
342 }
343 } 345 }
344#endif 346#endif
345 347
@@ -360,13 +362,13 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
360 if (abSrcSyncEnable[loop]) 362 if (abSrcSyncEnable[loop])
361 { 363 {
362 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahSrcSyncInfo[loop]; 364 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahSrcSyncInfo[loop];
363 psSyncInfo->psSyncData->ui32ReadOpsPending--; 365 psSyncInfo->psSyncData->ui32ReadOpsPending--;
364#if defined(PDUMP) 366#if defined(PDUMP)
365 if (PDumpIsCaptureFrameKM() 367 if (PDumpIsCaptureFrameKM()
366 || ((psKick->ui32PDumpFlags & PDUMP_FLAGS_CONTINUOUS) != 0)) 368 || ((psKick->ui32PDumpFlags & PDUMP_FLAGS_CONTINUOUS) != 0))
367 { 369 {
368 psSyncInfo->psSyncData->ui32LastReadOpDumpVal--; 370 psSyncInfo->psSyncData->ui32LastReadOpDumpVal--;
369 } 371 }
370#endif 372#endif
371 } 373 }
372 } 374 }
@@ -380,10 +382,10 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
380 if (PDumpIsCaptureFrameKM() 382 if (PDumpIsCaptureFrameKM()
381 || ((psKick->ui32PDumpFlags & PDUMP_FLAGS_CONTINUOUS) != 0)) 383 || ((psKick->ui32PDumpFlags & PDUMP_FLAGS_CONTINUOUS) != 0))
382 { 384 {
383 psSyncInfo->psSyncData->ui32LastOpDumpVal--; 385 psSyncInfo->psSyncData->ui32LastOpDumpVal--;
384 } 386 }
385#endif 387#endif
386 } 388 }
387 } 389 }
388 } 390 }
389 391
@@ -420,8 +422,8 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
420 if (abSrcSyncEnable[loop]) 422 if (abSrcSyncEnable[loop])
421 { 423 {
422 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahSrcSyncInfo[loop]; 424 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahSrcSyncInfo[loop];
423 psSyncInfo->psSyncData->ui32ReadOpsComplete = psSyncInfo->psSyncData->ui32ReadOpsPending; 425 psSyncInfo->psSyncData->ui32ReadOpsComplete = psSyncInfo->psSyncData->ui32ReadOpsPending;
424 } 426 }
425 } 427 }
426 428
427 for (loop = 0; loop < psKick->ui32NumDstSync; loop++) 429 for (loop = 0; loop < psKick->ui32NumDstSync; loop++)
@@ -429,8 +431,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
429 if (abDstSyncEnable[loop]) 431 if (abDstSyncEnable[loop])
430 { 432 {
431 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahDstSyncInfo[loop]; 433 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahDstSyncInfo[loop];
432 psSyncInfo->psSyncData->ui32WriteOpsComplete = psSyncInfo->psSyncData->ui32WriteOpsPending; 434 psSyncInfo->psSyncData->ui32WriteOpsComplete = psSyncInfo->psSyncData->ui32WriteOpsPending;
433
434 } 435 }
435 } 436 }
436 437
diff --git a/drivers/gpu/pvr/sgx/sgxutils.c b/drivers/gpu/pvr/sgx/sgxutils.c
index cf7ecc68d93..75b1b893200 100644
--- a/drivers/gpu/pvr/sgx/sgxutils.c
+++ b/drivers/gpu/pvr/sgx/sgxutils.c
@@ -206,7 +206,7 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_DEVICE_NODE *psDeviceNode,
206 206
207 207
208 208
209 if ( (eCmdType != SGXMKIF_CMD_PROCESS_QUEUES) && 209 if ( (eCmdType != SGXMKIF_CMD_PROCESS_QUEUES) &&
210 ((psDevInfo->ui32CacheControl & SGXMKIF_CC_INVAL_DATA) != 0) && 210 ((psDevInfo->ui32CacheControl & SGXMKIF_CC_INVAL_DATA) != 0) &&
211 ((psDevInfo->ui32CacheControl & (SGXMKIF_CC_INVAL_BIF_PT | SGXMKIF_CC_INVAL_BIF_PD)) != 0)) 211 ((psDevInfo->ui32CacheControl & (SGXMKIF_CC_INVAL_BIF_PT | SGXMKIF_CC_INVAL_BIF_PD)) != 0))
212 { 212 {
@@ -227,7 +227,7 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_DEVICE_NODE *psDeviceNode,
227 { 227 {
228 goto Exit; 228 goto Exit;
229 } 229 }
230 230
231 231
232 #if !defined(NO_HARDWARE) 232 #if !defined(NO_HARDWARE)
233 if(PollForValueKM(&psSGXHostCtl->ui32InvalStatus, 233 if(PollForValueKM(&psSGXHostCtl->ui32InvalStatus,
@@ -241,7 +241,7 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_DEVICE_NODE *psDeviceNode,
241 PVR_DBG_BREAK; 241 PVR_DBG_BREAK;
242 } 242 }
243 #endif 243 #endif
244 244
245 #if defined(PDUMP) 245 #if defined(PDUMP)
246 246
247 PDUMPCOMMENTWITHFLAGS(0, "Host Control - Poll for BIF cache invalidate request to complete"); 247 PDUMPCOMMENTWITHFLAGS(0, "Host Control - Poll for BIF cache invalidate request to complete");
@@ -253,14 +253,14 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_DEVICE_NODE *psDeviceNode,
253 0, 253 0,
254 MAKEUNIQUETAG(psSGXHostCtlMemInfo)); 254 MAKEUNIQUETAG(psSGXHostCtlMemInfo));
255 #endif 255 #endif
256 256
257 psSGXHostCtl->ui32InvalStatus &= ~(PVRSRV_USSE_EDM_BIF_INVAL_COMPLETE); 257 psSGXHostCtl->ui32InvalStatus &= ~(PVRSRV_USSE_EDM_BIF_INVAL_COMPLETE);
258 PDUMPMEM(IMG_NULL, psSGXHostCtlMemInfo, offsetof(SGXMKIF_HOST_CTL, ui32CleanupStatus), sizeof(IMG_UINT32), 0, MAKEUNIQUETAG(psSGXHostCtlMemInfo)); 258 PDUMPMEM(IMG_NULL, psSGXHostCtlMemInfo, offsetof(SGXMKIF_HOST_CTL, ui32CleanupStatus), sizeof(IMG_UINT32), 0, MAKEUNIQUETAG(psSGXHostCtlMemInfo));
259 } 259 }
260#else 260#else
261 PVR_UNREFERENCED_PARAMETER(hDevMemContext); 261 PVR_UNREFERENCED_PARAMETER(hDevMemContext);
262#endif 262#endif
263 263
264#if defined(FIX_HW_BRN_31620) 264#if defined(FIX_HW_BRN_31620)
265 if ((eCmdType != SGXMKIF_CMD_FLUSHPDCACHE) && (psDevInfo->ui32CacheControl & SGXMKIF_CC_INVAL_BIF_PD)) 265 if ((eCmdType != SGXMKIF_CMD_FLUSHPDCACHE) && (psDevInfo->ui32CacheControl & SGXMKIF_CC_INVAL_BIF_PD))
266 { 266 {
@@ -636,9 +636,10 @@ PVRSRV_ERROR SGXGetInternalDevInfoKM(IMG_HANDLE hDevCookie,
636} 636}
637 637
638 638
639IMG_VOID SGXCleanupRequest(PVRSRV_DEVICE_NODE *psDeviceNode, 639PVRSRV_ERROR SGXCleanupRequest(PVRSRV_DEVICE_NODE *psDeviceNode,
640 IMG_DEV_VIRTADDR *psHWDataDevVAddr, 640 IMG_DEV_VIRTADDR *psHWDataDevVAddr,
641 IMG_UINT32 ui32CleanupType) 641 IMG_UINT32 ui32CleanupType,
642 IMG_BOOL bForceCleanup)
642{ 643{
643 PVRSRV_ERROR eError; 644 PVRSRV_ERROR eError;
644 PVRSRV_SGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice; 645 PVRSRV_SGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice;
@@ -647,52 +648,64 @@ IMG_VOID SGXCleanupRequest(PVRSRV_DEVICE_NODE *psDeviceNode,
647 648
648 SGXMKIF_COMMAND sCommand = {0}; 649 SGXMKIF_COMMAND sCommand = {0};
649 650
650 sCommand.ui32Data[0] = ui32CleanupType;
651 sCommand.ui32Data[1] = (psHWDataDevVAddr == IMG_NULL) ? 0 : psHWDataDevVAddr->uiAddr;
652 PDUMPCOMMENTWITHFLAGS(0, "Request ukernel resource clean-up, Type %u, Data 0x%X", sCommand.ui32Data[0], sCommand.ui32Data[1]);
653 651
654 eError = SGXScheduleCCBCommandKM(psDeviceNode, SGXMKIF_CMD_CLEANUP, &sCommand, KERNEL_ID, 0, IMG_NULL, IMG_FALSE); 652 if (bForceCleanup != FORCE_CLEANUP)
655 if (eError != PVRSRV_OK)
656 { 653 {
657 PVR_DPF((PVR_DBG_ERROR,"SGXCleanupRequest: Failed to submit clean-up command")); 654 sCommand.ui32Data[0] = ui32CleanupType;
658 PVR_DBG_BREAK; 655 sCommand.ui32Data[1] = (psHWDataDevVAddr == IMG_NULL) ? 0 : psHWDataDevVAddr->uiAddr;
659 } 656 PDUMPCOMMENTWITHFLAGS(0, "Request ukernel resource clean-up, Type %u, Data 0x%X", sCommand.ui32Data[0], sCommand.ui32Data[1]);
660
661 657
662 #if !defined(NO_HARDWARE) 658 eError = SGXScheduleCCBCommandKM(psDeviceNode, SGXMKIF_CMD_CLEANUP, &sCommand, KERNEL_ID, 0, IMG_NULL, IMG_FALSE);
663 if(PollForValueKM(&psHostCtl->ui32CleanupStatus, 659 if (eError != PVRSRV_OK)
664 PVRSRV_USSE_EDM_CLEANUPCMD_COMPLETE, 660 {
665 PVRSRV_USSE_EDM_CLEANUPCMD_COMPLETE, 661 PVR_DPF((PVR_DBG_ERROR,"SGXCleanupRequest: Failed to submit clean-up command"));
666 10 * MAX_HW_TIME_US, 662 PVR_DBG_BREAK;
667 1000, 663 return eError;
668 IMG_TRUE) != PVRSRV_OK) 664 }
669 {
670 PVR_DPF((PVR_DBG_ERROR,"SGXCleanupRequest: Wait for uKernel to clean up (%u) failed", ui32CleanupType));
671 PVR_DBG_BREAK;
672 }
673 #endif
674 665
675 #if defined(PDUMP)
676
677 PDUMPCOMMENTWITHFLAGS(0, "Host Control - Poll for clean-up request to complete");
678 PDUMPMEMPOL(psHostCtlMemInfo,
679 offsetof(SGXMKIF_HOST_CTL, ui32CleanupStatus),
680 PVRSRV_USSE_EDM_CLEANUPCMD_COMPLETE,
681 PVRSRV_USSE_EDM_CLEANUPCMD_COMPLETE,
682 PDUMP_POLL_OPERATOR_EQUAL,
683 0,
684 MAKEUNIQUETAG(psHostCtlMemInfo));
685 #endif
686 666
667 #if !defined(NO_HARDWARE)
668 if(PollForValueKM(&psHostCtl->ui32CleanupStatus,
669 PVRSRV_USSE_EDM_CLEANUPCMD_COMPLETE,
670 PVRSRV_USSE_EDM_CLEANUPCMD_COMPLETE,
671 10 * MAX_HW_TIME_US,
672 1000,
673 IMG_TRUE) != PVRSRV_OK)
674 {
675 PVR_DPF((PVR_DBG_ERROR,"SGXCleanupRequest: Wait for uKernel to clean up (%u) failed", ui32CleanupType));
676 eError = PVRSRV_ERROR_TIMEOUT;
677 PVR_DBG_BREAK;
678 }
679 #endif
680
681 #if defined(PDUMP)
682
683 PDUMPCOMMENTWITHFLAGS(0, "Host Control - Poll for clean-up request to complete");
684 PDUMPMEMPOL(psHostCtlMemInfo,
685 offsetof(SGXMKIF_HOST_CTL, ui32CleanupStatus),
686 PVRSRV_USSE_EDM_CLEANUPCMD_COMPLETE,
687 PVRSRV_USSE_EDM_CLEANUPCMD_COMPLETE,
688 PDUMP_POLL_OPERATOR_EQUAL,
689 0,
690 MAKEUNIQUETAG(psHostCtlMemInfo));
691 #endif
692
693 if (eError != PVRSRV_OK)
694 {
695 return eError;
696 }
697 }
698
687 psHostCtl->ui32CleanupStatus &= ~(PVRSRV_USSE_EDM_CLEANUPCMD_COMPLETE); 699 psHostCtl->ui32CleanupStatus &= ~(PVRSRV_USSE_EDM_CLEANUPCMD_COMPLETE);
688 PDUMPMEM(IMG_NULL, psHostCtlMemInfo, offsetof(SGXMKIF_HOST_CTL, ui32CleanupStatus), sizeof(IMG_UINT32), 0, MAKEUNIQUETAG(psHostCtlMemInfo)); 700 PDUMPMEM(IMG_NULL, psHostCtlMemInfo, offsetof(SGXMKIF_HOST_CTL, ui32CleanupStatus), sizeof(IMG_UINT32), 0, MAKEUNIQUETAG(psHostCtlMemInfo));
689 701
690 702
691#if defined(SGX_FEATURE_SYSTEM_CACHE) 703#if defined(SGX_FEATURE_SYSTEM_CACHE)
692 psDevInfo->ui32CacheControl |= (SGXMKIF_CC_INVAL_BIF_SL | SGXMKIF_CC_INVAL_DATA); 704 psDevInfo->ui32CacheControl |= (SGXMKIF_CC_INVAL_BIF_SL | SGXMKIF_CC_INVAL_DATA);
693#else 705#else
694 psDevInfo->ui32CacheControl |= SGXMKIF_CC_INVAL_DATA; 706 psDevInfo->ui32CacheControl |= SGXMKIF_CC_INVAL_DATA;
695#endif 707#endif
708 return PVRSRV_OK;
696} 709}
697 710
698 711
@@ -706,15 +719,18 @@ typedef struct _SGX_HW_RENDER_CONTEXT_CLEANUP_
706 719
707 720
708static PVRSRV_ERROR SGXCleanupHWRenderContextCallback(IMG_PVOID pvParam, 721static PVRSRV_ERROR SGXCleanupHWRenderContextCallback(IMG_PVOID pvParam,
709 IMG_UINT32 ui32Param) 722 IMG_UINT32 ui32Param,
723 IMG_BOOL bForceCleanup)
710{ 724{
725 PVRSRV_ERROR eError;
711 SGX_HW_RENDER_CONTEXT_CLEANUP *psCleanup = pvParam; 726 SGX_HW_RENDER_CONTEXT_CLEANUP *psCleanup = pvParam;
712 727
713 PVR_UNREFERENCED_PARAMETER(ui32Param); 728 PVR_UNREFERENCED_PARAMETER(ui32Param);
714 729
715 SGXCleanupRequest(psCleanup->psDeviceNode, 730 eError = SGXCleanupRequest(psCleanup->psDeviceNode,
716 &psCleanup->sHWRenderContextDevVAddr, 731 &psCleanup->sHWRenderContextDevVAddr,
717 PVRSRV_CLEANUPCMD_RC); 732 PVRSRV_CLEANUPCMD_RC,
733 bForceCleanup);
718 734
719 OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, 735 OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP,
720 sizeof(SGX_HW_RENDER_CONTEXT_CLEANUP), 736 sizeof(SGX_HW_RENDER_CONTEXT_CLEANUP),
@@ -722,7 +738,7 @@ static PVRSRV_ERROR SGXCleanupHWRenderContextCallback(IMG_PVOID pvParam,
722 psCleanup->hBlockAlloc); 738 psCleanup->hBlockAlloc);
723 739
724 740
725 return PVRSRV_OK; 741 return eError;
726} 742}
727 743
728typedef struct _SGX_HW_TRANSFER_CONTEXT_CLEANUP_ 744typedef struct _SGX_HW_TRANSFER_CONTEXT_CLEANUP_
@@ -735,15 +751,18 @@ typedef struct _SGX_HW_TRANSFER_CONTEXT_CLEANUP_
735 751
736 752
737static PVRSRV_ERROR SGXCleanupHWTransferContextCallback(IMG_PVOID pvParam, 753static PVRSRV_ERROR SGXCleanupHWTransferContextCallback(IMG_PVOID pvParam,
738 IMG_UINT32 ui32Param) 754 IMG_UINT32 ui32Param,
755 IMG_BOOL bForceCleanup)
739{ 756{
757 PVRSRV_ERROR eError;
740 SGX_HW_TRANSFER_CONTEXT_CLEANUP *psCleanup = (SGX_HW_TRANSFER_CONTEXT_CLEANUP *)pvParam; 758 SGX_HW_TRANSFER_CONTEXT_CLEANUP *psCleanup = (SGX_HW_TRANSFER_CONTEXT_CLEANUP *)pvParam;
741 759
742 PVR_UNREFERENCED_PARAMETER(ui32Param); 760 PVR_UNREFERENCED_PARAMETER(ui32Param);
743 761
744 SGXCleanupRequest(psCleanup->psDeviceNode, 762 eError = SGXCleanupRequest(psCleanup->psDeviceNode,
745 &psCleanup->sHWTransferContextDevVAddr, 763 &psCleanup->sHWTransferContextDevVAddr,
746 PVRSRV_CLEANUPCMD_TC); 764 PVRSRV_CLEANUPCMD_TC,
765 bForceCleanup);
747 766
748 OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, 767 OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP,
749 sizeof(SGX_HW_TRANSFER_CONTEXT_CLEANUP), 768 sizeof(SGX_HW_TRANSFER_CONTEXT_CLEANUP),
@@ -751,7 +770,7 @@ static PVRSRV_ERROR SGXCleanupHWTransferContextCallback(IMG_PVOID pvParam,
751 psCleanup->hBlockAlloc); 770 psCleanup->hBlockAlloc);
752 771
753 772
754 return PVRSRV_OK; 773 return eError;
755} 774}
756 775
757IMG_EXPORT 776IMG_EXPORT
@@ -804,7 +823,7 @@ IMG_HANDLE SGXRegisterHWRenderContextKM(IMG_HANDLE psDeviceNode,
804} 823}
805 824
806IMG_EXPORT 825IMG_EXPORT
807PVRSRV_ERROR SGXUnregisterHWRenderContextKM(IMG_HANDLE hHWRenderContext) 826PVRSRV_ERROR SGXUnregisterHWRenderContextKM(IMG_HANDLE hHWRenderContext, IMG_BOOL bForceCleanup)
808{ 827{
809 PVRSRV_ERROR eError; 828 PVRSRV_ERROR eError;
810 SGX_HW_RENDER_CONTEXT_CLEANUP *psCleanup; 829 SGX_HW_RENDER_CONTEXT_CLEANUP *psCleanup;
@@ -819,7 +838,7 @@ PVRSRV_ERROR SGXUnregisterHWRenderContextKM(IMG_HANDLE hHWRenderContext)
819 return PVRSRV_ERROR_INVALID_PARAMS; 838 return PVRSRV_ERROR_INVALID_PARAMS;
820 } 839 }
821 840
822 eError = ResManFreeResByPtr(psCleanup->psResItem); 841 eError = ResManFreeResByPtr(psCleanup->psResItem, bForceCleanup);
823 842
824 return eError; 843 return eError;
825} 844}
@@ -875,7 +894,7 @@ IMG_HANDLE SGXRegisterHWTransferContextKM(IMG_HANDLE psDeviceNode,
875} 894}
876 895
877IMG_EXPORT 896IMG_EXPORT
878PVRSRV_ERROR SGXUnregisterHWTransferContextKM(IMG_HANDLE hHWTransferContext) 897PVRSRV_ERROR SGXUnregisterHWTransferContextKM(IMG_HANDLE hHWTransferContext, IMG_BOOL bForceCleanup)
879{ 898{
880 PVRSRV_ERROR eError; 899 PVRSRV_ERROR eError;
881 SGX_HW_TRANSFER_CONTEXT_CLEANUP *psCleanup; 900 SGX_HW_TRANSFER_CONTEXT_CLEANUP *psCleanup;
@@ -890,7 +909,7 @@ PVRSRV_ERROR SGXUnregisterHWTransferContextKM(IMG_HANDLE hHWTransferContext)
890 return PVRSRV_ERROR_INVALID_PARAMS; 909 return PVRSRV_ERROR_INVALID_PARAMS;
891 } 910 }
892 911
893 eError = ResManFreeResByPtr(psCleanup->psResItem); 912 eError = ResManFreeResByPtr(psCleanup->psResItem, bForceCleanup);
894 913
895 return eError; 914 return eError;
896} 915}
@@ -904,15 +923,19 @@ typedef struct _SGX_HW_2D_CONTEXT_CLEANUP_
904 PRESMAN_ITEM psResItem; 923 PRESMAN_ITEM psResItem;
905} SGX_HW_2D_CONTEXT_CLEANUP; 924} SGX_HW_2D_CONTEXT_CLEANUP;
906 925
907static PVRSRV_ERROR SGXCleanupHW2DContextCallback(IMG_PVOID pvParam, IMG_UINT32 ui32Param) 926static PVRSRV_ERROR SGXCleanupHW2DContextCallback(IMG_PVOID pvParam,
927 IMG_UINT32 ui32Param,
928 IMG_BOOL bForceCleanup)
908{ 929{
930 PVRSRV_ERROR eError;
909 SGX_HW_2D_CONTEXT_CLEANUP *psCleanup = (SGX_HW_2D_CONTEXT_CLEANUP *)pvParam; 931 SGX_HW_2D_CONTEXT_CLEANUP *psCleanup = (SGX_HW_2D_CONTEXT_CLEANUP *)pvParam;
910 932
911 PVR_UNREFERENCED_PARAMETER(ui32Param); 933 PVR_UNREFERENCED_PARAMETER(ui32Param);
912 934
913 SGXCleanupRequest(psCleanup->psDeviceNode, 935 eError = SGXCleanupRequest(psCleanup->psDeviceNode,
914 &psCleanup->sHW2DContextDevVAddr, 936 &psCleanup->sHW2DContextDevVAddr,
915 PVRSRV_CLEANUPCMD_2DC); 937 PVRSRV_CLEANUPCMD_2DC,
938 bForceCleanup);
916 939
917 OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, 940 OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP,
918 sizeof(SGX_HW_2D_CONTEXT_CLEANUP), 941 sizeof(SGX_HW_2D_CONTEXT_CLEANUP),
@@ -920,7 +943,7 @@ static PVRSRV_ERROR SGXCleanupHW2DContextCallback(IMG_PVOID pvParam, IMG_UINT32
920 psCleanup->hBlockAlloc); 943 psCleanup->hBlockAlloc);
921 944
922 945
923 return PVRSRV_OK; 946 return eError;
924} 947}
925 948
926IMG_EXPORT 949IMG_EXPORT
@@ -973,7 +996,7 @@ IMG_HANDLE SGXRegisterHW2DContextKM(IMG_HANDLE psDeviceNode,
973} 996}
974 997
975IMG_EXPORT 998IMG_EXPORT
976PVRSRV_ERROR SGXUnregisterHW2DContextKM(IMG_HANDLE hHW2DContext) 999PVRSRV_ERROR SGXUnregisterHW2DContextKM(IMG_HANDLE hHW2DContext, IMG_BOOL bForceCleanup)
977{ 1000{
978 PVRSRV_ERROR eError; 1001 PVRSRV_ERROR eError;
979 SGX_HW_2D_CONTEXT_CLEANUP *psCleanup; 1002 SGX_HW_2D_CONTEXT_CLEANUP *psCleanup;
@@ -987,7 +1010,7 @@ PVRSRV_ERROR SGXUnregisterHW2DContextKM(IMG_HANDLE hHW2DContext)
987 1010
988 psCleanup = (SGX_HW_2D_CONTEXT_CLEANUP *)hHW2DContext; 1011 psCleanup = (SGX_HW_2D_CONTEXT_CLEANUP *)hHW2DContext;
989 1012
990 eError = ResManFreeResByPtr(psCleanup->psResItem); 1013 eError = ResManFreeResByPtr(psCleanup->psResItem, bForceCleanup);
991 1014
992 return eError; 1015 return eError;
993} 1016}
@@ -1076,13 +1099,16 @@ PVRSRV_ERROR SGX2DQueryBlitsCompleteKM(PVRSRV_SGXDEV_INFO *psDevInfo,
1076 1099
1077 1100
1078IMG_EXPORT 1101IMG_EXPORT
1079IMG_VOID SGXFlushHWRenderTargetKM(IMG_HANDLE psDeviceNode, IMG_DEV_VIRTADDR sHWRTDataSetDevVAddr) 1102PVRSRV_ERROR SGXFlushHWRenderTargetKM(IMG_HANDLE psDeviceNode,
1103 IMG_DEV_VIRTADDR sHWRTDataSetDevVAddr,
1104 IMG_BOOL bForceCleanup)
1080{ 1105{
1081 PVR_ASSERT(sHWRTDataSetDevVAddr.uiAddr != IMG_NULL); 1106 PVR_ASSERT(sHWRTDataSetDevVAddr.uiAddr != IMG_NULL);
1082 1107
1083 SGXCleanupRequest(psDeviceNode, 1108 return SGXCleanupRequest(psDeviceNode,
1084 &sHWRTDataSetDevVAddr, 1109 &sHWRTDataSetDevVAddr,
1085 PVRSRV_CLEANUPCMD_RT); 1110 PVRSRV_CLEANUPCMD_RT,
1111 bForceCleanup);
1086} 1112}
1087 1113
1088 1114
@@ -1141,7 +1167,7 @@ PVRSRV_ERROR SGXContextSuspend(PVRSRV_DEVICE_NODE *psDeviceNode,
1141 PVR_DPF((PVR_DBG_ERROR,"SGXContextSuspend: Failed to submit context suspend command")); 1167 PVR_DPF((PVR_DBG_ERROR,"SGXContextSuspend: Failed to submit context suspend command"));
1142 return eError; 1168 return eError;
1143 } 1169 }
1144 1170
1145 return eError; 1171 return eError;
1146} 1172}
1147 1173
diff --git a/drivers/gpu/pvr/sgx/sgxutils.h b/drivers/gpu/pvr/sgx/sgxutils.h
index a7cbcb7193a..bc60fdd9186 100644
--- a/drivers/gpu/pvr/sgx/sgxutils.h
+++ b/drivers/gpu/pvr/sgx/sgxutils.h
@@ -75,13 +75,15 @@ IMG_HANDLE SGXRegisterHWTransferContextKM(IMG_HANDLE psDeviceNode,
75 PVRSRV_PER_PROCESS_DATA *psPerProc); 75 PVRSRV_PER_PROCESS_DATA *psPerProc);
76 76
77IMG_IMPORT 77IMG_IMPORT
78IMG_VOID SGXFlushHWRenderTargetKM(IMG_HANDLE psSGXDevInfo, IMG_DEV_VIRTADDR psHWRTDataSetDevVAddr); 78PVRSRV_ERROR SGXFlushHWRenderTargetKM(IMG_HANDLE psSGXDevInfo,
79 IMG_DEV_VIRTADDR psHWRTDataSetDevVAddr,
80 IMG_BOOL bForceCleanup);
79 81
80IMG_IMPORT 82IMG_IMPORT
81PVRSRV_ERROR SGXUnregisterHWRenderContextKM(IMG_HANDLE hHWRenderContext); 83PVRSRV_ERROR SGXUnregisterHWRenderContextKM(IMG_HANDLE hHWRenderContext, IMG_BOOL bForceCleanup);
82 84
83IMG_IMPORT 85IMG_IMPORT
84PVRSRV_ERROR SGXUnregisterHWTransferContextKM(IMG_HANDLE hHWTransferContext); 86PVRSRV_ERROR SGXUnregisterHWTransferContextKM(IMG_HANDLE hHWTransferContext, IMG_BOOL bForceCleanup);
85 87
86#if defined(SGX_FEATURE_2D_HARDWARE) 88#if defined(SGX_FEATURE_2D_HARDWARE)
87IMG_IMPORT 89IMG_IMPORT
@@ -90,16 +92,17 @@ IMG_HANDLE SGXRegisterHW2DContextKM(IMG_HANDLE psDeviceNode,
90 PVRSRV_PER_PROCESS_DATA *psPerProc); 92 PVRSRV_PER_PROCESS_DATA *psPerProc);
91 93
92IMG_IMPORT 94IMG_IMPORT
93PVRSRV_ERROR SGXUnregisterHW2DContextKM(IMG_HANDLE hHW2DContext); 95PVRSRV_ERROR SGXUnregisterHW2DContextKM(IMG_HANDLE hHW2DContext, IMG_BOOL bForceCleanup);
94#endif 96#endif
95 97
96IMG_UINT32 SGXConvertTimeStamp(PVRSRV_SGXDEV_INFO *psDevInfo, 98IMG_UINT32 SGXConvertTimeStamp(PVRSRV_SGXDEV_INFO *psDevInfo,
97 IMG_UINT32 ui32TimeWraps, 99 IMG_UINT32 ui32TimeWraps,
98 IMG_UINT32 ui32Time); 100 IMG_UINT32 ui32Time);
99 101
100IMG_VOID SGXCleanupRequest(PVRSRV_DEVICE_NODE *psDeviceNode, 102PVRSRV_ERROR SGXCleanupRequest(PVRSRV_DEVICE_NODE *psDeviceNode,
101 IMG_DEV_VIRTADDR *psHWDataDevVAddr, 103 IMG_DEV_VIRTADDR *psHWDataDevVAddr,
102 IMG_UINT32 ui32CleanupType); 104 IMG_UINT32 ui32CleanupType,
105 IMG_BOOL bForceCleanup);
103 106
104IMG_IMPORT 107IMG_IMPORT
105PVRSRV_ERROR PVRSRVGetSGXRevDataKM(PVRSRV_DEVICE_NODE* psDeviceNode, IMG_UINT32 *pui32SGXCoreRev, 108PVRSRV_ERROR PVRSRVGetSGXRevDataKM(PVRSRV_DEVICE_NODE* psDeviceNode, IMG_UINT32 *pui32SGXCoreRev,
diff --git a/drivers/gpu/pvr/sgx535defs.h b/drivers/gpu/pvr/sgx520defs.h
index 66f216668a0..a21295d0c64 100644
--- a/drivers/gpu/pvr/sgx535defs.h
+++ b/drivers/gpu/pvr/sgx520defs.h
@@ -24,12 +24,10 @@
24 * 24 *
25 ******************************************************************************/ 25 ******************************************************************************/
26 26
27#ifndef _SGX535DEFS_KM_H_ 27#ifndef _SGX520DEFS_KM_H_
28#define _SGX535DEFS_KM_H_ 28#define _SGX520DEFS_KM_H_
29 29
30#define EUR_CR_CLKGATECTL 0x0000 30#define EUR_CR_CLKGATECTL 0x0000
31#define EUR_CR_CLKGATECTL_2D_CLKG_MASK 0x00000003U
32#define EUR_CR_CLKGATECTL_2D_CLKG_SHIFT 0
33#define EUR_CR_CLKGATECTL_ISP_CLKG_MASK 0x00000030U 31#define EUR_CR_CLKGATECTL_ISP_CLKG_MASK 0x00000030U
34#define EUR_CR_CLKGATECTL_ISP_CLKG_SHIFT 4 32#define EUR_CR_CLKGATECTL_ISP_CLKG_SHIFT 4
35#define EUR_CR_CLKGATECTL_TSP_CLKG_MASK 0x00000300U 33#define EUR_CR_CLKGATECTL_TSP_CLKG_MASK 0x00000300U
@@ -43,8 +41,6 @@
43#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_MASK 0x01000000U 41#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_MASK 0x01000000U
44#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_SHIFT 24 42#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_SHIFT 24
45#define EUR_CR_CLKGATESTATUS 0x0004 43#define EUR_CR_CLKGATESTATUS 0x0004
46#define EUR_CR_CLKGATESTATUS_2D_CLKS_MASK 0x00000001
47#define EUR_CR_CLKGATESTATUS_2D_CLKS_SHIFT 0
48#define EUR_CR_CLKGATESTATUS_ISP_CLKS_MASK 0x00000010U 44#define EUR_CR_CLKGATESTATUS_ISP_CLKS_MASK 0x00000010U
49#define EUR_CR_CLKGATESTATUS_ISP_CLKS_SHIFT 4 45#define EUR_CR_CLKGATESTATUS_ISP_CLKS_SHIFT 4
50#define EUR_CR_CLKGATESTATUS_TSP_CLKS_MASK 0x00000100U 46#define EUR_CR_CLKGATESTATUS_TSP_CLKS_MASK 0x00000100U
@@ -56,8 +52,6 @@
56#define EUR_CR_CLKGATESTATUS_USE_CLKS_MASK 0x00100000U 52#define EUR_CR_CLKGATESTATUS_USE_CLKS_MASK 0x00100000U
57#define EUR_CR_CLKGATESTATUS_USE_CLKS_SHIFT 20 53#define EUR_CR_CLKGATESTATUS_USE_CLKS_SHIFT 20
58#define EUR_CR_CLKGATECTLOVR 0x0008 54#define EUR_CR_CLKGATECTLOVR 0x0008
59#define EUR_CR_CLKGATECTLOVR_2D_CLKO_MASK 0x00000003U
60#define EUR_CR_CLKGATECTLOVR_2D_CLKO_SHIFT 0
61#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_MASK 0x00000030U 55#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_MASK 0x00000030U
62#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_SHIFT 4 56#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_SHIFT 4
63#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_MASK 0x00000300U 57#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_MASK 0x00000300U
@@ -91,8 +85,6 @@
91#define EUR_CR_SOFT_RESET 0x0080 85#define EUR_CR_SOFT_RESET 0x0080
92#define EUR_CR_SOFT_RESET_BIF_RESET_MASK 0x00000001U 86#define EUR_CR_SOFT_RESET_BIF_RESET_MASK 0x00000001U
93#define EUR_CR_SOFT_RESET_BIF_RESET_SHIFT 0 87#define EUR_CR_SOFT_RESET_BIF_RESET_SHIFT 0
94#define EUR_CR_SOFT_RESET_TWOD_RESET_MASK 0x00000002U
95#define EUR_CR_SOFT_RESET_TWOD_RESET_SHIFT 1
96#define EUR_CR_SOFT_RESET_DPM_RESET_MASK 0x00000004U 88#define EUR_CR_SOFT_RESET_DPM_RESET_MASK 0x00000004U
97#define EUR_CR_SOFT_RESET_DPM_RESET_SHIFT 2 89#define EUR_CR_SOFT_RESET_DPM_RESET_SHIFT 2
98#define EUR_CR_SOFT_RESET_TA_RESET_MASK 0x00000008U 90#define EUR_CR_SOFT_RESET_TA_RESET_MASK 0x00000008U
@@ -104,65 +96,45 @@
104#define EUR_CR_SOFT_RESET_TSP_RESET_MASK 0x00000040U 96#define EUR_CR_SOFT_RESET_TSP_RESET_MASK 0x00000040U
105#define EUR_CR_SOFT_RESET_TSP_RESET_SHIFT 6 97#define EUR_CR_SOFT_RESET_TSP_RESET_SHIFT 6
106#define EUR_CR_EVENT_HOST_ENABLE2 0x0110 98#define EUR_CR_EVENT_HOST_ENABLE2 0x0110
107#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_MASK 0x00000080U 99#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_MASK 0x00000010U
108#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_SHIFT 7 100#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_SHIFT 4
109#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_MASK 0x00000040U 101#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_MASK 0x00000008U
110#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_SHIFT 6 102#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_SHIFT 3
111#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_MASK 0x00000020U 103#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_MASK 0x00000004U
112#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_SHIFT 5 104#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_SHIFT 2
113#define EUR_CR_EVENT_HOST_ENABLE2_BIF_REQUESTER_FAULT_MASK 0x00000010U
114#define EUR_CR_EVENT_HOST_ENABLE2_BIF_REQUESTER_FAULT_SHIFT 4
115#define EUR_CR_EVENT_HOST_ENABLE2_DPM_DHOST_FREE_LOAD_MASK 0x00000008U
116#define EUR_CR_EVENT_HOST_ENABLE2_DPM_DHOST_FREE_LOAD_SHIFT 3
117#define EUR_CR_EVENT_HOST_ENABLE2_DPM_HOST_FREE_LOAD_MASK 0x00000004U
118#define EUR_CR_EVENT_HOST_ENABLE2_DPM_HOST_FREE_LOAD_SHIFT 2
119#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_MASK 0x00000002U 105#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_MASK 0x00000002U
120#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_SHIFT 1 106#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_SHIFT 1
121#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_MASK 0x00000001U 107#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_MASK 0x00000001U
122#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_SHIFT 0 108#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_SHIFT 0
123#define EUR_CR_EVENT_HOST_CLEAR2 0x0114 109#define EUR_CR_EVENT_HOST_CLEAR2 0x0114
124#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_MASK 0x00000080U 110#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_MASK 0x00000010U
125#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_SHIFT 7 111#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_SHIFT 4
126#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_MASK 0x00000040U 112#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_MASK 0x00000008U
127#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_SHIFT 6 113#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_SHIFT 3
128#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_MASK 0x00000020U 114#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_MASK 0x00000004U
129#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_SHIFT 5 115#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_SHIFT 2
130#define EUR_CR_EVENT_HOST_CLEAR2_BIF_REQUESTER_FAULT_MASK 0x00000010U
131#define EUR_CR_EVENT_HOST_CLEAR2_BIF_REQUESTER_FAULT_SHIFT 4
132#define EUR_CR_EVENT_HOST_CLEAR2_DPM_DHOST_FREE_LOAD_MASK 0x00000008U
133#define EUR_CR_EVENT_HOST_CLEAR2_DPM_DHOST_FREE_LOAD_SHIFT 3
134#define EUR_CR_EVENT_HOST_CLEAR2_DPM_HOST_FREE_LOAD_MASK 0x00000004U
135#define EUR_CR_EVENT_HOST_CLEAR2_DPM_HOST_FREE_LOAD_SHIFT 2
136#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_MASK 0x00000002U 116#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_MASK 0x00000002U
137#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_SHIFT 1 117#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_SHIFT 1
138#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_MASK 0x00000001U 118#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_MASK 0x00000001U
139#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_SHIFT 0 119#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_SHIFT 0
140#define EUR_CR_EVENT_STATUS2 0x0118U 120#define EUR_CR_EVENT_STATUS2 0x0118
141#define EUR_CR_EVENT_STATUS2_TRIG_TA_MASK 0x00000080U 121#define EUR_CR_EVENT_STATUS2_TRIG_TA_MASK 0x00000010U
142#define EUR_CR_EVENT_STATUS2_TRIG_TA_SHIFT 7 122#define EUR_CR_EVENT_STATUS2_TRIG_TA_SHIFT 4
143#define EUR_CR_EVENT_STATUS2_TRIG_3D_MASK 0x00000040U 123#define EUR_CR_EVENT_STATUS2_TRIG_3D_MASK 0x00000008U
144#define EUR_CR_EVENT_STATUS2_TRIG_3D_SHIFT 6 124#define EUR_CR_EVENT_STATUS2_TRIG_3D_SHIFT 3
145#define EUR_CR_EVENT_STATUS2_TRIG_DL_MASK 0x00000020U 125#define EUR_CR_EVENT_STATUS2_TRIG_DL_MASK 0x00000004U
146#define EUR_CR_EVENT_STATUS2_TRIG_DL_SHIFT 5 126#define EUR_CR_EVENT_STATUS2_TRIG_DL_SHIFT 2
147#define EUR_CR_EVENT_STATUS2_BIF_REQUESTER_FAULT_MASK 0x00000010U
148#define EUR_CR_EVENT_STATUS2_BIF_REQUESTER_FAULT_SHIFT 4
149#define EUR_CR_EVENT_STATUS2_DPM_DHOST_FREE_LOAD_MASK 0x00000008U
150#define EUR_CR_EVENT_STATUS2_DPM_DHOST_FREE_LOAD_SHIFT 3
151#define EUR_CR_EVENT_STATUS2_DPM_HOST_FREE_LOAD_MASK 0x00000004U
152#define EUR_CR_EVENT_STATUS2_DPM_HOST_FREE_LOAD_SHIFT 2
153#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_MASK 0x00000002U 127#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_MASK 0x00000002U
154#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_SHIFT 1 128#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_SHIFT 1
155#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_MASK 0x00000001U 129#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_MASK 0x00000001U
156#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_SHIFT 0 130#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_SHIFT 0
157#define EUR_CR_EVENT_STATUS 0x012CU 131#define EUR_CR_EVENT_STATUS 0x012C
158#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_MASK 0x80000000U 132#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_MASK 0x80000000U
159#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_SHIFT 31 133#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_SHIFT 31
160#define EUR_CR_EVENT_STATUS_TIMER_MASK 0x20000000U 134#define EUR_CR_EVENT_STATUS_TIMER_MASK 0x20000000U
161#define EUR_CR_EVENT_STATUS_TIMER_SHIFT 29 135#define EUR_CR_EVENT_STATUS_TIMER_SHIFT 29
162#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_MASK 0x10000000U 136#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_MASK 0x10000000U
163#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_SHIFT 28 137#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_SHIFT 28
164#define EUR_CR_EVENT_STATUS_TWOD_COMPLETE_MASK 0x08000000U
165#define EUR_CR_EVENT_STATUS_TWOD_COMPLETE_SHIFT 27
166#define EUR_CR_EVENT_STATUS_MADD_CACHE_INVALCOMPLETE_MASK 0x04000000U 138#define EUR_CR_EVENT_STATUS_MADD_CACHE_INVALCOMPLETE_MASK 0x04000000U
167#define EUR_CR_EVENT_STATUS_MADD_CACHE_INVALCOMPLETE_SHIFT 26 139#define EUR_CR_EVENT_STATUS_MADD_CACHE_INVALCOMPLETE_SHIFT 26
168#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U 140#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U
@@ -224,8 +196,6 @@
224#define EUR_CR_EVENT_HOST_ENABLE_TIMER_SHIFT 29 196#define EUR_CR_EVENT_HOST_ENABLE_TIMER_SHIFT 29
225#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_MASK 0x10000000U 197#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_MASK 0x10000000U
226#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_SHIFT 28 198#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_SHIFT 28
227#define EUR_CR_EVENT_HOST_ENABLE_TWOD_COMPLETE_MASK 0x08000000U
228#define EUR_CR_EVENT_HOST_ENABLE_TWOD_COMPLETE_SHIFT 27
229#define EUR_CR_EVENT_HOST_ENABLE_MADD_CACHE_INVALCOMPLETE_MASK 0x04000000U 199#define EUR_CR_EVENT_HOST_ENABLE_MADD_CACHE_INVALCOMPLETE_MASK 0x04000000U
230#define EUR_CR_EVENT_HOST_ENABLE_MADD_CACHE_INVALCOMPLETE_SHIFT 26 200#define EUR_CR_EVENT_HOST_ENABLE_MADD_CACHE_INVALCOMPLETE_SHIFT 26
231#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U 201#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U
@@ -287,8 +257,6 @@
287#define EUR_CR_EVENT_HOST_CLEAR_TIMER_SHIFT 29 257#define EUR_CR_EVENT_HOST_CLEAR_TIMER_SHIFT 29
288#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_MASK 0x10000000U 258#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_MASK 0x10000000U
289#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_SHIFT 28 259#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_SHIFT 28
290#define EUR_CR_EVENT_HOST_CLEAR_TWOD_COMPLETE_MASK 0x08000000U
291#define EUR_CR_EVENT_HOST_CLEAR_TWOD_COMPLETE_SHIFT 27
292#define EUR_CR_EVENT_HOST_CLEAR_MADD_CACHE_INVALCOMPLETE_MASK 0x04000000U 260#define EUR_CR_EVENT_HOST_CLEAR_MADD_CACHE_INVALCOMPLETE_MASK 0x04000000U
293#define EUR_CR_EVENT_HOST_CLEAR_MADD_CACHE_INVALCOMPLETE_SHIFT 26 261#define EUR_CR_EVENT_HOST_CLEAR_MADD_CACHE_INVALCOMPLETE_SHIFT 26
294#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U 262#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U
@@ -343,11 +311,94 @@
343#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_SHIFT 1 311#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_SHIFT 1
344#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_MASK 0x00000001U 312#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_MASK 0x00000001U
345#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_SHIFT 0 313#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_SHIFT 0
314#define EUR_CR_TIMER 0x0144
315#define EUR_CR_TIMER_VALUE_MASK 0xFFFFFFFFU
316#define EUR_CR_TIMER_VALUE_SHIFT 0
317#define EUR_CR_USE_CODE_BASE_0 0x0A0C
318#define EUR_CR_USE_CODE_BASE_ADDR_00_MASK 0x000FFFFFU
319#define EUR_CR_USE_CODE_BASE_ADDR_00_SHIFT 0
320#define EUR_CR_USE_CODE_BASE_DM_00_MASK 0x00300000U
321#define EUR_CR_USE_CODE_BASE_DM_00_SHIFT 20
322#define EUR_CR_USE_CODE_BASE_1 0x0A10
323#define EUR_CR_USE_CODE_BASE_ADDR_01_MASK 0x000FFFFFU
324#define EUR_CR_USE_CODE_BASE_ADDR_01_SHIFT 0
325#define EUR_CR_USE_CODE_BASE_DM_01_MASK 0x00300000U
326#define EUR_CR_USE_CODE_BASE_DM_01_SHIFT 20
327#define EUR_CR_USE_CODE_BASE_2 0x0A14
328#define EUR_CR_USE_CODE_BASE_ADDR_02_MASK 0x000FFFFFU
329#define EUR_CR_USE_CODE_BASE_ADDR_02_SHIFT 0
330#define EUR_CR_USE_CODE_BASE_DM_02_MASK 0x00300000U
331#define EUR_CR_USE_CODE_BASE_DM_02_SHIFT 20
332#define EUR_CR_USE_CODE_BASE_3 0x0A18
333#define EUR_CR_USE_CODE_BASE_ADDR_03_MASK 0x000FFFFFU
334#define EUR_CR_USE_CODE_BASE_ADDR_03_SHIFT 0
335#define EUR_CR_USE_CODE_BASE_DM_03_MASK 0x00300000U
336#define EUR_CR_USE_CODE_BASE_DM_03_SHIFT 20
337#define EUR_CR_USE_CODE_BASE_4 0x0A1C
338#define EUR_CR_USE_CODE_BASE_ADDR_04_MASK 0x000FFFFFU
339#define EUR_CR_USE_CODE_BASE_ADDR_04_SHIFT 0
340#define EUR_CR_USE_CODE_BASE_DM_04_MASK 0x00300000U
341#define EUR_CR_USE_CODE_BASE_DM_04_SHIFT 20
342#define EUR_CR_USE_CODE_BASE_5 0x0A20
343#define EUR_CR_USE_CODE_BASE_ADDR_05_MASK 0x000FFFFFU
344#define EUR_CR_USE_CODE_BASE_ADDR_05_SHIFT 0
345#define EUR_CR_USE_CODE_BASE_DM_05_MASK 0x00300000U
346#define EUR_CR_USE_CODE_BASE_DM_05_SHIFT 20
347#define EUR_CR_USE_CODE_BASE_6 0x0A24
348#define EUR_CR_USE_CODE_BASE_ADDR_06_MASK 0x000FFFFFU
349#define EUR_CR_USE_CODE_BASE_ADDR_06_SHIFT 0
350#define EUR_CR_USE_CODE_BASE_DM_06_MASK 0x00300000U
351#define EUR_CR_USE_CODE_BASE_DM_06_SHIFT 20
352#define EUR_CR_USE_CODE_BASE_7 0x0A28
353#define EUR_CR_USE_CODE_BASE_ADDR_07_MASK 0x000FFFFFU
354#define EUR_CR_USE_CODE_BASE_ADDR_07_SHIFT 0
355#define EUR_CR_USE_CODE_BASE_DM_07_MASK 0x00300000U
356#define EUR_CR_USE_CODE_BASE_DM_07_SHIFT 20
357#define EUR_CR_USE_CODE_BASE_8 0x0A2C
358#define EUR_CR_USE_CODE_BASE_ADDR_08_MASK 0x000FFFFFU
359#define EUR_CR_USE_CODE_BASE_ADDR_08_SHIFT 0
360#define EUR_CR_USE_CODE_BASE_DM_08_MASK 0x00300000U
361#define EUR_CR_USE_CODE_BASE_DM_08_SHIFT 20
362#define EUR_CR_USE_CODE_BASE_9 0x0A30
363#define EUR_CR_USE_CODE_BASE_ADDR_09_MASK 0x000FFFFFU
364#define EUR_CR_USE_CODE_BASE_ADDR_09_SHIFT 0
365#define EUR_CR_USE_CODE_BASE_DM_09_MASK 0x00300000U
366#define EUR_CR_USE_CODE_BASE_DM_09_SHIFT 20
367#define EUR_CR_USE_CODE_BASE_10 0x0A34
368#define EUR_CR_USE_CODE_BASE_ADDR_10_MASK 0x000FFFFFU
369#define EUR_CR_USE_CODE_BASE_ADDR_10_SHIFT 0
370#define EUR_CR_USE_CODE_BASE_DM_10_MASK 0x00300000U
371#define EUR_CR_USE_CODE_BASE_DM_10_SHIFT 20
372#define EUR_CR_USE_CODE_BASE_11 0x0A38
373#define EUR_CR_USE_CODE_BASE_ADDR_11_MASK 0x000FFFFFU
374#define EUR_CR_USE_CODE_BASE_ADDR_11_SHIFT 0
375#define EUR_CR_USE_CODE_BASE_DM_11_MASK 0x00300000U
376#define EUR_CR_USE_CODE_BASE_DM_11_SHIFT 20
377#define EUR_CR_USE_CODE_BASE_12 0x0A3C
378#define EUR_CR_USE_CODE_BASE_ADDR_12_MASK 0x000FFFFFU
379#define EUR_CR_USE_CODE_BASE_ADDR_12_SHIFT 0
380#define EUR_CR_USE_CODE_BASE_DM_12_MASK 0x00300000U
381#define EUR_CR_USE_CODE_BASE_DM_12_SHIFT 20
382#define EUR_CR_USE_CODE_BASE_13 0x0A40
383#define EUR_CR_USE_CODE_BASE_ADDR_13_MASK 0x000FFFFFU
384#define EUR_CR_USE_CODE_BASE_ADDR_13_SHIFT 0
385#define EUR_CR_USE_CODE_BASE_DM_13_MASK 0x00300000U
386#define EUR_CR_USE_CODE_BASE_DM_13_SHIFT 20
387#define EUR_CR_USE_CODE_BASE_14 0x0A44
388#define EUR_CR_USE_CODE_BASE_ADDR_14_MASK 0x000FFFFFU
389#define EUR_CR_USE_CODE_BASE_ADDR_14_SHIFT 0
390#define EUR_CR_USE_CODE_BASE_DM_14_MASK 0x00300000U
391#define EUR_CR_USE_CODE_BASE_DM_14_SHIFT 20
392#define EUR_CR_USE_CODE_BASE_15 0x0A48
393#define EUR_CR_USE_CODE_BASE_ADDR_15_MASK 0x000FFFFFU
394#define EUR_CR_USE_CODE_BASE_ADDR_15_SHIFT 0
395#define EUR_CR_USE_CODE_BASE_DM_15_MASK 0x00300000U
396#define EUR_CR_USE_CODE_BASE_DM_15_SHIFT 20
346#define EUR_CR_PDS_EXEC_BASE 0x0AB8 397#define EUR_CR_PDS_EXEC_BASE 0x0AB8
347#define EUR_CR_PDS_EXEC_BASE_ADDR_MASK 0xFFF00000U 398#define EUR_CR_PDS_EXEC_BASE_ADDR_MASK 0x0FF00000U
348#define EUR_CR_PDS_EXEC_BASE_ADDR_SHIFT 20 399#define EUR_CR_PDS_EXEC_BASE_ADDR_SHIFT 20
349#define EUR_CR_EVENT_KICKER 0x0AC4 400#define EUR_CR_EVENT_KICKER 0x0AC4
350#define EUR_CR_EVENT_KICKER_ADDRESS_MASK 0xFFFFFFF0U 401#define EUR_CR_EVENT_KICKER_ADDRESS_MASK 0x0FFFFFF0U
351#define EUR_CR_EVENT_KICKER_ADDRESS_SHIFT 4 402#define EUR_CR_EVENT_KICKER_ADDRESS_SHIFT 4
352#define EUR_CR_EVENT_KICK 0x0AC8 403#define EUR_CR_EVENT_KICK 0x0AC8
353#define EUR_CR_EVENT_KICK_NOW_MASK 0x00000001U 404#define EUR_CR_EVENT_KICK_NOW_MASK 0x00000001U
@@ -392,8 +443,6 @@
392#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_SHIFT 9 443#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_SHIFT 9
393#define EUR_CR_BIF_CTRL_MMU_BYPASS_TE_MASK 0x00000400U 444#define EUR_CR_BIF_CTRL_MMU_BYPASS_TE_MASK 0x00000400U
394#define EUR_CR_BIF_CTRL_MMU_BYPASS_TE_SHIFT 10 445#define EUR_CR_BIF_CTRL_MMU_BYPASS_TE_SHIFT 10
395#define EUR_CR_BIF_CTRL_MMU_BYPASS_TWOD_MASK 0x00000800U
396#define EUR_CR_BIF_CTRL_MMU_BYPASS_TWOD_SHIFT 11
397#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_MASK 0x00001000U 446#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_MASK 0x00001000U
398#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_SHIFT 12 447#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_SHIFT 12
399#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_MASK 0x00002000U 448#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_MASK 0x00002000U
@@ -402,8 +451,6 @@
402#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_SHIFT 14 451#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_SHIFT 14
403#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_MASK 0x00008000U 452#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_MASK 0x00008000U
404#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_SHIFT 15 453#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_SHIFT 15
405#define EUR_CR_BIF_CTRL_MMU_BYPASS_HOST_MASK 0x00010000U
406#define EUR_CR_BIF_CTRL_MMU_BYPASS_HOST_SHIFT 16
407#define EUR_CR_BIF_INT_STAT 0x0C04 454#define EUR_CR_BIF_INT_STAT 0x0C04
408#define EUR_CR_BIF_INT_STAT_FAULT_MASK 0x00003FFFU 455#define EUR_CR_BIF_INT_STAT_FAULT_MASK 0x00003FFFU
409#define EUR_CR_BIF_INT_STAT_FAULT_SHIFT 0 456#define EUR_CR_BIF_INT_STAT_FAULT_SHIFT 0
@@ -412,237 +459,28 @@
412#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_MASK 0x00008000U 459#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_MASK 0x00008000U
413#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_SHIFT 15 460#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_SHIFT 15
414#define EUR_CR_BIF_FAULT 0x0C08 461#define EUR_CR_BIF_FAULT 0x0C08
415#define EUR_CR_BIF_FAULT_ADDR_MASK 0xFFFFF000U 462#define EUR_CR_BIF_FAULT_ADDR_MASK 0x0FFFF000U
416#define EUR_CR_BIF_FAULT_ADDR_SHIFT 12 463#define EUR_CR_BIF_FAULT_ADDR_SHIFT 12
417#define EUR_CR_BIF_TILE0 0x0C0C
418#define EUR_CR_BIF_TILE0_MIN_ADDRESS_MASK 0x00000FFFU
419#define EUR_CR_BIF_TILE0_MIN_ADDRESS_SHIFT 0
420#define EUR_CR_BIF_TILE0_MAX_ADDRESS_MASK 0x00FFF000U
421#define EUR_CR_BIF_TILE0_MAX_ADDRESS_SHIFT 12
422#define EUR_CR_BIF_TILE0_CFG_MASK 0x0F000000U
423#define EUR_CR_BIF_TILE0_CFG_SHIFT 24
424#define EUR_CR_BIF_TILE1 0x0C10
425#define EUR_CR_BIF_TILE1_MIN_ADDRESS_MASK 0x00000FFFU
426#define EUR_CR_BIF_TILE1_MIN_ADDRESS_SHIFT 0
427#define EUR_CR_BIF_TILE1_MAX_ADDRESS_MASK 0x00FFF000U
428#define EUR_CR_BIF_TILE1_MAX_ADDRESS_SHIFT 12
429#define EUR_CR_BIF_TILE1_CFG_MASK 0x0F000000U
430#define EUR_CR_BIF_TILE1_CFG_SHIFT 24
431#define EUR_CR_BIF_TILE2 0x0C14
432#define EUR_CR_BIF_TILE2_MIN_ADDRESS_MASK 0x00000FFFU
433#define EUR_CR_BIF_TILE2_MIN_ADDRESS_SHIFT 0
434#define EUR_CR_BIF_TILE2_MAX_ADDRESS_MASK 0x00FFF000U
435#define EUR_CR_BIF_TILE2_MAX_ADDRESS_SHIFT 12
436#define EUR_CR_BIF_TILE2_CFG_MASK 0x0F000000U
437#define EUR_CR_BIF_TILE2_CFG_SHIFT 24
438#define EUR_CR_BIF_TILE3 0x0C18
439#define EUR_CR_BIF_TILE3_MIN_ADDRESS_MASK 0x00000FFFU
440#define EUR_CR_BIF_TILE3_MIN_ADDRESS_SHIFT 0
441#define EUR_CR_BIF_TILE3_MAX_ADDRESS_MASK 0x00FFF000U
442#define EUR_CR_BIF_TILE3_MAX_ADDRESS_SHIFT 12
443#define EUR_CR_BIF_TILE3_CFG_MASK 0x0F000000U
444#define EUR_CR_BIF_TILE3_CFG_SHIFT 24
445#define EUR_CR_BIF_TILE4 0x0C1C
446#define EUR_CR_BIF_TILE4_MIN_ADDRESS_MASK 0x00000FFFU
447#define EUR_CR_BIF_TILE4_MIN_ADDRESS_SHIFT 0
448#define EUR_CR_BIF_TILE4_MAX_ADDRESS_MASK 0x00FFF000U
449#define EUR_CR_BIF_TILE4_MAX_ADDRESS_SHIFT 12
450#define EUR_CR_BIF_TILE4_CFG_MASK 0x0F000000U
451#define EUR_CR_BIF_TILE4_CFG_SHIFT 24
452#define EUR_CR_BIF_TILE5 0x0C20
453#define EUR_CR_BIF_TILE5_MIN_ADDRESS_MASK 0x00000FFFU
454#define EUR_CR_BIF_TILE5_MIN_ADDRESS_SHIFT 0
455#define EUR_CR_BIF_TILE5_MAX_ADDRESS_MASK 0x00FFF000U
456#define EUR_CR_BIF_TILE5_MAX_ADDRESS_SHIFT 12
457#define EUR_CR_BIF_TILE5_CFG_MASK 0x0F000000U
458#define EUR_CR_BIF_TILE5_CFG_SHIFT 24
459#define EUR_CR_BIF_TILE6 0x0C24
460#define EUR_CR_BIF_TILE6_MIN_ADDRESS_MASK 0x00000FFFU
461#define EUR_CR_BIF_TILE6_MIN_ADDRESS_SHIFT 0
462#define EUR_CR_BIF_TILE6_MAX_ADDRESS_MASK 0x00FFF000U
463#define EUR_CR_BIF_TILE6_MAX_ADDRESS_SHIFT 12
464#define EUR_CR_BIF_TILE6_CFG_MASK 0x0F000000U
465#define EUR_CR_BIF_TILE6_CFG_SHIFT 24
466#define EUR_CR_BIF_TILE7 0x0C28
467#define EUR_CR_BIF_TILE7_MIN_ADDRESS_MASK 0x00000FFFU
468#define EUR_CR_BIF_TILE7_MIN_ADDRESS_SHIFT 0
469#define EUR_CR_BIF_TILE7_MAX_ADDRESS_MASK 0x00FFF000U
470#define EUR_CR_BIF_TILE7_MAX_ADDRESS_SHIFT 12
471#define EUR_CR_BIF_TILE7_CFG_MASK 0x0F000000U
472#define EUR_CR_BIF_TILE7_CFG_SHIFT 24
473#define EUR_CR_BIF_TILE8 0x0C2C
474#define EUR_CR_BIF_TILE8_MIN_ADDRESS_MASK 0x00000FFFU
475#define EUR_CR_BIF_TILE8_MIN_ADDRESS_SHIFT 0
476#define EUR_CR_BIF_TILE8_MAX_ADDRESS_MASK 0x00FFF000U
477#define EUR_CR_BIF_TILE8_MAX_ADDRESS_SHIFT 12
478#define EUR_CR_BIF_TILE8_CFG_MASK 0x0F000000U
479#define EUR_CR_BIF_TILE8_CFG_SHIFT 24
480#define EUR_CR_BIF_TILE9 0x0C30
481#define EUR_CR_BIF_TILE9_MIN_ADDRESS_MASK 0x00000FFFU
482#define EUR_CR_BIF_TILE9_MIN_ADDRESS_SHIFT 0
483#define EUR_CR_BIF_TILE9_MAX_ADDRESS_MASK 0x00FFF000U
484#define EUR_CR_BIF_TILE9_MAX_ADDRESS_SHIFT 12
485#define EUR_CR_BIF_TILE9_CFG_MASK 0x0F000000U
486#define EUR_CR_BIF_TILE9_CFG_SHIFT 24
487#define EUR_CR_BIF_DIR_LIST_BASE1 0x0C38
488#define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_MASK 0xFFFFF000U
489#define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_SHIFT 12
490#define EUR_CR_BIF_DIR_LIST_BASE2 0x0C3C
491#define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_MASK 0xFFFFF000U
492#define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_SHIFT 12
493#define EUR_CR_BIF_DIR_LIST_BASE3 0x0C40
494#define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_MASK 0xFFFFF000U
495#define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_SHIFT 12
496#define EUR_CR_BIF_DIR_LIST_BASE4 0x0C44
497#define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_MASK 0xFFFFF000U
498#define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_SHIFT 12
499#define EUR_CR_BIF_DIR_LIST_BASE5 0x0C48
500#define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_MASK 0xFFFFF000U
501#define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_SHIFT 12
502#define EUR_CR_BIF_DIR_LIST_BASE6 0x0C4C
503#define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_MASK 0xFFFFF000U
504#define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_SHIFT 12
505#define EUR_CR_BIF_DIR_LIST_BASE7 0x0C50
506#define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_MASK 0xFFFFF000U
507#define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_SHIFT 12
508#define EUR_CR_BIF_DIR_LIST_BASE8 0x0C54
509#define EUR_CR_BIF_DIR_LIST_BASE8_ADDR_MASK 0xFFFFF000U
510#define EUR_CR_BIF_DIR_LIST_BASE8_ADDR_SHIFT 12
511#define EUR_CR_BIF_DIR_LIST_BASE9 0x0C58
512#define EUR_CR_BIF_DIR_LIST_BASE9_ADDR_MASK 0xFFFFF000U
513#define EUR_CR_BIF_DIR_LIST_BASE9_ADDR_SHIFT 12
514#define EUR_CR_BIF_DIR_LIST_BASE10 0x0C5C
515#define EUR_CR_BIF_DIR_LIST_BASE10_ADDR_MASK 0xFFFFF000U
516#define EUR_CR_BIF_DIR_LIST_BASE10_ADDR_SHIFT 12
517#define EUR_CR_BIF_DIR_LIST_BASE11 0x0C60
518#define EUR_CR_BIF_DIR_LIST_BASE11_ADDR_MASK 0xFFFFF000U
519#define EUR_CR_BIF_DIR_LIST_BASE11_ADDR_SHIFT 12
520#define EUR_CR_BIF_DIR_LIST_BASE12 0x0C64
521#define EUR_CR_BIF_DIR_LIST_BASE12_ADDR_MASK 0xFFFFF000U
522#define EUR_CR_BIF_DIR_LIST_BASE12_ADDR_SHIFT 12
523#define EUR_CR_BIF_DIR_LIST_BASE13 0x0C68
524#define EUR_CR_BIF_DIR_LIST_BASE13_ADDR_MASK 0xFFFFF000U
525#define EUR_CR_BIF_DIR_LIST_BASE13_ADDR_SHIFT 12
526#define EUR_CR_BIF_DIR_LIST_BASE14 0x0C6C
527#define EUR_CR_BIF_DIR_LIST_BASE14_ADDR_MASK 0xFFFFF000U
528#define EUR_CR_BIF_DIR_LIST_BASE14_ADDR_SHIFT 12
529#define EUR_CR_BIF_DIR_LIST_BASE15 0x0C70
530#define EUR_CR_BIF_DIR_LIST_BASE15_ADDR_MASK 0xFFFFF000U
531#define EUR_CR_BIF_DIR_LIST_BASE15_ADDR_SHIFT 12
532#define EUR_CR_BIF_BANK_SET 0x0C74
533#define EUR_CR_BIF_BANK_SET_SELECT_MASK 0x000003FFU
534#define EUR_CR_BIF_BANK_SET_SELECT_SHIFT 0
535#define EUR_CR_BIF_BANK0 0x0C78
536#define EUR_CR_BIF_BANK0_INDEX_EDM_MASK 0x0000000FU
537#define EUR_CR_BIF_BANK0_INDEX_EDM_SHIFT 0
538#define EUR_CR_BIF_BANK0_INDEX_TA_MASK 0x000000F0U
539#define EUR_CR_BIF_BANK0_INDEX_TA_SHIFT 4
540#define EUR_CR_BIF_BANK0_INDEX_HOST_MASK 0x00000F00U
541#define EUR_CR_BIF_BANK0_INDEX_HOST_SHIFT 8
542#define EUR_CR_BIF_BANK0_INDEX_3D_MASK 0x0000F000U
543#define EUR_CR_BIF_BANK0_INDEX_3D_SHIFT 12
544#define EUR_CR_BIF_BANK0_INDEX_2D_MASK 0x000F0000U
545#define EUR_CR_BIF_BANK0_INDEX_2D_SHIFT 16
546#define EUR_CR_BIF_BANK1 0x0C7C
547#define EUR_CR_BIF_BANK1_INDEX_EDM_MASK 0x0000000FU
548#define EUR_CR_BIF_BANK1_INDEX_EDM_SHIFT 0
549#define EUR_CR_BIF_BANK1_INDEX_TA_MASK 0x000000F0U
550#define EUR_CR_BIF_BANK1_INDEX_TA_SHIFT 4
551#define EUR_CR_BIF_BANK1_INDEX_HOST_MASK 0x00000F00U
552#define EUR_CR_BIF_BANK1_INDEX_HOST_SHIFT 8
553#define EUR_CR_BIF_BANK1_INDEX_3D_MASK 0x0000F000U
554#define EUR_CR_BIF_BANK1_INDEX_3D_SHIFT 12
555#define EUR_CR_BIF_BANK1_INDEX_2D_MASK 0x000F0000U
556#define EUR_CR_BIF_BANK1_INDEX_2D_SHIFT 16
557#define EUR_CR_BIF_ADT_TTE 0x0C80
558#define EUR_CR_BIF_ADT_TTE_VALUE_MASK 0x000000FFU
559#define EUR_CR_BIF_ADT_TTE_VALUE_SHIFT 0
560#define EUR_CR_BIF_DIR_LIST_BASE0 0x0C84 464#define EUR_CR_BIF_DIR_LIST_BASE0 0x0C84
561#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_MASK 0xFFFFF000U 465#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_MASK 0xFFFFF000U
562#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_SHIFT 12 466#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_SHIFT 12
563#define EUR_CR_BIF_TWOD_REQ_BASE 0x0C88
564#define EUR_CR_BIF_TWOD_REQ_BASE_ADDR_MASK 0xFFF00000U
565#define EUR_CR_BIF_TWOD_REQ_BASE_ADDR_SHIFT 20
566#define EUR_CR_BIF_TA_REQ_BASE 0x0C90 467#define EUR_CR_BIF_TA_REQ_BASE 0x0C90
567#define EUR_CR_BIF_TA_REQ_BASE_ADDR_MASK 0xFFF00000U 468#define EUR_CR_BIF_TA_REQ_BASE_ADDR_MASK 0x0FF00000U
568#define EUR_CR_BIF_TA_REQ_BASE_ADDR_SHIFT 20 469#define EUR_CR_BIF_TA_REQ_BASE_ADDR_SHIFT 20
569#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1 0x0C94
570#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_MMU_MASK 0x00000007U
571#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_MMU_SHIFT 0
572#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_CACHE_MASK 0x00000038U
573#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_CACHE_SHIFT 3
574#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_VDM_MASK 0x000001C0U
575#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_VDM_SHIFT 6
576#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_TE_MASK 0x00000E00U
577#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_TE_SHIFT 9
578#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_TWOD_MASK 0x00007000U
579#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_TWOD_SHIFT 12
580#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_PBE_MASK 0x00038000U
581#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_PBE_SHIFT 15
582#define EUR_CR_BIF_MEM_ARB_FLOWRATES_2 0x0C98
583#define EUR_CR_BIF_MEM_ARB_FLOWRATES_2_HOST_MASK 0x00000007U
584#define EUR_CR_BIF_MEM_ARB_FLOWRATES_2_HOST_SHIFT 0
585#define EUR_CR_BIF_MEM_ARB_FLOWRATES_2_USE_MASK 0x00000038U
586#define EUR_CR_BIF_MEM_ARB_FLOWRATES_2_USE_SHIFT 3
587#define EUR_CR_BIF_MEM_ARB_FLOWRATES_2_ISP_MASK 0x000001C0U
588#define EUR_CR_BIF_MEM_ARB_FLOWRATES_2_ISP_SHIFT 6
589#define EUR_CR_BIF_MEM_ARB_FLOWRATES_2_TSPP_MASK 0x00000E00U
590#define EUR_CR_BIF_MEM_ARB_FLOWRATES_2_TSPP_SHIFT 9
591#define EUR_CR_BIF_MEM_ARB_CONFIG 0x0CA0
592#define EUR_CR_BIF_MEM_ARB_CONFIG_PAGE_SIZE_MASK 0x0000000FU
593#define EUR_CR_BIF_MEM_ARB_CONFIG_PAGE_SIZE_SHIFT 0
594#define EUR_CR_BIF_MEM_ARB_CONFIG_BEST_CNT_MASK 0x00000FF0U
595#define EUR_CR_BIF_MEM_ARB_CONFIG_BEST_CNT_SHIFT 4
596#define EUR_CR_BIF_MEM_ARB_CONFIG_TTE_THRESH_MASK 0x00FFF000U
597#define EUR_CR_BIF_MEM_ARB_CONFIG_TTE_THRESH_SHIFT 12
598#define EUR_CR_BIF_MEM_REQ_STAT 0x0CA8 470#define EUR_CR_BIF_MEM_REQ_STAT 0x0CA8
599#define EUR_CR_BIF_MEM_REQ_STAT_READS_MASK 0x000000FFU 471#define EUR_CR_BIF_MEM_REQ_STAT_READS_MASK 0x000000FFU
600#define EUR_CR_BIF_MEM_REQ_STAT_READS_SHIFT 0 472#define EUR_CR_BIF_MEM_REQ_STAT_READS_SHIFT 0
601#define EUR_CR_BIF_3D_REQ_BASE 0x0CAC 473#define EUR_CR_BIF_3D_REQ_BASE 0x0CAC
602#define EUR_CR_BIF_3D_REQ_BASE_ADDR_MASK 0xFFF00000U 474#define EUR_CR_BIF_3D_REQ_BASE_ADDR_MASK 0x0FF00000U
603#define EUR_CR_BIF_3D_REQ_BASE_ADDR_SHIFT 20 475#define EUR_CR_BIF_3D_REQ_BASE_ADDR_SHIFT 20
604#define EUR_CR_BIF_ZLS_REQ_BASE 0x0CB0 476#define EUR_CR_BIF_ZLS_REQ_BASE 0x0CB0
605#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_MASK 0xFFF00000U 477#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_MASK 0x0FF00000U
606#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_SHIFT 20 478#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_SHIFT 20
607#define EUR_CR_BIF_BANK_STATUS 0x0CB4
608#define EUR_CR_BIF_BANK_STATUS_3D_CURRENT_BANK_MASK 0x00000001U
609#define EUR_CR_BIF_BANK_STATUS_3D_CURRENT_BANK_SHIFT 0
610#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_MASK 0x00000002U
611#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_SHIFT 1
612#define EUR_CR_2D_BLIT_STATUS 0x0E04
613#define EUR_CR_2D_BLIT_STATUS_COMPLETE_MASK 0x00FFFFFFU
614#define EUR_CR_2D_BLIT_STATUS_COMPLETE_SHIFT 0
615#define EUR_CR_2D_BLIT_STATUS_BUSY_MASK 0x01000000U
616#define EUR_CR_2D_BLIT_STATUS_BUSY_SHIFT 24
617#define EUR_CR_2D_VIRTUAL_FIFO_0 0x0E10
618#define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_MASK 0x00000001U
619#define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_SHIFT 0
620#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MASK 0x0000000EU
621#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_SHIFT 1
622#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_MASK 0x00000FF0U
623#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_SHIFT 4
624#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_MASK 0x0000F000U
625#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_SHIFT 12
626#define EUR_CR_2D_VIRTUAL_FIFO_1 0x0E14
627#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_MASK 0x00000FFFU
628#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_SHIFT 0
629#define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_MASK 0x00FFF000U
630#define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_SHIFT 12
631#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_MASK 0xFF000000U
632#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_SHIFT 24
633#define EUR_CR_2D_SOCIF 0x0E18
634#define EUR_CR_2D_SOCIF_FREESPACE_MASK 0x000000FFU
635#define EUR_CR_2D_SOCIF_FREESPACE_SHIFT 0
636#define EUR_CR_2D_ALPHA 0x0E1C
637#define EUR_CR_2D_ALPHA_COMPONENT_ONE_MASK 0x0000FF00U
638#define EUR_CR_2D_ALPHA_COMPONENT_ONE_SHIFT 8
639#define EUR_CR_2D_ALPHA_COMPONENT_ZERO_MASK 0x000000FFU
640#define EUR_CR_2D_ALPHA_COMPONENT_ZERO_SHIFT 0
641#define EUR_CR_USE_CODE_BASE(X) (0x0A0C + (4 * (X))) 479#define EUR_CR_USE_CODE_BASE(X) (0x0A0C + (4 * (X)))
642#define EUR_CR_USE_CODE_BASE_ADDR_MASK 0x01FFFFFFU 480#define EUR_CR_USE_CODE_BASE_ADDR_MASK 0x000FFFFFU
643#define EUR_CR_USE_CODE_BASE_ADDR_SHIFT 0 481#define EUR_CR_USE_CODE_BASE_ADDR_SHIFT 0
644#define EUR_CR_USE_CODE_BASE_DM_MASK 0x06000000U 482#define EUR_CR_USE_CODE_BASE_DM_MASK 0x00300000U
645#define EUR_CR_USE_CODE_BASE_DM_SHIFT 25 483#define EUR_CR_USE_CODE_BASE_DM_SHIFT 20
646#define EUR_CR_USE_CODE_BASE_SIZE_UINT32 16 484#define EUR_CR_USE_CODE_BASE_SIZE_UINT32 16
647#define EUR_CR_USE_CODE_BASE_NUM_ENTRIES 16 485#define EUR_CR_USE_CODE_BASE_NUM_ENTRIES 16
648 486
diff --git a/drivers/gpu/pvr/sgx544defs.h b/drivers/gpu/pvr/sgx544defs.h
index ff3e1e05da6..c18b8ad042a 100644
--- a/drivers/gpu/pvr/sgx544defs.h
+++ b/drivers/gpu/pvr/sgx544defs.h
@@ -987,6 +987,22 @@
987#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_MASK 0x00000002U 987#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_MASK 0x00000002U
988#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_SHIFT 1 988#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_SHIFT 1
989#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_SIGNED 0 989#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_SIGNED 0
990#define EUR_CR_BIF_MMU_CTRL 0x0CD0
991#define EUR_CR_BIF_MMU_CTRL_PREFETCHING_ON_MASK 0x00000001U
992#define EUR_CR_BIF_MMU_CTRL_PREFETCHING_ON_SHIFT 0
993#define EUR_CR_BIF_MMU_CTRL_PREFETCHING_ON_SIGNED 0
994#define EUR_CR_BIF_MMU_CTRL_ADDR_HASH_MODE_MASK 0x00000006U
995#define EUR_CR_BIF_MMU_CTRL_ADDR_HASH_MODE_SHIFT 1
996#define EUR_CR_BIF_MMU_CTRL_ADDR_HASH_MODE_SIGNED 0
997#define EUR_CR_BIF_MMU_CTRL_ENABLE_WRITE_BURST_COLLATE_MASK 0x00000008U
998#define EUR_CR_BIF_MMU_CTRL_ENABLE_WRITE_BURST_COLLATE_SHIFT 3
999#define EUR_CR_BIF_MMU_CTRL_ENABLE_WRITE_BURST_COLLATE_SIGNED 0
1000#define EUR_CR_BIF_MMU_CTRL_ENABLE_DC_TLB_MASK 0x00000010U
1001#define EUR_CR_BIF_MMU_CTRL_ENABLE_DC_TLB_SHIFT 4
1002#define EUR_CR_BIF_MMU_CTRL_ENABLE_DC_TLB_SIGNED 0
1003#define EUR_CR_BIF_MMU_CTRL_DISABLE_BURST_EXP_MASK 0x00000020U
1004#define EUR_CR_BIF_MMU_CTRL_DISABLE_BURST_EXP_SHIFT 5
1005#define EUR_CR_BIF_MMU_CTRL_DISABLE_BURST_EXP_SIGNED 0
990#define EUR_CR_2D_BLIT_STATUS 0x0E04 1006#define EUR_CR_2D_BLIT_STATUS 0x0E04
991#define EUR_CR_2D_BLIT_STATUS_COMPLETE_MASK 0x00FFFFFFU 1007#define EUR_CR_2D_BLIT_STATUS_COMPLETE_MASK 0x00FFFFFFU
992#define EUR_CR_2D_BLIT_STATUS_COMPLETE_SHIFT 0 1008#define EUR_CR_2D_BLIT_STATUS_COMPLETE_SHIFT 0
diff --git a/drivers/gpu/pvr/sgx_bridge.h b/drivers/gpu/pvr/sgx_bridge.h
index 926c75b69f4..204189c1d18 100644
--- a/drivers/gpu/pvr/sgx_bridge.h
+++ b/drivers/gpu/pvr/sgx_bridge.h
@@ -521,6 +521,7 @@ typedef struct PVRSRV_BRIDGE_OUT_SGX_REGISTER_HW_RENDER_CONTEXT_TAG
521typedef struct PVRSRV_BRIDGE_IN_SGX_UNREGISTER_HW_RENDER_CONTEXT_TAG 521typedef struct PVRSRV_BRIDGE_IN_SGX_UNREGISTER_HW_RENDER_CONTEXT_TAG
522{ 522{
523 IMG_UINT32 ui32BridgeFlags; 523 IMG_UINT32 ui32BridgeFlags;
524 IMG_BOOL bForceCleanup;
524#if defined (SUPPORT_SID_INTERFACE) 525#if defined (SUPPORT_SID_INTERFACE)
525 IMG_SID hDevCookie; 526 IMG_SID hDevCookie;
526 IMG_SID hHWRenderContext; 527 IMG_SID hHWRenderContext;
@@ -554,6 +555,7 @@ typedef struct PVRSRV_BRIDGE_OUT_SGX_REGISTER_HW_TRANSFER_CONTEXT_TAG
554typedef struct PVRSRV_BRIDGE_IN_SGX_UNREGISTER_HW_TRANSFER_CONTEXT_TAG 555typedef struct PVRSRV_BRIDGE_IN_SGX_UNREGISTER_HW_TRANSFER_CONTEXT_TAG
555{ 556{
556 IMG_UINT32 ui32BridgeFlags; 557 IMG_UINT32 ui32BridgeFlags;
558 IMG_BOOL bForceCleanup;
557#if defined (SUPPORT_SID_INTERFACE) 559#if defined (SUPPORT_SID_INTERFACE)
558 IMG_SID hDevCookie; 560 IMG_SID hDevCookie;
559 IMG_SID hHWTransferContext; 561 IMG_SID hHWTransferContext;
@@ -600,6 +602,7 @@ typedef struct PVRSRV_BRIDGE_OUT_SGX_REGISTER_HW_2D_CONTEXT_TAG
600typedef struct PVRSRV_BRIDGE_IN_SGX_UNREGISTER_HW_2D_CONTEXT_TAG 602typedef struct PVRSRV_BRIDGE_IN_SGX_UNREGISTER_HW_2D_CONTEXT_TAG
601{ 603{
602 IMG_UINT32 ui32BridgeFlags; 604 IMG_UINT32 ui32BridgeFlags;
605 IMG_BOOL bForceCleanup;
603#if defined (SUPPORT_SID_INTERFACE) 606#if defined (SUPPORT_SID_INTERFACE)
604 IMG_SID hDevCookie; 607 IMG_SID hDevCookie;
605 IMG_SID hHW2DContext; 608 IMG_SID hHW2DContext;
diff --git a/drivers/gpu/pvr/sgxerrata.h b/drivers/gpu/pvr/sgxerrata.h
index de8f484c8a6..83c0444cc9f 100644
--- a/drivers/gpu/pvr/sgxerrata.h
+++ b/drivers/gpu/pvr/sgxerrata.h
@@ -406,6 +406,18 @@
406 #define FIX_HW_BRN_31425 406 #define FIX_HW_BRN_31425
407 #endif 407 #endif
408 #else 408 #else
409 #if SGX_CORE_REV == 104
410 #define FIX_HW_BRN_29954
411 #define FIX_HW_BRN_31093
412 #define FIX_HW_BRN_31195
413 #define FIX_HW_BRN_31278
414 #if defined(SGX_FEATURE_MP)
415 #define FIX_HW_BRN_31425
416 #endif
417 #define FIX_HW_BRN_31542
418 #define FIX_HW_BRN_31620
419 #define FIX_HW_BRN_31671
420 #else
409 #if SGX_CORE_REV == 105 421 #if SGX_CORE_REV == 105
410 #if defined(SGX_FEATURE_MP) 422 #if defined(SGX_FEATURE_MP)
411 #define FIX_HW_BRN_31425 423 #define FIX_HW_BRN_31425
@@ -420,6 +432,7 @@
420 #endif 432 #endif
421 #endif 433 #endif
422 #endif 434 #endif
435 #endif
423 436
424 #define SGX_CORE_DEFINED 437 #define SGX_CORE_DEFINED
425#endif 438#endif
@@ -471,19 +484,12 @@
471 #define SGX_CORE_REV SGX_CORE_REV_HEAD 484 #define SGX_CORE_REV SGX_CORE_REV_HEAD
472 #endif 485 #endif
473 486
474 #if SGX_CORE_REV == 100
475 #if defined(SGX_FEATURE_MP)
476 #define FIX_HW_BRN_31425
477 #endif
478 #else
479 #if SGX_CORE_REV == 101
480 #if defined(SGX_FEATURE_MP)
481 #define FIX_HW_BRN_31425
482 #endif
483 #else
484 #if SGX_CORE_REV == 123 487 #if SGX_CORE_REV == 123
485 488
486 #else 489 #else
490 #if SGX_CORE_REV == 124
491
492 #else
487 #if SGX_CORE_REV == SGX_CORE_REV_HEAD 493 #if SGX_CORE_REV == SGX_CORE_REV_HEAD
488 494
489 #else 495 #else
@@ -491,7 +497,6 @@
491 #endif 497 #endif
492 #endif 498 #endif
493 #endif 499 #endif
494 #endif
495 500
496 #define SGX_CORE_DEFINED 501 #define SGX_CORE_DEFINED
497#endif 502#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-25 01:15:49 -0400