3 files changed, 35 insertions, 1 deletions

diff --git a/arch/m68k/include/asm/m53xxacr.h b/arch/m68k/include/asm/m53xxacr.h
index 74c81c9b177..d8b8dd68368 100644
--- a/arch/m68k/include/asm/m53xxacr.h
+++ b/arch/m68k/include/asm/m53xxacr.h
@@ -53,6 +53,12 @@
  * CACR is cache inhibited, we use the ACR register to set cacheing
  * enabled on the regions we want (eg RAM).
  */
+#if defined(CONFIG_CACHE_COPYBACK)
+#define CACHE_TYPE      ACR_CM_CB
+#else
+#define CACHE_TYPE      ACR_CM_WT
+#endif
+
 #ifdef CONFIG_COLDFIRE_SW_A7
 #define CACHE_MODE      (CACR_EC + CACR_ESB + CACR_DCM_PRE)
 #else
@@ -63,7 +69,7 @@
 
 #define ACR0_MODE       ((CONFIG_RAMBASE & 0xff000000) + \
                          (0x000f0000) + \
-                         (ACR_ENABLE + ACR_ANY + ACR_CM_CB))
+                         (ACR_ENABLE + ACR_ANY + CACHE_TYPE))
 #define ACR1_MODE       0
 
 /****************************************************************************/
diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h
index 6bce82fdb9c..29d4713f796 100644
--- a/arch/m68k/include/asm/m54xxacr.h
+++ b/arch/m68k/include/asm/m54xxacr.h
@@ -73,7 +73,11 @@
 #else
 #define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC+CACR_EUSP)
 #endif
+#if defined(CONFIG_CACHE_COPYBACK)
+#define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_CP)
+#else
 #define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_WT)
+#endif
 #define INSN_CACHE_MODE (ACR_ENABLE+ACR_ANY)
 
 #define CACHE_INIT      (CACR_DCINVA+CACR_BCINVA+CACR_ICINVA)
diff --git a/arch/m68knommu/Kconfig b/arch/m68knommu/Kconfig
index 61c29081b99..89b12237e1e 100644
--- a/arch/m68knommu/Kconfig
+++ b/arch/m68knommu/Kconfig
@@ -82,6 +82,9 @@ config COLDFIRE_SW_A7
 config HAVE_CACHE_SPLIT
         bool
 
+config HAVE_CACHE_CB
+        bool
+
 source "init/Kconfig"
 
 source "kernel/Kconfig.freezer"
@@ -172,27 +175,32 @@ config M528x
 config M5307
         bool "MCF5307"
         select COLDFIRE_SW_A7
+        select HAVE_CACHE_CB
         help
           Motorola ColdFire 5307 processor support.
 
 config M532x
         bool "MCF532x"
+        select HAVE_CACHE_CB
         help
           Freescale (Motorola) ColdFire 532x processor support.
 
 config M5407
         bool "MCF5407"
         select COLDFIRE_SW_A7
+        select HAVE_CACHE_CB
         help
           Motorola ColdFire 5407 processor support.
 
 config M547x
         bool "MCF547x"
+        select HAVE_CACHE_CB
         help
           Freescale ColdFire 5470/5471/5472/5473/5474/5475 processor support.
 
 config M548x
         bool "MCF548x"
+        select HAVE_CACHE_CB
         help
           Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support.
 
@@ -279,7 +287,23 @@ config CACHE_BOTH
           Split the ColdFire CPU cache, and use half as an instruction cache
           and half as a data cache.
 endchoice
+endif
+
+if HAVE_CACHE_CB
+choice
+        prompt "Data cache mode"
+        default CACHE_WRITETHRU
 
+config CACHE_WRITETHRU
+        bool "Write-through"
+        help
+          The ColdFire CPU cache is set into Write-through mode.
+
+config CACHE_COPYBACK
+        bool "Copy-back"
+        help
+          The ColdFire CPU cache is set into Copy-back mode.
+endchoice
 endif
 
 comment "Platform"