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-rw-r--r--arch/arm/kernel/smp_twd.c69
-rw-r--r--arch/arm/mach-omap2/clkt_dpll.c14
-rw-r--r--arch/arm/mach-omap2/clock.c24
-rw-r--r--arch/arm/mach-omap2/clock.h1
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c257
-rw-r--r--arch/arm/mach-omap2/clockdomain.c7
-rw-r--r--arch/arm/mach-omap2/clockdomain44xx.c7
-rw-r--r--arch/arm/mach-omap2/hsmmc.c7
-rw-r--r--arch/arm/mach-omap2/omap-smp.c1
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c5
-rw-r--r--arch/arm/mach-omap2/powerdomain.h12
-rw-r--r--arch/arm/mach-omap2/powerdomains44xx_data.c30
-rw-r--r--arch/arm/mach-omap2/serial.c2
-rw-r--r--arch/arm/plat-omap/include/plat/clock.h4
-rw-r--r--arch/arm/plat-omap/include/plat/cpu.h4
-rw-r--r--arch/arm/plat-omap/include/plat/mmc.h5
-rw-r--r--drivers/mmc/host/omap_hsmmc.c13
-rw-r--r--drivers/regulator/twl-regulator.c2
-rw-r--r--include/linux/clockchips.h2
-rw-r--r--kernel/time/clockevents.c24
20 files changed, 318 insertions, 172 deletions
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index 2c277d40cee..27761cacd7b 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -10,21 +10,29 @@
10 */ 10 */
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/kernel.h> 12#include <linux/kernel.h>
13#include <linux/clk.h>
14#include <linux/cpufreq.h>
13#include <linux/delay.h> 15#include <linux/delay.h>
14#include <linux/device.h> 16#include <linux/device.h>
17#include <linux/err.h>
15#include <linux/smp.h> 18#include <linux/smp.h>
16#include <linux/jiffies.h> 19#include <linux/jiffies.h>
17#include <linux/clockchips.h> 20#include <linux/clockchips.h>
18#include <linux/irq.h> 21#include <linux/irq.h>
19#include <linux/io.h> 22#include <linux/io.h>
23#include <linux/percpu.h>
20 24
21#include <asm/smp_twd.h> 25#include <asm/smp_twd.h>
22#include <asm/hardware/gic.h> 26#include <asm/hardware/gic.h>
23 27
28#define TWD_MIN_RANGE 4
29
24/* set up by the platform code */ 30/* set up by the platform code */
25void __iomem *twd_base; 31void __iomem *twd_base;
26 32
33static struct clk *twd_clk;
27static unsigned long twd_timer_rate; 34static unsigned long twd_timer_rate;
35static DEFINE_PER_CPU(struct clock_event_device *, twd_ce);
28 36
29static void twd_set_mode(enum clock_event_mode mode, 37static void twd_set_mode(enum clock_event_mode mode,
30 struct clock_event_device *clk) 38 struct clock_event_device *clk)
@@ -80,6 +88,49 @@ int twd_timer_ack(void)
80 return 0; 88 return 0;
81} 89}
82 90
91/*
92 * Updates clockevent frequency when the cpu frequency changes.
93 * Called on the cpu that is changing frequency with interrupts disabled.
94 */
95static void twd_update_frequency(void *data)
96{
97 twd_timer_rate = clk_get_rate(twd_clk);
98
99 clockevents_reconfigure(__get_cpu_var(twd_ce), twd_timer_rate,
100 TWD_MIN_RANGE);
101}
102
103static int twd_cpufreq_transition(struct notifier_block *nb,
104 unsigned long state, void *data)
105{
106 struct cpufreq_freqs *freqs = data;
107
108 /*
109 * The twd clock events must be reprogrammed to account for the new
110 * frequency. The timer is local to a cpu, so cross-call to the
111 * changing cpu.
112 */
113 if (state == CPUFREQ_POSTCHANGE || state == CPUFREQ_RESUMECHANGE)
114 smp_call_function_single(freqs->cpu, twd_update_frequency,
115 NULL, 1);
116
117 return NOTIFY_OK;
118}
119
120static struct notifier_block twd_cpufreq_nb = {
121 .notifier_call = twd_cpufreq_transition,
122};
123
124static int twd_cpufreq_init(void)
125{
126 if (!IS_ERR_OR_NULL(twd_clk))
127 return cpufreq_register_notifier(&twd_cpufreq_nb,
128 CPUFREQ_TRANSITION_NOTIFIER);
129
130 return 0;
131}
132core_initcall(twd_cpufreq_init);
133
83static void __cpuinit twd_calibrate_rate(void) 134static void __cpuinit twd_calibrate_rate(void)
84{ 135{
85 unsigned long count; 136 unsigned long count;
@@ -124,7 +175,16 @@ static void __cpuinit twd_calibrate_rate(void)
124 */ 175 */
125void __cpuinit twd_timer_setup(struct clock_event_device *clk) 176void __cpuinit twd_timer_setup(struct clock_event_device *clk)
126{ 177{
127 twd_calibrate_rate(); 178 if (twd_clk == NULL) {
179 twd_clk = clk_get_sys("smp_twd", NULL);
180 if (IS_ERR_OR_NULL(twd_clk))
181 pr_warn("%s: no clock found\n", __func__);
182 }
183
184 if (!IS_ERR_OR_NULL(twd_clk))
185 twd_timer_rate = clk_get_rate(twd_clk);
186 else
187 twd_calibrate_rate();
128 188
129 clk->name = "local_timer"; 189 clk->name = "local_timer";
130 clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | 190 clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
@@ -132,13 +192,16 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk)
132 clk->rating = 350; 192 clk->rating = 350;
133 clk->set_mode = twd_set_mode; 193 clk->set_mode = twd_set_mode;
134 clk->set_next_event = twd_set_next_event; 194 clk->set_next_event = twd_set_next_event;
135 clk->shift = 20; 195
136 clk->mult = div_sc(twd_timer_rate, NSEC_PER_SEC, clk->shift); 196 clockevents_calc_mult_shift(clk, twd_timer_rate, TWD_MIN_RANGE);
197
137 clk->max_delta_ns = clockevent_delta2ns(0xffffffff, clk); 198 clk->max_delta_ns = clockevent_delta2ns(0xffffffff, clk);
138 clk->min_delta_ns = clockevent_delta2ns(0xf, clk); 199 clk->min_delta_ns = clockevent_delta2ns(0xf, clk);
139 200
140 /* Make sure our local interrupt controller has this enabled */ 201 /* Make sure our local interrupt controller has this enabled */
141 gic_enable_ppi(clk->irq); 202 gic_enable_ppi(clk->irq);
142 203
204 __get_cpu_var(twd_ce) = clk;
205
143 clockevents_register_device(clk); 206 clockevents_register_device(clk);
144} 207}
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index bcffee001bf..a7e78e4104f 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -292,12 +292,14 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
292 292
293 for (n = dd->min_divider; n <= dd->max_divider; n++) { 293 for (n = dd->min_divider; n <= dd->max_divider; n++) {
294 294
295 /* Is the (input clk, divider) pair valid for the DPLL? */ 295 if (cpu_is_omap34xx()) {
296 r = _dpll_test_fint(clk, n); 296 /* Is the (input clk, divider)pair valid for the DPLL?*/
297 if (r == DPLL_FINT_UNDERFLOW) 297 r = _dpll_test_fint(clk, n);
298 break; 298 if (r == DPLL_FINT_UNDERFLOW)
299 else if (r == DPLL_FINT_INVALID) 299 break;
300 continue; 300 else if (r == DPLL_FINT_INVALID)
301 continue;
302 }
301 303
302 /* Compute the scaled DPLL multiplier, based on the divider */ 304 /* Compute the scaled DPLL multiplier, based on the divider */
303 m = scaled_rt_rp * n; 305 m = scaled_rt_rp * n;
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 180299e4a83..1334f595eab 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -32,6 +32,7 @@
32 32
33#include "clock.h" 33#include "clock.h"
34#include "cm2xxx_3xxx.h" 34#include "cm2xxx_3xxx.h"
35#include "cm44xx.h"
35#include "cm-regbits-24xx.h" 36#include "cm-regbits-24xx.h"
36#include "cm-regbits-34xx.h" 37#include "cm-regbits-34xx.h"
37 38
@@ -43,6 +44,11 @@ u8 cpu_mask;
43 44
44/* Private functions */ 45/* Private functions */
45 46
47static void _omap4_module_wait_ready(struct clk *clk)
48{
49 omap4_cm_wait_module_ready(clk->enable_reg);
50}
51
46/** 52/**
47 * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE 53 * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE
48 * @clk: struct clk * belonging to the module 54 * @clk: struct clk * belonging to the module
@@ -190,8 +196,12 @@ int omap2_dflt_clk_enable(struct clk *clk)
190 __raw_writel(v, clk->enable_reg); 196 __raw_writel(v, clk->enable_reg);
191 v = __raw_readl(clk->enable_reg); /* OCP barrier */ 197 v = __raw_readl(clk->enable_reg); /* OCP barrier */
192 198
193 if (clk->ops->find_idlest) 199 if (clk->ops->find_idlest) {
194 _omap2_module_wait_ready(clk); 200 if (cpu_is_omap44xx())
201 _omap4_module_wait_ready(clk);
202 else
203 _omap2_module_wait_ready(clk);
204 }
195 205
196 return 0; 206 return 0;
197} 207}
@@ -219,6 +229,12 @@ void omap2_dflt_clk_disable(struct clk *clk)
219 /* No OCP barrier needed here since it is a disable operation */ 229 /* No OCP barrier needed here since it is a disable operation */
220} 230}
221 231
232const struct clkops clkops_omap4_dflt_wait = {
233 .enable = omap2_dflt_clk_enable,
234 .disable = omap2_dflt_clk_disable,
235 .find_idlest = omap2_clk_dflt_find_idlest,
236};
237
222const struct clkops clkops_omap2_dflt_wait = { 238const struct clkops clkops_omap2_dflt_wait = {
223 .enable = omap2_dflt_clk_enable, 239 .enable = omap2_dflt_clk_enable,
224 .disable = omap2_dflt_clk_disable, 240 .disable = omap2_dflt_clk_disable,
@@ -327,6 +343,10 @@ int omap2_clk_enable(struct clk *clk)
327 } 343 }
328 } 344 }
329 345
346 /* If clockdomain supports hardware control, enable it */
347 if (clk->clkdm)
348 clkdm_allow_idle(clk->clkdm);
349
330 return 0; 350 return 0;
331 351
332oce_err3: 352oce_err3:
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 014be5b215b..6b26929624f 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -135,6 +135,7 @@ extern u8 cpu_mask;
135extern const struct clkops clkops_omap2_dflt_wait; 135extern const struct clkops clkops_omap2_dflt_wait;
136extern const struct clkops clkops_dummy; 136extern const struct clkops clkops_dummy;
137extern const struct clkops clkops_omap2_dflt; 137extern const struct clkops clkops_omap2_dflt;
138extern const struct clkops clkops_omap4_dflt_wait;
138 139
139extern struct clk_functions omap2_clk_functions; 140extern struct clk_functions omap2_clk_functions;
140extern struct clk *vclk, *sclk; 141extern struct clk *vclk, *sclk;
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index ffa66424368..7dfa65f1baf 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -53,7 +53,7 @@ static struct clk extalt_clkin_ck = {
53static struct clk pad_clks_ck = { 53static struct clk pad_clks_ck = {
54 .name = "pad_clks_ck", 54 .name = "pad_clks_ck",
55 .rate = 12000000, 55 .rate = 12000000,
56 .ops = &clkops_omap2_dflt, 56 .ops = &clkops_omap4_dflt_wait,
57 .enable_reg = OMAP4430_CM_CLKSEL_ABE, 57 .enable_reg = OMAP4430_CM_CLKSEL_ABE,
58 .enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT, 58 .enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT,
59}; 59};
@@ -73,7 +73,7 @@ static struct clk secure_32k_clk_src_ck = {
73static struct clk slimbus_clk = { 73static struct clk slimbus_clk = {
74 .name = "slimbus_clk", 74 .name = "slimbus_clk",
75 .rate = 12000000, 75 .rate = 12000000,
76 .ops = &clkops_omap2_dflt, 76 .ops = &clkops_omap4_dflt_wait,
77 .enable_reg = OMAP4430_CM_CLKSEL_ABE, 77 .enable_reg = OMAP4430_CM_CLKSEL_ABE,
78 .enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT, 78 .enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
79}; 79};
@@ -621,7 +621,7 @@ static struct clk dpll_core_m3x2_ck = {
621 .clksel = dpll_core_m6x2_div, 621 .clksel = dpll_core_m6x2_div,
622 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE, 622 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
623 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, 623 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
624 .ops = &clkops_omap2_dflt, 624 .ops = &clkops_omap4_dflt_wait,
625 .enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE, 625 .enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
626 .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, 626 .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
627 .recalc = &omap2_clksel_recalc, 627 .recalc = &omap2_clksel_recalc,
@@ -888,7 +888,7 @@ static struct clk dpll_per_m3x2_ck = {
888 .clksel = dpll_per_m2x2_div, 888 .clksel = dpll_per_m2x2_div,
889 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER, 889 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
890 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, 890 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
891 .ops = &clkops_omap2_dflt, 891 .ops = &clkops_omap4_dflt_wait,
892 .enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER, 892 .enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
893 .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, 893 .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
894 .recalc = &omap2_clksel_recalc, 894 .recalc = &omap2_clksel_recalc,
@@ -1374,7 +1374,7 @@ static struct clk syc_clk_div_ck = {
1374 1374
1375static struct clk aes1_fck = { 1375static struct clk aes1_fck = {
1376 .name = "aes1_fck", 1376 .name = "aes1_fck",
1377 .ops = &clkops_omap2_dflt, 1377 .ops = &clkops_omap4_dflt_wait,
1378 .enable_reg = OMAP4430_CM_L4SEC_AES1_CLKCTRL, 1378 .enable_reg = OMAP4430_CM_L4SEC_AES1_CLKCTRL,
1379 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1379 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1380 .clkdm_name = "l4_secure_clkdm", 1380 .clkdm_name = "l4_secure_clkdm",
@@ -1384,7 +1384,7 @@ static struct clk aes1_fck = {
1384 1384
1385static struct clk aes2_fck = { 1385static struct clk aes2_fck = {
1386 .name = "aes2_fck", 1386 .name = "aes2_fck",
1387 .ops = &clkops_omap2_dflt, 1387 .ops = &clkops_omap4_dflt_wait,
1388 .enable_reg = OMAP4430_CM_L4SEC_AES2_CLKCTRL, 1388 .enable_reg = OMAP4430_CM_L4SEC_AES2_CLKCTRL,
1389 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1389 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1390 .clkdm_name = "l4_secure_clkdm", 1390 .clkdm_name = "l4_secure_clkdm",
@@ -1394,7 +1394,7 @@ static struct clk aes2_fck = {
1394 1394
1395static struct clk aess_fck = { 1395static struct clk aess_fck = {
1396 .name = "aess_fck", 1396 .name = "aess_fck",
1397 .ops = &clkops_omap2_dflt, 1397 .ops = &clkops_omap4_dflt_wait,
1398 .enable_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, 1398 .enable_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
1399 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1399 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1400 .clkdm_name = "abe_clkdm", 1400 .clkdm_name = "abe_clkdm",
@@ -1404,7 +1404,7 @@ static struct clk aess_fck = {
1404 1404
1405static struct clk bandgap_fclk = { 1405static struct clk bandgap_fclk = {
1406 .name = "bandgap_fclk", 1406 .name = "bandgap_fclk",
1407 .ops = &clkops_omap2_dflt, 1407 .ops = &clkops_omap4_dflt_wait,
1408 .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, 1408 .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1409 .enable_bit = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, 1409 .enable_bit = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT,
1410 .clkdm_name = "l4_wkup_clkdm", 1410 .clkdm_name = "l4_wkup_clkdm",
@@ -1424,7 +1424,7 @@ static struct clk bandgap_ts_fclk = {
1424 1424
1425static struct clk des3des_fck = { 1425static struct clk des3des_fck = {
1426 .name = "des3des_fck", 1426 .name = "des3des_fck",
1427 .ops = &clkops_omap2_dflt, 1427 .ops = &clkops_omap4_dflt_wait,
1428 .enable_reg = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL, 1428 .enable_reg = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
1429 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1429 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1430 .clkdm_name = "l4_secure_clkdm", 1430 .clkdm_name = "l4_secure_clkdm",
@@ -1465,7 +1465,7 @@ static struct clk dmic_fck = {
1465 .init = &omap2_init_clksel_parent, 1465 .init = &omap2_init_clksel_parent,
1466 .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, 1466 .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1467 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, 1467 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1468 .ops = &clkops_omap2_dflt, 1468 .ops = &clkops_omap4_dflt_wait,
1469 .recalc = &omap2_clksel_recalc, 1469 .recalc = &omap2_clksel_recalc,
1470 .enable_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, 1470 .enable_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1471 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1471 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -1474,7 +1474,7 @@ static struct clk dmic_fck = {
1474 1474
1475static struct clk dsp_fck = { 1475static struct clk dsp_fck = {
1476 .name = "dsp_fck", 1476 .name = "dsp_fck",
1477 .ops = &clkops_omap2_dflt, 1477 .ops = &clkops_omap4_dflt_wait,
1478 .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL, 1478 .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1479 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1479 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1480 .clkdm_name = "tesla_clkdm", 1480 .clkdm_name = "tesla_clkdm",
@@ -1484,7 +1484,7 @@ static struct clk dsp_fck = {
1484 1484
1485static struct clk dss_sys_clk = { 1485static struct clk dss_sys_clk = {
1486 .name = "dss_sys_clk", 1486 .name = "dss_sys_clk",
1487 .ops = &clkops_omap2_dflt, 1487 .ops = &clkops_omap4_dflt_wait,
1488 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, 1488 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1489 .enable_bit = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, 1489 .enable_bit = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT,
1490 .clkdm_name = "l3_dss_clkdm", 1490 .clkdm_name = "l3_dss_clkdm",
@@ -1494,7 +1494,7 @@ static struct clk dss_sys_clk = {
1494 1494
1495static struct clk dss_tv_clk = { 1495static struct clk dss_tv_clk = {
1496 .name = "dss_tv_clk", 1496 .name = "dss_tv_clk",
1497 .ops = &clkops_omap2_dflt, 1497 .ops = &clkops_omap4_dflt_wait,
1498 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, 1498 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1499 .enable_bit = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 1499 .enable_bit = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT,
1500 .clkdm_name = "l3_dss_clkdm", 1500 .clkdm_name = "l3_dss_clkdm",
@@ -1504,7 +1504,7 @@ static struct clk dss_tv_clk = {
1504 1504
1505static struct clk dss_dss_clk = { 1505static struct clk dss_dss_clk = {
1506 .name = "dss_dss_clk", 1506 .name = "dss_dss_clk",
1507 .ops = &clkops_omap2_dflt, 1507 .ops = &clkops_omap4_dflt_wait,
1508 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, 1508 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1509 .enable_bit = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT, 1509 .enable_bit = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
1510 .clkdm_name = "l3_dss_clkdm", 1510 .clkdm_name = "l3_dss_clkdm",
@@ -1514,7 +1514,7 @@ static struct clk dss_dss_clk = {
1514 1514
1515static struct clk dss_48mhz_clk = { 1515static struct clk dss_48mhz_clk = {
1516 .name = "dss_48mhz_clk", 1516 .name = "dss_48mhz_clk",
1517 .ops = &clkops_omap2_dflt, 1517 .ops = &clkops_omap4_dflt_wait,
1518 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, 1518 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1519 .enable_bit = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT, 1519 .enable_bit = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
1520 .clkdm_name = "l3_dss_clkdm", 1520 .clkdm_name = "l3_dss_clkdm",
@@ -1524,7 +1524,7 @@ static struct clk dss_48mhz_clk = {
1524 1524
1525static struct clk dss_fck = { 1525static struct clk dss_fck = {
1526 .name = "dss_fck", 1526 .name = "dss_fck",
1527 .ops = &clkops_omap2_dflt, 1527 .ops = &clkops_omap4_dflt_wait,
1528 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, 1528 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1529 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1529 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1530 .clkdm_name = "l3_dss_clkdm", 1530 .clkdm_name = "l3_dss_clkdm",
@@ -1534,7 +1534,7 @@ static struct clk dss_fck = {
1534 1534
1535static struct clk efuse_ctrl_cust_fck = { 1535static struct clk efuse_ctrl_cust_fck = {
1536 .name = "efuse_ctrl_cust_fck", 1536 .name = "efuse_ctrl_cust_fck",
1537 .ops = &clkops_omap2_dflt, 1537 .ops = &clkops_omap4_dflt_wait,
1538 .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL, 1538 .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
1539 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1539 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1540 .clkdm_name = "l4_cefuse_clkdm", 1540 .clkdm_name = "l4_cefuse_clkdm",
@@ -1544,7 +1544,7 @@ static struct clk efuse_ctrl_cust_fck = {
1544 1544
1545static struct clk emif1_fck = { 1545static struct clk emif1_fck = {
1546 .name = "emif1_fck", 1546 .name = "emif1_fck",
1547 .ops = &clkops_omap2_dflt, 1547 .ops = &clkops_omap4_dflt_wait,
1548 .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL, 1548 .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
1549 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1549 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1550 .flags = ENABLE_ON_INIT, 1550 .flags = ENABLE_ON_INIT,
@@ -1555,7 +1555,7 @@ static struct clk emif1_fck = {
1555 1555
1556static struct clk emif2_fck = { 1556static struct clk emif2_fck = {
1557 .name = "emif2_fck", 1557 .name = "emif2_fck",
1558 .ops = &clkops_omap2_dflt, 1558 .ops = &clkops_omap4_dflt_wait,
1559 .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL, 1559 .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
1560 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1560 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1561 .flags = ENABLE_ON_INIT, 1561 .flags = ENABLE_ON_INIT,
@@ -1576,7 +1576,7 @@ static struct clk fdif_fck = {
1576 .clksel = fdif_fclk_div, 1576 .clksel = fdif_fclk_div,
1577 .clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL, 1577 .clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1578 .clksel_mask = OMAP4430_CLKSEL_FCLK_MASK, 1578 .clksel_mask = OMAP4430_CLKSEL_FCLK_MASK,
1579 .ops = &clkops_omap2_dflt, 1579 .ops = &clkops_omap4_dflt_wait,
1580 .recalc = &omap2_clksel_recalc, 1580 .recalc = &omap2_clksel_recalc,
1581 .round_rate = &omap2_clksel_round_rate, 1581 .round_rate = &omap2_clksel_round_rate,
1582 .set_rate = &omap2_clksel_set_rate, 1582 .set_rate = &omap2_clksel_set_rate,
@@ -1587,7 +1587,7 @@ static struct clk fdif_fck = {
1587 1587
1588static struct clk fpka_fck = { 1588static struct clk fpka_fck = {
1589 .name = "fpka_fck", 1589 .name = "fpka_fck",
1590 .ops = &clkops_omap2_dflt, 1590 .ops = &clkops_omap4_dflt_wait,
1591 .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL, 1591 .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
1592 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1592 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1593 .clkdm_name = "l4_secure_clkdm", 1593 .clkdm_name = "l4_secure_clkdm",
@@ -1597,7 +1597,7 @@ static struct clk fpka_fck = {
1597 1597
1598static struct clk gpio1_dbclk = { 1598static struct clk gpio1_dbclk = {
1599 .name = "gpio1_dbclk", 1599 .name = "gpio1_dbclk",
1600 .ops = &clkops_omap2_dflt, 1600 .ops = &clkops_omap4_dflt_wait,
1601 .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, 1601 .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1602 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 1602 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1603 .clkdm_name = "l4_wkup_clkdm", 1603 .clkdm_name = "l4_wkup_clkdm",
@@ -1607,7 +1607,7 @@ static struct clk gpio1_dbclk = {
1607 1607
1608static struct clk gpio1_ick = { 1608static struct clk gpio1_ick = {
1609 .name = "gpio1_ick", 1609 .name = "gpio1_ick",
1610 .ops = &clkops_omap2_dflt, 1610 .ops = &clkops_omap4_dflt_wait,
1611 .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, 1611 .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1612 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1612 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1613 .clkdm_name = "l4_wkup_clkdm", 1613 .clkdm_name = "l4_wkup_clkdm",
@@ -1617,7 +1617,7 @@ static struct clk gpio1_ick = {
1617 1617
1618static struct clk gpio2_dbclk = { 1618static struct clk gpio2_dbclk = {
1619 .name = "gpio2_dbclk", 1619 .name = "gpio2_dbclk",
1620 .ops = &clkops_omap2_dflt, 1620 .ops = &clkops_omap4_dflt_wait,
1621 .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, 1621 .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1622 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 1622 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1623 .clkdm_name = "l4_per_clkdm", 1623 .clkdm_name = "l4_per_clkdm",
@@ -1627,7 +1627,7 @@ static struct clk gpio2_dbclk = {
1627 1627
1628static struct clk gpio2_ick = { 1628static struct clk gpio2_ick = {
1629 .name = "gpio2_ick", 1629 .name = "gpio2_ick",
1630 .ops = &clkops_omap2_dflt, 1630 .ops = &clkops_omap4_dflt_wait,
1631 .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, 1631 .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1632 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1632 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1633 .clkdm_name = "l4_per_clkdm", 1633 .clkdm_name = "l4_per_clkdm",
@@ -1637,7 +1637,7 @@ static struct clk gpio2_ick = {
1637 1637
1638static struct clk gpio3_dbclk = { 1638static struct clk gpio3_dbclk = {
1639 .name = "gpio3_dbclk", 1639 .name = "gpio3_dbclk",
1640 .ops = &clkops_omap2_dflt, 1640 .ops = &clkops_omap4_dflt_wait,
1641 .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, 1641 .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1642 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 1642 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1643 .clkdm_name = "l4_per_clkdm", 1643 .clkdm_name = "l4_per_clkdm",
@@ -1647,7 +1647,7 @@ static struct clk gpio3_dbclk = {
1647 1647
1648static struct clk gpio3_ick = { 1648static struct clk gpio3_ick = {
1649 .name = "gpio3_ick", 1649 .name = "gpio3_ick",
1650 .ops = &clkops_omap2_dflt, 1650 .ops = &clkops_omap4_dflt_wait,
1651 .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, 1651 .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1652 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1652 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1653 .clkdm_name = "l4_per_clkdm", 1653 .clkdm_name = "l4_per_clkdm",
@@ -1657,7 +1657,7 @@ static struct clk gpio3_ick = {
1657 1657
1658static struct clk gpio4_dbclk = { 1658static struct clk gpio4_dbclk = {
1659 .name = "gpio4_dbclk", 1659 .name = "gpio4_dbclk",
1660 .ops = &clkops_omap2_dflt, 1660 .ops = &clkops_omap4_dflt_wait,
1661 .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, 1661 .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1662 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 1662 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1663 .clkdm_name = "l4_per_clkdm", 1663 .clkdm_name = "l4_per_clkdm",
@@ -1667,7 +1667,7 @@ static struct clk gpio4_dbclk = {
1667 1667
1668static struct clk gpio4_ick = { 1668static struct clk gpio4_ick = {
1669 .name = "gpio4_ick", 1669 .name = "gpio4_ick",
1670 .ops = &clkops_omap2_dflt, 1670 .ops = &clkops_omap4_dflt_wait,
1671 .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, 1671 .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1672 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1672 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1673 .clkdm_name = "l4_per_clkdm", 1673 .clkdm_name = "l4_per_clkdm",
@@ -1677,7 +1677,7 @@ static struct clk gpio4_ick = {
1677 1677
1678static struct clk gpio5_dbclk = { 1678static struct clk gpio5_dbclk = {
1679 .name = "gpio5_dbclk", 1679 .name = "gpio5_dbclk",
1680 .ops = &clkops_omap2_dflt, 1680 .ops = &clkops_omap4_dflt_wait,
1681 .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, 1681 .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1682 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 1682 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1683 .clkdm_name = "l4_per_clkdm", 1683 .clkdm_name = "l4_per_clkdm",
@@ -1687,7 +1687,7 @@ static struct clk gpio5_dbclk = {
1687 1687
1688static struct clk gpio5_ick = { 1688static struct clk gpio5_ick = {
1689 .name = "gpio5_ick", 1689 .name = "gpio5_ick",
1690 .ops = &clkops_omap2_dflt, 1690 .ops = &clkops_omap4_dflt_wait,
1691 .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, 1691 .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1692 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1692 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1693 .clkdm_name = "l4_per_clkdm", 1693 .clkdm_name = "l4_per_clkdm",
@@ -1697,7 +1697,7 @@ static struct clk gpio5_ick = {
1697 1697
1698static struct clk gpio6_dbclk = { 1698static struct clk gpio6_dbclk = {
1699 .name = "gpio6_dbclk", 1699 .name = "gpio6_dbclk",
1700 .ops = &clkops_omap2_dflt, 1700 .ops = &clkops_omap4_dflt_wait,
1701 .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, 1701 .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1702 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 1702 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1703 .clkdm_name = "l4_per_clkdm", 1703 .clkdm_name = "l4_per_clkdm",
@@ -1707,7 +1707,7 @@ static struct clk gpio6_dbclk = {
1707 1707
1708static struct clk gpio6_ick = { 1708static struct clk gpio6_ick = {
1709 .name = "gpio6_ick", 1709 .name = "gpio6_ick",
1710 .ops = &clkops_omap2_dflt, 1710 .ops = &clkops_omap4_dflt_wait,
1711 .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, 1711 .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1712 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1712 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1713 .clkdm_name = "l4_per_clkdm", 1713 .clkdm_name = "l4_per_clkdm",
@@ -1717,7 +1717,7 @@ static struct clk gpio6_ick = {
1717 1717
1718static struct clk gpmc_ick = { 1718static struct clk gpmc_ick = {
1719 .name = "gpmc_ick", 1719 .name = "gpmc_ick",
1720 .ops = &clkops_omap2_dflt, 1720 .ops = &clkops_omap4_dflt_wait,
1721 .enable_reg = OMAP4430_CM_L3_2_GPMC_CLKCTRL, 1721 .enable_reg = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
1722 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1722 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1723 .clkdm_name = "l3_2_clkdm", 1723 .clkdm_name = "l3_2_clkdm",
@@ -1739,7 +1739,7 @@ static struct clk gpu_fck = {
1739 .init = &omap2_init_clksel_parent, 1739 .init = &omap2_init_clksel_parent,
1740 .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, 1740 .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1741 .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK, 1741 .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK,
1742 .ops = &clkops_omap2_dflt, 1742 .ops = &clkops_omap4_dflt_wait,
1743 .recalc = &omap2_clksel_recalc, 1743 .recalc = &omap2_clksel_recalc,
1744 .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, 1744 .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1745 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1745 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -1748,7 +1748,7 @@ static struct clk gpu_fck = {
1748 1748
1749static struct clk hdq1w_fck = { 1749static struct clk hdq1w_fck = {
1750 .name = "hdq1w_fck", 1750 .name = "hdq1w_fck",
1751 .ops = &clkops_omap2_dflt, 1751 .ops = &clkops_omap4_dflt_wait,
1752 .enable_reg = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL, 1752 .enable_reg = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
1753 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1753 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1754 .clkdm_name = "l4_per_clkdm", 1754 .clkdm_name = "l4_per_clkdm",
@@ -1768,7 +1768,7 @@ static struct clk hsi_fck = {
1768 .clksel = hsi_fclk_div, 1768 .clksel = hsi_fclk_div,
1769 .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, 1769 .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1770 .clksel_mask = OMAP4430_CLKSEL_24_25_MASK, 1770 .clksel_mask = OMAP4430_CLKSEL_24_25_MASK,
1771 .ops = &clkops_omap2_dflt, 1771 .ops = &clkops_omap4_dflt_wait,
1772 .recalc = &omap2_clksel_recalc, 1772 .recalc = &omap2_clksel_recalc,
1773 .round_rate = &omap2_clksel_round_rate, 1773 .round_rate = &omap2_clksel_round_rate,
1774 .set_rate = &omap2_clksel_set_rate, 1774 .set_rate = &omap2_clksel_set_rate,
@@ -1779,7 +1779,7 @@ static struct clk hsi_fck = {
1779 1779
1780static struct clk i2c1_fck = { 1780static struct clk i2c1_fck = {
1781 .name = "i2c1_fck", 1781 .name = "i2c1_fck",
1782 .ops = &clkops_omap2_dflt, 1782 .ops = &clkops_omap4_dflt_wait,
1783 .enable_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL, 1783 .enable_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
1784 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1784 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1785 .clkdm_name = "l4_per_clkdm", 1785 .clkdm_name = "l4_per_clkdm",
@@ -1789,7 +1789,7 @@ static struct clk i2c1_fck = {
1789 1789
1790static struct clk i2c2_fck = { 1790static struct clk i2c2_fck = {
1791 .name = "i2c2_fck", 1791 .name = "i2c2_fck",
1792 .ops = &clkops_omap2_dflt, 1792 .ops = &clkops_omap4_dflt_wait,
1793 .enable_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL, 1793 .enable_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
1794 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1794 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1795 .clkdm_name = "l4_per_clkdm", 1795 .clkdm_name = "l4_per_clkdm",
@@ -1799,7 +1799,7 @@ static struct clk i2c2_fck = {
1799 1799
1800static struct clk i2c3_fck = { 1800static struct clk i2c3_fck = {
1801 .name = "i2c3_fck", 1801 .name = "i2c3_fck",
1802 .ops = &clkops_omap2_dflt, 1802 .ops = &clkops_omap4_dflt_wait,
1803 .enable_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL, 1803 .enable_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
1804 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1804 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1805 .clkdm_name = "l4_per_clkdm", 1805 .clkdm_name = "l4_per_clkdm",
@@ -1809,7 +1809,7 @@ static struct clk i2c3_fck = {
1809 1809
1810static struct clk i2c4_fck = { 1810static struct clk i2c4_fck = {
1811 .name = "i2c4_fck", 1811 .name = "i2c4_fck",
1812 .ops = &clkops_omap2_dflt, 1812 .ops = &clkops_omap4_dflt_wait,
1813 .enable_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL, 1813 .enable_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
1814 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1814 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1815 .clkdm_name = "l4_per_clkdm", 1815 .clkdm_name = "l4_per_clkdm",
@@ -1819,7 +1819,7 @@ static struct clk i2c4_fck = {
1819 1819
1820static struct clk ipu_fck = { 1820static struct clk ipu_fck = {
1821 .name = "ipu_fck", 1821 .name = "ipu_fck",
1822 .ops = &clkops_omap2_dflt, 1822 .ops = &clkops_omap4_dflt_wait,
1823 .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, 1823 .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
1824 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1824 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1825 .clkdm_name = "ducati_clkdm", 1825 .clkdm_name = "ducati_clkdm",
@@ -1829,7 +1829,7 @@ static struct clk ipu_fck = {
1829 1829
1830static struct clk iss_ctrlclk = { 1830static struct clk iss_ctrlclk = {
1831 .name = "iss_ctrlclk", 1831 .name = "iss_ctrlclk",
1832 .ops = &clkops_omap2_dflt, 1832 .ops = &clkops_omap4_dflt_wait,
1833 .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL, 1833 .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
1834 .enable_bit = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT, 1834 .enable_bit = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
1835 .clkdm_name = "iss_clkdm", 1835 .clkdm_name = "iss_clkdm",
@@ -1839,7 +1839,7 @@ static struct clk iss_ctrlclk = {
1839 1839
1840static struct clk iss_fck = { 1840static struct clk iss_fck = {
1841 .name = "iss_fck", 1841 .name = "iss_fck",
1842 .ops = &clkops_omap2_dflt, 1842 .ops = &clkops_omap4_dflt_wait,
1843 .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL, 1843 .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
1844 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1844 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1845 .clkdm_name = "iss_clkdm", 1845 .clkdm_name = "iss_clkdm",
@@ -1849,7 +1849,7 @@ static struct clk iss_fck = {
1849 1849
1850static struct clk iva_fck = { 1850static struct clk iva_fck = {
1851 .name = "iva_fck", 1851 .name = "iva_fck",
1852 .ops = &clkops_omap2_dflt, 1852 .ops = &clkops_omap4_dflt_wait,
1853 .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, 1853 .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
1854 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1854 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1855 .clkdm_name = "ivahd_clkdm", 1855 .clkdm_name = "ivahd_clkdm",
@@ -1859,7 +1859,7 @@ static struct clk iva_fck = {
1859 1859
1860static struct clk kbd_fck = { 1860static struct clk kbd_fck = {
1861 .name = "kbd_fck", 1861 .name = "kbd_fck",
1862 .ops = &clkops_omap2_dflt, 1862 .ops = &clkops_omap4_dflt_wait,
1863 .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, 1863 .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
1864 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1864 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1865 .clkdm_name = "l4_wkup_clkdm", 1865 .clkdm_name = "l4_wkup_clkdm",
@@ -1869,7 +1869,7 @@ static struct clk kbd_fck = {
1869 1869
1870static struct clk l3_instr_ick = { 1870static struct clk l3_instr_ick = {
1871 .name = "l3_instr_ick", 1871 .name = "l3_instr_ick",
1872 .ops = &clkops_omap2_dflt, 1872 .ops = &clkops_omap4_dflt_wait,
1873 .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, 1873 .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
1874 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1874 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1875 .clkdm_name = "l3_instr_clkdm", 1875 .clkdm_name = "l3_instr_clkdm",
@@ -1880,7 +1880,7 @@ static struct clk l3_instr_ick = {
1880 1880
1881static struct clk l3_main_3_ick = { 1881static struct clk l3_main_3_ick = {
1882 .name = "l3_main_3_ick", 1882 .name = "l3_main_3_ick",
1883 .ops = &clkops_omap2_dflt, 1883 .ops = &clkops_omap4_dflt_wait,
1884 .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, 1884 .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
1885 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1885 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1886 .clkdm_name = "l3_instr_clkdm", 1886 .clkdm_name = "l3_instr_clkdm",
@@ -1915,7 +1915,7 @@ static struct clk mcasp_fck = {
1915 .init = &omap2_init_clksel_parent, 1915 .init = &omap2_init_clksel_parent,
1916 .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL, 1916 .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1917 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, 1917 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1918 .ops = &clkops_omap2_dflt, 1918 .ops = &clkops_omap4_dflt_wait,
1919 .recalc = &omap2_clksel_recalc, 1919 .recalc = &omap2_clksel_recalc,
1920 .enable_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL, 1920 .enable_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1921 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1921 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -1948,7 +1948,7 @@ static struct clk mcbsp1_fck = {
1948 .init = &omap2_init_clksel_parent, 1948 .init = &omap2_init_clksel_parent,
1949 .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, 1949 .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1950 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, 1950 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1951 .ops = &clkops_omap2_dflt, 1951 .ops = &clkops_omap4_dflt_wait,
1952 .recalc = &omap2_clksel_recalc, 1952 .recalc = &omap2_clksel_recalc,
1953 .enable_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, 1953 .enable_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1954 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1954 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -1981,7 +1981,7 @@ static struct clk mcbsp2_fck = {
1981 .init = &omap2_init_clksel_parent, 1981 .init = &omap2_init_clksel_parent,
1982 .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, 1982 .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1983 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, 1983 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1984 .ops = &clkops_omap2_dflt, 1984 .ops = &clkops_omap4_dflt_wait,
1985 .recalc = &omap2_clksel_recalc, 1985 .recalc = &omap2_clksel_recalc,
1986 .enable_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, 1986 .enable_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1987 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1987 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2014,7 +2014,7 @@ static struct clk mcbsp3_fck = {
2014 .init = &omap2_init_clksel_parent, 2014 .init = &omap2_init_clksel_parent,
2015 .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, 2015 .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
2016 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, 2016 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
2017 .ops = &clkops_omap2_dflt, 2017 .ops = &clkops_omap4_dflt_wait,
2018 .recalc = &omap2_clksel_recalc, 2018 .recalc = &omap2_clksel_recalc,
2019 .enable_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, 2019 .enable_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
2020 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2020 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2046,7 +2046,7 @@ static struct clk mcbsp4_fck = {
2046 .init = &omap2_init_clksel_parent, 2046 .init = &omap2_init_clksel_parent,
2047 .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, 2047 .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
2048 .clksel_mask = OMAP4430_CLKSEL_SOURCE_24_24_MASK, 2048 .clksel_mask = OMAP4430_CLKSEL_SOURCE_24_24_MASK,
2049 .ops = &clkops_omap2_dflt, 2049 .ops = &clkops_omap4_dflt_wait,
2050 .recalc = &omap2_clksel_recalc, 2050 .recalc = &omap2_clksel_recalc,
2051 .enable_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, 2051 .enable_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
2052 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2052 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2055,7 +2055,7 @@ static struct clk mcbsp4_fck = {
2055 2055
2056static struct clk mcpdm_fck = { 2056static struct clk mcpdm_fck = {
2057 .name = "mcpdm_fck", 2057 .name = "mcpdm_fck",
2058 .ops = &clkops_omap2_dflt, 2058 .ops = &clkops_omap4_dflt_wait,
2059 .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL, 2059 .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
2060 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2060 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2061 .clkdm_name = "abe_clkdm", 2061 .clkdm_name = "abe_clkdm",
@@ -2065,7 +2065,7 @@ static struct clk mcpdm_fck = {
2065 2065
2066static struct clk mcspi1_fck = { 2066static struct clk mcspi1_fck = {
2067 .name = "mcspi1_fck", 2067 .name = "mcspi1_fck",
2068 .ops = &clkops_omap2_dflt, 2068 .ops = &clkops_omap4_dflt_wait,
2069 .enable_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL, 2069 .enable_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
2070 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2070 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2071 .clkdm_name = "l4_per_clkdm", 2071 .clkdm_name = "l4_per_clkdm",
@@ -2075,7 +2075,7 @@ static struct clk mcspi1_fck = {
2075 2075
2076static struct clk mcspi2_fck = { 2076static struct clk mcspi2_fck = {
2077 .name = "mcspi2_fck", 2077 .name = "mcspi2_fck",
2078 .ops = &clkops_omap2_dflt, 2078 .ops = &clkops_omap4_dflt_wait,
2079 .enable_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL, 2079 .enable_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
2080 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2080 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2081 .clkdm_name = "l4_per_clkdm", 2081 .clkdm_name = "l4_per_clkdm",
@@ -2085,7 +2085,7 @@ static struct clk mcspi2_fck = {
2085 2085
2086static struct clk mcspi3_fck = { 2086static struct clk mcspi3_fck = {
2087 .name = "mcspi3_fck", 2087 .name = "mcspi3_fck",
2088 .ops = &clkops_omap2_dflt, 2088 .ops = &clkops_omap4_dflt_wait,
2089 .enable_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL, 2089 .enable_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
2090 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2090 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2091 .clkdm_name = "l4_per_clkdm", 2091 .clkdm_name = "l4_per_clkdm",
@@ -2095,7 +2095,7 @@ static struct clk mcspi3_fck = {
2095 2095
2096static struct clk mcspi4_fck = { 2096static struct clk mcspi4_fck = {
2097 .name = "mcspi4_fck", 2097 .name = "mcspi4_fck",
2098 .ops = &clkops_omap2_dflt, 2098 .ops = &clkops_omap4_dflt_wait,
2099 .enable_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL, 2099 .enable_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
2100 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2100 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2101 .clkdm_name = "l4_per_clkdm", 2101 .clkdm_name = "l4_per_clkdm",
@@ -2111,7 +2111,7 @@ static struct clk mmc1_fck = {
2111 .init = &omap2_init_clksel_parent, 2111 .init = &omap2_init_clksel_parent,
2112 .clksel_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, 2112 .clksel_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2113 .clksel_mask = OMAP4430_CLKSEL_MASK, 2113 .clksel_mask = OMAP4430_CLKSEL_MASK,
2114 .ops = &clkops_omap2_dflt, 2114 .ops = &clkops_omap4_dflt_wait,
2115 .recalc = &omap2_clksel_recalc, 2115 .recalc = &omap2_clksel_recalc,
2116 .enable_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, 2116 .enable_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2117 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2117 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2126,7 +2126,7 @@ static struct clk mmc2_fck = {
2126 .init = &omap2_init_clksel_parent, 2126 .init = &omap2_init_clksel_parent,
2127 .clksel_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, 2127 .clksel_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2128 .clksel_mask = OMAP4430_CLKSEL_MASK, 2128 .clksel_mask = OMAP4430_CLKSEL_MASK,
2129 .ops = &clkops_omap2_dflt, 2129 .ops = &clkops_omap4_dflt_wait,
2130 .recalc = &omap2_clksel_recalc, 2130 .recalc = &omap2_clksel_recalc,
2131 .enable_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, 2131 .enable_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2132 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2132 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2135,7 +2135,7 @@ static struct clk mmc2_fck = {
2135 2135
2136static struct clk mmc3_fck = { 2136static struct clk mmc3_fck = {
2137 .name = "mmc3_fck", 2137 .name = "mmc3_fck",
2138 .ops = &clkops_omap2_dflt, 2138 .ops = &clkops_omap4_dflt_wait,
2139 .enable_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL, 2139 .enable_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
2140 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2140 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2141 .clkdm_name = "l4_per_clkdm", 2141 .clkdm_name = "l4_per_clkdm",
@@ -2145,7 +2145,7 @@ static struct clk mmc3_fck = {
2145 2145
2146static struct clk mmc4_fck = { 2146static struct clk mmc4_fck = {
2147 .name = "mmc4_fck", 2147 .name = "mmc4_fck",
2148 .ops = &clkops_omap2_dflt, 2148 .ops = &clkops_omap4_dflt_wait,
2149 .enable_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL, 2149 .enable_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
2150 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2150 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2151 .clkdm_name = "l4_per_clkdm", 2151 .clkdm_name = "l4_per_clkdm",
@@ -2155,7 +2155,7 @@ static struct clk mmc4_fck = {
2155 2155
2156static struct clk mmc5_fck = { 2156static struct clk mmc5_fck = {
2157 .name = "mmc5_fck", 2157 .name = "mmc5_fck",
2158 .ops = &clkops_omap2_dflt, 2158 .ops = &clkops_omap4_dflt_wait,
2159 .enable_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL, 2159 .enable_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
2160 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2160 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2161 .clkdm_name = "l4_per_clkdm", 2161 .clkdm_name = "l4_per_clkdm",
@@ -2165,7 +2165,7 @@ static struct clk mmc5_fck = {
2165 2165
2166static struct clk ocp2scp_usb_phy_phy_48m = { 2166static struct clk ocp2scp_usb_phy_phy_48m = {
2167 .name = "ocp2scp_usb_phy_phy_48m", 2167 .name = "ocp2scp_usb_phy_phy_48m",
2168 .ops = &clkops_omap2_dflt, 2168 .ops = &clkops_omap4_dflt_wait,
2169 .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, 2169 .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2170 .enable_bit = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 2170 .enable_bit = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT,
2171 .clkdm_name = "l3_init_clkdm", 2171 .clkdm_name = "l3_init_clkdm",
@@ -2175,7 +2175,7 @@ static struct clk ocp2scp_usb_phy_phy_48m = {
2175 2175
2176static struct clk ocp2scp_usb_phy_ick = { 2176static struct clk ocp2scp_usb_phy_ick = {
2177 .name = "ocp2scp_usb_phy_ick", 2177 .name = "ocp2scp_usb_phy_ick",
2178 .ops = &clkops_omap2_dflt, 2178 .ops = &clkops_omap4_dflt_wait,
2179 .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, 2179 .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2180 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2180 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2181 .clkdm_name = "l3_init_clkdm", 2181 .clkdm_name = "l3_init_clkdm",
@@ -2185,7 +2185,7 @@ static struct clk ocp2scp_usb_phy_ick = {
2185 2185
2186static struct clk ocp_wp_noc_ick = { 2186static struct clk ocp_wp_noc_ick = {
2187 .name = "ocp_wp_noc_ick", 2187 .name = "ocp_wp_noc_ick",
2188 .ops = &clkops_omap2_dflt, 2188 .ops = &clkops_omap4_dflt_wait,
2189 .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, 2189 .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
2190 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2190 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2191 .clkdm_name = "l3_instr_clkdm", 2191 .clkdm_name = "l3_instr_clkdm",
@@ -2196,7 +2196,7 @@ static struct clk ocp_wp_noc_ick = {
2196 2196
2197static struct clk rng_ick = { 2197static struct clk rng_ick = {
2198 .name = "rng_ick", 2198 .name = "rng_ick",
2199 .ops = &clkops_omap2_dflt, 2199 .ops = &clkops_omap4_dflt_wait,
2200 .enable_reg = OMAP4430_CM_L4SEC_RNG_CLKCTRL, 2200 .enable_reg = OMAP4430_CM_L4SEC_RNG_CLKCTRL,
2201 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2201 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2202 .clkdm_name = "l4_secure_clkdm", 2202 .clkdm_name = "l4_secure_clkdm",
@@ -2206,7 +2206,7 @@ static struct clk rng_ick = {
2206 2206
2207static struct clk sha2md5_fck = { 2207static struct clk sha2md5_fck = {
2208 .name = "sha2md5_fck", 2208 .name = "sha2md5_fck",
2209 .ops = &clkops_omap2_dflt, 2209 .ops = &clkops_omap4_dflt_wait,
2210 .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, 2210 .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
2211 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2211 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2212 .clkdm_name = "l4_secure_clkdm", 2212 .clkdm_name = "l4_secure_clkdm",
@@ -2216,7 +2216,7 @@ static struct clk sha2md5_fck = {
2216 2216
2217static struct clk sl2if_ick = { 2217static struct clk sl2if_ick = {
2218 .name = "sl2if_ick", 2218 .name = "sl2if_ick",
2219 .ops = &clkops_omap2_dflt, 2219 .ops = &clkops_omap4_dflt_wait,
2220 .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL, 2220 .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
2221 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2221 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2222 .clkdm_name = "ivahd_clkdm", 2222 .clkdm_name = "ivahd_clkdm",
@@ -2226,7 +2226,7 @@ static struct clk sl2if_ick = {
2226 2226
2227static struct clk slimbus1_fclk_1 = { 2227static struct clk slimbus1_fclk_1 = {
2228 .name = "slimbus1_fclk_1", 2228 .name = "slimbus1_fclk_1",
2229 .ops = &clkops_omap2_dflt, 2229 .ops = &clkops_omap4_dflt_wait,
2230 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, 2230 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2231 .enable_bit = OMAP4430_OPTFCLKEN_FCLK1_SHIFT, 2231 .enable_bit = OMAP4430_OPTFCLKEN_FCLK1_SHIFT,
2232 .clkdm_name = "abe_clkdm", 2232 .clkdm_name = "abe_clkdm",
@@ -2236,7 +2236,7 @@ static struct clk slimbus1_fclk_1 = {
2236 2236
2237static struct clk slimbus1_fclk_0 = { 2237static struct clk slimbus1_fclk_0 = {
2238 .name = "slimbus1_fclk_0", 2238 .name = "slimbus1_fclk_0",
2239 .ops = &clkops_omap2_dflt, 2239 .ops = &clkops_omap4_dflt_wait,
2240 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, 2240 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2241 .enable_bit = OMAP4430_OPTFCLKEN_FCLK0_SHIFT, 2241 .enable_bit = OMAP4430_OPTFCLKEN_FCLK0_SHIFT,
2242 .clkdm_name = "abe_clkdm", 2242 .clkdm_name = "abe_clkdm",
@@ -2246,7 +2246,7 @@ static struct clk slimbus1_fclk_0 = {
2246 2246
2247static struct clk slimbus1_fclk_2 = { 2247static struct clk slimbus1_fclk_2 = {
2248 .name = "slimbus1_fclk_2", 2248 .name = "slimbus1_fclk_2",
2249 .ops = &clkops_omap2_dflt, 2249 .ops = &clkops_omap4_dflt_wait,
2250 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, 2250 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2251 .enable_bit = OMAP4430_OPTFCLKEN_FCLK2_SHIFT, 2251 .enable_bit = OMAP4430_OPTFCLKEN_FCLK2_SHIFT,
2252 .clkdm_name = "abe_clkdm", 2252 .clkdm_name = "abe_clkdm",
@@ -2256,7 +2256,7 @@ static struct clk slimbus1_fclk_2 = {
2256 2256
2257static struct clk slimbus1_slimbus_clk = { 2257static struct clk slimbus1_slimbus_clk = {
2258 .name = "slimbus1_slimbus_clk", 2258 .name = "slimbus1_slimbus_clk",
2259 .ops = &clkops_omap2_dflt, 2259 .ops = &clkops_omap4_dflt_wait,
2260 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, 2260 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2261 .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, 2261 .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT,
2262 .clkdm_name = "abe_clkdm", 2262 .clkdm_name = "abe_clkdm",
@@ -2266,7 +2266,7 @@ static struct clk slimbus1_slimbus_clk = {
2266 2266
2267static struct clk slimbus1_fck = { 2267static struct clk slimbus1_fck = {
2268 .name = "slimbus1_fck", 2268 .name = "slimbus1_fck",
2269 .ops = &clkops_omap2_dflt, 2269 .ops = &clkops_omap4_dflt_wait,
2270 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, 2270 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2271 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2271 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2272 .clkdm_name = "abe_clkdm", 2272 .clkdm_name = "abe_clkdm",
@@ -2276,7 +2276,7 @@ static struct clk slimbus1_fck = {
2276 2276
2277static struct clk slimbus2_fclk_1 = { 2277static struct clk slimbus2_fclk_1 = {
2278 .name = "slimbus2_fclk_1", 2278 .name = "slimbus2_fclk_1",
2279 .ops = &clkops_omap2_dflt, 2279 .ops = &clkops_omap4_dflt_wait,
2280 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, 2280 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2281 .enable_bit = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, 2281 .enable_bit = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT,
2282 .clkdm_name = "l4_per_clkdm", 2282 .clkdm_name = "l4_per_clkdm",
@@ -2286,7 +2286,7 @@ static struct clk slimbus2_fclk_1 = {
2286 2286
2287static struct clk slimbus2_fclk_0 = { 2287static struct clk slimbus2_fclk_0 = {
2288 .name = "slimbus2_fclk_0", 2288 .name = "slimbus2_fclk_0",
2289 .ops = &clkops_omap2_dflt, 2289 .ops = &clkops_omap4_dflt_wait,
2290 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, 2290 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2291 .enable_bit = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT, 2291 .enable_bit = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT,
2292 .clkdm_name = "l4_per_clkdm", 2292 .clkdm_name = "l4_per_clkdm",
@@ -2296,7 +2296,7 @@ static struct clk slimbus2_fclk_0 = {
2296 2296
2297static struct clk slimbus2_slimbus_clk = { 2297static struct clk slimbus2_slimbus_clk = {
2298 .name = "slimbus2_slimbus_clk", 2298 .name = "slimbus2_slimbus_clk",
2299 .ops = &clkops_omap2_dflt, 2299 .ops = &clkops_omap4_dflt_wait,
2300 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, 2300 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2301 .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, 2301 .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT,
2302 .clkdm_name = "l4_per_clkdm", 2302 .clkdm_name = "l4_per_clkdm",
@@ -2306,7 +2306,7 @@ static struct clk slimbus2_slimbus_clk = {
2306 2306
2307static struct clk slimbus2_fck = { 2307static struct clk slimbus2_fck = {
2308 .name = "slimbus2_fck", 2308 .name = "slimbus2_fck",
2309 .ops = &clkops_omap2_dflt, 2309 .ops = &clkops_omap4_dflt_wait,
2310 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, 2310 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2311 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2311 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2312 .clkdm_name = "l4_per_clkdm", 2312 .clkdm_name = "l4_per_clkdm",
@@ -2316,7 +2316,7 @@ static struct clk slimbus2_fck = {
2316 2316
2317static struct clk smartreflex_core_fck = { 2317static struct clk smartreflex_core_fck = {
2318 .name = "smartreflex_core_fck", 2318 .name = "smartreflex_core_fck",
2319 .ops = &clkops_omap2_dflt, 2319 .ops = &clkops_omap4_dflt_wait,
2320 .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, 2320 .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
2321 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2321 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2322 .clkdm_name = "l4_ao_clkdm", 2322 .clkdm_name = "l4_ao_clkdm",
@@ -2326,7 +2326,7 @@ static struct clk smartreflex_core_fck = {
2326 2326
2327static struct clk smartreflex_iva_fck = { 2327static struct clk smartreflex_iva_fck = {
2328 .name = "smartreflex_iva_fck", 2328 .name = "smartreflex_iva_fck",
2329 .ops = &clkops_omap2_dflt, 2329 .ops = &clkops_omap4_dflt_wait,
2330 .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, 2330 .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
2331 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2331 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2332 .clkdm_name = "l4_ao_clkdm", 2332 .clkdm_name = "l4_ao_clkdm",
@@ -2336,7 +2336,7 @@ static struct clk smartreflex_iva_fck = {
2336 2336
2337static struct clk smartreflex_mpu_fck = { 2337static struct clk smartreflex_mpu_fck = {
2338 .name = "smartreflex_mpu_fck", 2338 .name = "smartreflex_mpu_fck",
2339 .ops = &clkops_omap2_dflt, 2339 .ops = &clkops_omap4_dflt_wait,
2340 .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, 2340 .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
2341 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2341 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2342 .clkdm_name = "l4_ao_clkdm", 2342 .clkdm_name = "l4_ao_clkdm",
@@ -2352,7 +2352,7 @@ static struct clk timer1_fck = {
2352 .init = &omap2_init_clksel_parent, 2352 .init = &omap2_init_clksel_parent,
2353 .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, 2353 .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2354 .clksel_mask = OMAP4430_CLKSEL_MASK, 2354 .clksel_mask = OMAP4430_CLKSEL_MASK,
2355 .ops = &clkops_omap2_dflt, 2355 .ops = &clkops_omap4_dflt_wait,
2356 .recalc = &omap2_clksel_recalc, 2356 .recalc = &omap2_clksel_recalc,
2357 .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, 2357 .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2358 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2358 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2367,7 +2367,7 @@ static struct clk timer10_fck = {
2367 .init = &omap2_init_clksel_parent, 2367 .init = &omap2_init_clksel_parent,
2368 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, 2368 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2369 .clksel_mask = OMAP4430_CLKSEL_MASK, 2369 .clksel_mask = OMAP4430_CLKSEL_MASK,
2370 .ops = &clkops_omap2_dflt, 2370 .ops = &clkops_omap4_dflt_wait,
2371 .recalc = &omap2_clksel_recalc, 2371 .recalc = &omap2_clksel_recalc,
2372 .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, 2372 .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2373 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2373 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2382,7 +2382,7 @@ static struct clk timer11_fck = {
2382 .init = &omap2_init_clksel_parent, 2382 .init = &omap2_init_clksel_parent,
2383 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, 2383 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2384 .clksel_mask = OMAP4430_CLKSEL_MASK, 2384 .clksel_mask = OMAP4430_CLKSEL_MASK,
2385 .ops = &clkops_omap2_dflt, 2385 .ops = &clkops_omap4_dflt_wait,
2386 .recalc = &omap2_clksel_recalc, 2386 .recalc = &omap2_clksel_recalc,
2387 .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, 2387 .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2388 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2388 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2397,7 +2397,7 @@ static struct clk timer2_fck = {
2397 .init = &omap2_init_clksel_parent, 2397 .init = &omap2_init_clksel_parent,
2398 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, 2398 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2399 .clksel_mask = OMAP4430_CLKSEL_MASK, 2399 .clksel_mask = OMAP4430_CLKSEL_MASK,
2400 .ops = &clkops_omap2_dflt, 2400 .ops = &clkops_omap4_dflt_wait,
2401 .recalc = &omap2_clksel_recalc, 2401 .recalc = &omap2_clksel_recalc,
2402 .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, 2402 .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2403 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2403 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2412,7 +2412,7 @@ static struct clk timer3_fck = {
2412 .init = &omap2_init_clksel_parent, 2412 .init = &omap2_init_clksel_parent,
2413 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, 2413 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2414 .clksel_mask = OMAP4430_CLKSEL_MASK, 2414 .clksel_mask = OMAP4430_CLKSEL_MASK,
2415 .ops = &clkops_omap2_dflt, 2415 .ops = &clkops_omap4_dflt_wait,
2416 .recalc = &omap2_clksel_recalc, 2416 .recalc = &omap2_clksel_recalc,
2417 .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, 2417 .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2418 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2418 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2427,7 +2427,7 @@ static struct clk timer4_fck = {
2427 .init = &omap2_init_clksel_parent, 2427 .init = &omap2_init_clksel_parent,
2428 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, 2428 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2429 .clksel_mask = OMAP4430_CLKSEL_MASK, 2429 .clksel_mask = OMAP4430_CLKSEL_MASK,
2430 .ops = &clkops_omap2_dflt, 2430 .ops = &clkops_omap4_dflt_wait,
2431 .recalc = &omap2_clksel_recalc, 2431 .recalc = &omap2_clksel_recalc,
2432 .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, 2432 .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2433 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2433 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2448,7 +2448,7 @@ static struct clk timer5_fck = {
2448 .init = &omap2_init_clksel_parent, 2448 .init = &omap2_init_clksel_parent,
2449 .clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, 2449 .clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2450 .clksel_mask = OMAP4430_CLKSEL_MASK, 2450 .clksel_mask = OMAP4430_CLKSEL_MASK,
2451 .ops = &clkops_omap2_dflt, 2451 .ops = &clkops_omap4_dflt_wait,
2452 .recalc = &omap2_clksel_recalc, 2452 .recalc = &omap2_clksel_recalc,
2453 .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, 2453 .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2454 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2454 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2463,7 +2463,7 @@ static struct clk timer6_fck = {
2463 .init = &omap2_init_clksel_parent, 2463 .init = &omap2_init_clksel_parent,
2464 .clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, 2464 .clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2465 .clksel_mask = OMAP4430_CLKSEL_MASK, 2465 .clksel_mask = OMAP4430_CLKSEL_MASK,
2466 .ops = &clkops_omap2_dflt, 2466 .ops = &clkops_omap4_dflt_wait,
2467 .recalc = &omap2_clksel_recalc, 2467 .recalc = &omap2_clksel_recalc,
2468 .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, 2468 .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2469 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2469 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2478,7 +2478,7 @@ static struct clk timer7_fck = {
2478 .init = &omap2_init_clksel_parent, 2478 .init = &omap2_init_clksel_parent,
2479 .clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, 2479 .clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2480 .clksel_mask = OMAP4430_CLKSEL_MASK, 2480 .clksel_mask = OMAP4430_CLKSEL_MASK,
2481 .ops = &clkops_omap2_dflt, 2481 .ops = &clkops_omap4_dflt_wait,
2482 .recalc = &omap2_clksel_recalc, 2482 .recalc = &omap2_clksel_recalc,
2483 .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, 2483 .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2484 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2484 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2493,7 +2493,7 @@ static struct clk timer8_fck = {
2493 .init = &omap2_init_clksel_parent, 2493 .init = &omap2_init_clksel_parent,
2494 .clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, 2494 .clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2495 .clksel_mask = OMAP4430_CLKSEL_MASK, 2495 .clksel_mask = OMAP4430_CLKSEL_MASK,
2496 .ops = &clkops_omap2_dflt, 2496 .ops = &clkops_omap4_dflt_wait,
2497 .recalc = &omap2_clksel_recalc, 2497 .recalc = &omap2_clksel_recalc,
2498 .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, 2498 .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2499 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2499 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2508,7 +2508,7 @@ static struct clk timer9_fck = {
2508 .init = &omap2_init_clksel_parent, 2508 .init = &omap2_init_clksel_parent,
2509 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, 2509 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2510 .clksel_mask = OMAP4430_CLKSEL_MASK, 2510 .clksel_mask = OMAP4430_CLKSEL_MASK,
2511 .ops = &clkops_omap2_dflt, 2511 .ops = &clkops_omap4_dflt_wait,
2512 .recalc = &omap2_clksel_recalc, 2512 .recalc = &omap2_clksel_recalc,
2513 .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, 2513 .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2514 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2514 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2517,7 +2517,7 @@ static struct clk timer9_fck = {
2517 2517
2518static struct clk uart1_fck = { 2518static struct clk uart1_fck = {
2519 .name = "uart1_fck", 2519 .name = "uart1_fck",
2520 .ops = &clkops_omap2_dflt, 2520 .ops = &clkops_omap4_dflt_wait,
2521 .enable_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL, 2521 .enable_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
2522 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2522 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2523 .clkdm_name = "l4_per_clkdm", 2523 .clkdm_name = "l4_per_clkdm",
@@ -2527,7 +2527,7 @@ static struct clk uart1_fck = {
2527 2527
2528static struct clk uart2_fck = { 2528static struct clk uart2_fck = {
2529 .name = "uart2_fck", 2529 .name = "uart2_fck",
2530 .ops = &clkops_omap2_dflt, 2530 .ops = &clkops_omap4_dflt_wait,
2531 .enable_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL, 2531 .enable_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
2532 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2532 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2533 .clkdm_name = "l4_per_clkdm", 2533 .clkdm_name = "l4_per_clkdm",
@@ -2537,7 +2537,7 @@ static struct clk uart2_fck = {
2537 2537
2538static struct clk uart3_fck = { 2538static struct clk uart3_fck = {
2539 .name = "uart3_fck", 2539 .name = "uart3_fck",
2540 .ops = &clkops_omap2_dflt, 2540 .ops = &clkops_omap4_dflt_wait,
2541 .enable_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL, 2541 .enable_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
2542 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2542 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2543 .clkdm_name = "l4_per_clkdm", 2543 .clkdm_name = "l4_per_clkdm",
@@ -2547,7 +2547,7 @@ static struct clk uart3_fck = {
2547 2547
2548static struct clk uart4_fck = { 2548static struct clk uart4_fck = {
2549 .name = "uart4_fck", 2549 .name = "uart4_fck",
2550 .ops = &clkops_omap2_dflt, 2550 .ops = &clkops_omap4_dflt_wait,
2551 .enable_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL, 2551 .enable_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
2552 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2552 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2553 .clkdm_name = "l4_per_clkdm", 2553 .clkdm_name = "l4_per_clkdm",
@@ -2557,7 +2557,7 @@ static struct clk uart4_fck = {
2557 2557
2558static struct clk usb_host_fs_fck = { 2558static struct clk usb_host_fs_fck = {
2559 .name = "usb_host_fs_fck", 2559 .name = "usb_host_fs_fck",
2560 .ops = &clkops_omap2_dflt, 2560 .ops = &clkops_omap4_dflt_wait,
2561 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL, 2561 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
2562 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2562 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2563 .clkdm_name = "l3_init_clkdm", 2563 .clkdm_name = "l3_init_clkdm",
@@ -2584,7 +2584,7 @@ static struct clk utmi_p1_gfclk = {
2584 2584
2585static struct clk usb_host_hs_utmi_p1_clk = { 2585static struct clk usb_host_hs_utmi_p1_clk = {
2586 .name = "usb_host_hs_utmi_p1_clk", 2586 .name = "usb_host_hs_utmi_p1_clk",
2587 .ops = &clkops_omap2_dflt, 2587 .ops = &clkops_omap4_dflt_wait,
2588 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, 2588 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2589 .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT, 2589 .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT,
2590 .clkdm_name = "l3_init_clkdm", 2590 .clkdm_name = "l3_init_clkdm",
@@ -2611,7 +2611,7 @@ static struct clk utmi_p2_gfclk = {
2611 2611
2612static struct clk usb_host_hs_utmi_p2_clk = { 2612static struct clk usb_host_hs_utmi_p2_clk = {
2613 .name = "usb_host_hs_utmi_p2_clk", 2613 .name = "usb_host_hs_utmi_p2_clk",
2614 .ops = &clkops_omap2_dflt, 2614 .ops = &clkops_omap4_dflt_wait,
2615 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, 2615 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2616 .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT, 2616 .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT,
2617 .clkdm_name = "l3_init_clkdm", 2617 .clkdm_name = "l3_init_clkdm",
@@ -2621,7 +2621,7 @@ static struct clk usb_host_hs_utmi_p2_clk = {
2621 2621
2622static struct clk usb_host_hs_utmi_p3_clk = { 2622static struct clk usb_host_hs_utmi_p3_clk = {
2623 .name = "usb_host_hs_utmi_p3_clk", 2623 .name = "usb_host_hs_utmi_p3_clk",
2624 .ops = &clkops_omap2_dflt, 2624 .ops = &clkops_omap4_dflt_wait,
2625 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, 2625 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2626 .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, 2626 .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
2627 .clkdm_name = "l3_init_clkdm", 2627 .clkdm_name = "l3_init_clkdm",
@@ -2631,7 +2631,7 @@ static struct clk usb_host_hs_utmi_p3_clk = {
2631 2631
2632static struct clk usb_host_hs_hsic480m_p1_clk = { 2632static struct clk usb_host_hs_hsic480m_p1_clk = {
2633 .name = "usb_host_hs_hsic480m_p1_clk", 2633 .name = "usb_host_hs_hsic480m_p1_clk",
2634 .ops = &clkops_omap2_dflt, 2634 .ops = &clkops_omap4_dflt_wait,
2635 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, 2635 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2636 .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, 2636 .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT,
2637 .clkdm_name = "l3_init_clkdm", 2637 .clkdm_name = "l3_init_clkdm",
@@ -2641,7 +2641,7 @@ static struct clk usb_host_hs_hsic480m_p1_clk = {
2641 2641
2642static struct clk usb_host_hs_hsic60m_p1_clk = { 2642static struct clk usb_host_hs_hsic60m_p1_clk = {
2643 .name = "usb_host_hs_hsic60m_p1_clk", 2643 .name = "usb_host_hs_hsic60m_p1_clk",
2644 .ops = &clkops_omap2_dflt, 2644 .ops = &clkops_omap4_dflt_wait,
2645 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, 2645 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2646 .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, 2646 .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
2647 .clkdm_name = "l3_init_clkdm", 2647 .clkdm_name = "l3_init_clkdm",
@@ -2651,7 +2651,7 @@ static struct clk usb_host_hs_hsic60m_p1_clk = {
2651 2651
2652static struct clk usb_host_hs_hsic60m_p2_clk = { 2652static struct clk usb_host_hs_hsic60m_p2_clk = {
2653 .name = "usb_host_hs_hsic60m_p2_clk", 2653 .name = "usb_host_hs_hsic60m_p2_clk",
2654 .ops = &clkops_omap2_dflt, 2654 .ops = &clkops_omap4_dflt_wait,
2655 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, 2655 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2656 .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, 2656 .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
2657 .clkdm_name = "l3_init_clkdm", 2657 .clkdm_name = "l3_init_clkdm",
@@ -2661,7 +2661,7 @@ static struct clk usb_host_hs_hsic60m_p2_clk = {
2661 2661
2662static struct clk usb_host_hs_hsic480m_p2_clk = { 2662static struct clk usb_host_hs_hsic480m_p2_clk = {
2663 .name = "usb_host_hs_hsic480m_p2_clk", 2663 .name = "usb_host_hs_hsic480m_p2_clk",
2664 .ops = &clkops_omap2_dflt, 2664 .ops = &clkops_omap4_dflt_wait,
2665 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, 2665 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2666 .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, 2666 .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT,
2667 .clkdm_name = "l3_init_clkdm", 2667 .clkdm_name = "l3_init_clkdm",
@@ -2671,7 +2671,7 @@ static struct clk usb_host_hs_hsic480m_p2_clk = {
2671 2671
2672static struct clk usb_host_hs_func48mclk = { 2672static struct clk usb_host_hs_func48mclk = {
2673 .name = "usb_host_hs_func48mclk", 2673 .name = "usb_host_hs_func48mclk",
2674 .ops = &clkops_omap2_dflt, 2674 .ops = &clkops_omap4_dflt_wait,
2675 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, 2675 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2676 .enable_bit = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT, 2676 .enable_bit = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT,
2677 .clkdm_name = "l3_init_clkdm", 2677 .clkdm_name = "l3_init_clkdm",
@@ -2681,7 +2681,7 @@ static struct clk usb_host_hs_func48mclk = {
2681 2681
2682static struct clk usb_host_hs_fck = { 2682static struct clk usb_host_hs_fck = {
2683 .name = "usb_host_hs_fck", 2683 .name = "usb_host_hs_fck",
2684 .ops = &clkops_omap2_dflt, 2684 .ops = &clkops_omap4_dflt_wait,
2685 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, 2685 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2686 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2686 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2687 .clkdm_name = "l3_init_clkdm", 2687 .clkdm_name = "l3_init_clkdm",
@@ -2708,7 +2708,7 @@ static struct clk otg_60m_gfclk = {
2708 2708
2709static struct clk usb_otg_hs_xclk = { 2709static struct clk usb_otg_hs_xclk = {
2710 .name = "usb_otg_hs_xclk", 2710 .name = "usb_otg_hs_xclk",
2711 .ops = &clkops_omap2_dflt, 2711 .ops = &clkops_omap4_dflt_wait,
2712 .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, 2712 .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2713 .enable_bit = OMAP4430_OPTFCLKEN_XCLK_SHIFT, 2713 .enable_bit = OMAP4430_OPTFCLKEN_XCLK_SHIFT,
2714 .clkdm_name = "l3_init_clkdm", 2714 .clkdm_name = "l3_init_clkdm",
@@ -2718,7 +2718,7 @@ static struct clk usb_otg_hs_xclk = {
2718 2718
2719static struct clk usb_otg_hs_ick = { 2719static struct clk usb_otg_hs_ick = {
2720 .name = "usb_otg_hs_ick", 2720 .name = "usb_otg_hs_ick",
2721 .ops = &clkops_omap2_dflt, 2721 .ops = &clkops_omap4_dflt_wait,
2722 .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, 2722 .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2723 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2723 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2724 .clkdm_name = "l3_init_clkdm", 2724 .clkdm_name = "l3_init_clkdm",
@@ -2728,7 +2728,7 @@ static struct clk usb_otg_hs_ick = {
2728 2728
2729static struct clk usb_phy_cm_clk32k = { 2729static struct clk usb_phy_cm_clk32k = {
2730 .name = "usb_phy_cm_clk32k", 2730 .name = "usb_phy_cm_clk32k",
2731 .ops = &clkops_omap2_dflt, 2731 .ops = &clkops_omap4_dflt_wait,
2732 .enable_reg = OMAP4430_CM_ALWON_USBPHY_CLKCTRL, 2732 .enable_reg = OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
2733 .enable_bit = OMAP4430_OPTFCLKEN_CLK32K_SHIFT, 2733 .enable_bit = OMAP4430_OPTFCLKEN_CLK32K_SHIFT,
2734 .clkdm_name = "l4_ao_clkdm", 2734 .clkdm_name = "l4_ao_clkdm",
@@ -2738,7 +2738,7 @@ static struct clk usb_phy_cm_clk32k = {
2738 2738
2739static struct clk usb_tll_hs_usb_ch2_clk = { 2739static struct clk usb_tll_hs_usb_ch2_clk = {
2740 .name = "usb_tll_hs_usb_ch2_clk", 2740 .name = "usb_tll_hs_usb_ch2_clk",
2741 .ops = &clkops_omap2_dflt, 2741 .ops = &clkops_omap4_dflt_wait,
2742 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, 2742 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2743 .enable_bit = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT, 2743 .enable_bit = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT,
2744 .clkdm_name = "l3_init_clkdm", 2744 .clkdm_name = "l3_init_clkdm",
@@ -2748,7 +2748,7 @@ static struct clk usb_tll_hs_usb_ch2_clk = {
2748 2748
2749static struct clk usb_tll_hs_usb_ch0_clk = { 2749static struct clk usb_tll_hs_usb_ch0_clk = {
2750 .name = "usb_tll_hs_usb_ch0_clk", 2750 .name = "usb_tll_hs_usb_ch0_clk",
2751 .ops = &clkops_omap2_dflt, 2751 .ops = &clkops_omap4_dflt_wait,
2752 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, 2752 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2753 .enable_bit = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT, 2753 .enable_bit = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT,
2754 .clkdm_name = "l3_init_clkdm", 2754 .clkdm_name = "l3_init_clkdm",
@@ -2758,7 +2758,7 @@ static struct clk usb_tll_hs_usb_ch0_clk = {
2758 2758
2759static struct clk usb_tll_hs_usb_ch1_clk = { 2759static struct clk usb_tll_hs_usb_ch1_clk = {
2760 .name = "usb_tll_hs_usb_ch1_clk", 2760 .name = "usb_tll_hs_usb_ch1_clk",
2761 .ops = &clkops_omap2_dflt, 2761 .ops = &clkops_omap4_dflt_wait,
2762 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, 2762 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2763 .enable_bit = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT, 2763 .enable_bit = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT,
2764 .clkdm_name = "l3_init_clkdm", 2764 .clkdm_name = "l3_init_clkdm",
@@ -2768,7 +2768,7 @@ static struct clk usb_tll_hs_usb_ch1_clk = {
2768 2768
2769static struct clk usb_tll_hs_ick = { 2769static struct clk usb_tll_hs_ick = {
2770 .name = "usb_tll_hs_ick", 2770 .name = "usb_tll_hs_ick",
2771 .ops = &clkops_omap2_dflt, 2771 .ops = &clkops_omap4_dflt_wait,
2772 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, 2772 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2773 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2773 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2774 .clkdm_name = "l3_init_clkdm", 2774 .clkdm_name = "l3_init_clkdm",
@@ -2801,7 +2801,7 @@ static struct clk usim_ck = {
2801 2801
2802static struct clk usim_fclk = { 2802static struct clk usim_fclk = {
2803 .name = "usim_fclk", 2803 .name = "usim_fclk",
2804 .ops = &clkops_omap2_dflt, 2804 .ops = &clkops_omap4_dflt_wait,
2805 .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, 2805 .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2806 .enable_bit = OMAP4430_OPTFCLKEN_FCLK_SHIFT, 2806 .enable_bit = OMAP4430_OPTFCLKEN_FCLK_SHIFT,
2807 .clkdm_name = "l4_wkup_clkdm", 2807 .clkdm_name = "l4_wkup_clkdm",
@@ -2811,7 +2811,7 @@ static struct clk usim_fclk = {
2811 2811
2812static struct clk usim_fck = { 2812static struct clk usim_fck = {
2813 .name = "usim_fck", 2813 .name = "usim_fck",
2814 .ops = &clkops_omap2_dflt, 2814 .ops = &clkops_omap4_dflt_wait,
2815 .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, 2815 .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2816 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2816 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2817 .clkdm_name = "l4_wkup_clkdm", 2817 .clkdm_name = "l4_wkup_clkdm",
@@ -2821,7 +2821,7 @@ static struct clk usim_fck = {
2821 2821
2822static struct clk wd_timer2_fck = { 2822static struct clk wd_timer2_fck = {
2823 .name = "wd_timer2_fck", 2823 .name = "wd_timer2_fck",
2824 .ops = &clkops_omap2_dflt, 2824 .ops = &clkops_omap4_dflt_wait,
2825 .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, 2825 .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
2826 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2826 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2827 .clkdm_name = "l4_wkup_clkdm", 2827 .clkdm_name = "l4_wkup_clkdm",
@@ -2831,7 +2831,7 @@ static struct clk wd_timer2_fck = {
2831 2831
2832static struct clk wd_timer3_fck = { 2832static struct clk wd_timer3_fck = {
2833 .name = "wd_timer3_fck", 2833 .name = "wd_timer3_fck",
2834 .ops = &clkops_omap2_dflt, 2834 .ops = &clkops_omap4_dflt_wait,
2835 .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, 2835 .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
2836 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2836 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2837 .clkdm_name = "abe_clkdm", 2837 .clkdm_name = "abe_clkdm",
@@ -2887,7 +2887,7 @@ static struct clk auxclk0_ck = {
2887 .name = "auxclk0_ck", 2887 .name = "auxclk0_ck",
2888 .parent = &sys_clkin_ck, 2888 .parent = &sys_clkin_ck,
2889 .init = &omap2_init_clksel_parent, 2889 .init = &omap2_init_clksel_parent,
2890 .ops = &clkops_omap2_dflt, 2890 .ops = &clkops_omap4_dflt_wait,
2891 .clksel = auxclk_sel, 2891 .clksel = auxclk_sel,
2892 .clksel_reg = OMAP4_SCRM_AUXCLK0, 2892 .clksel_reg = OMAP4_SCRM_AUXCLK0,
2893 .clksel_mask = OMAP4_SRCSELECT_MASK, 2893 .clksel_mask = OMAP4_SRCSELECT_MASK,
@@ -2900,7 +2900,7 @@ static struct clk auxclk1_ck = {
2900 .name = "auxclk1_ck", 2900 .name = "auxclk1_ck",
2901 .parent = &sys_clkin_ck, 2901 .parent = &sys_clkin_ck,
2902 .init = &omap2_init_clksel_parent, 2902 .init = &omap2_init_clksel_parent,
2903 .ops = &clkops_omap2_dflt, 2903 .ops = &clkops_omap4_dflt_wait,
2904 .clksel = auxclk_sel, 2904 .clksel = auxclk_sel,
2905 .clksel_reg = OMAP4_SCRM_AUXCLK1, 2905 .clksel_reg = OMAP4_SCRM_AUXCLK1,
2906 .clksel_mask = OMAP4_SRCSELECT_MASK, 2906 .clksel_mask = OMAP4_SRCSELECT_MASK,
@@ -2913,7 +2913,7 @@ static struct clk auxclk2_ck = {
2913 .name = "auxclk2_ck", 2913 .name = "auxclk2_ck",
2914 .parent = &sys_clkin_ck, 2914 .parent = &sys_clkin_ck,
2915 .init = &omap2_init_clksel_parent, 2915 .init = &omap2_init_clksel_parent,
2916 .ops = &clkops_omap2_dflt, 2916 .ops = &clkops_omap4_dflt_wait,
2917 .clksel = auxclk_sel, 2917 .clksel = auxclk_sel,
2918 .clksel_reg = OMAP4_SCRM_AUXCLK2, 2918 .clksel_reg = OMAP4_SCRM_AUXCLK2,
2919 .clksel_mask = OMAP4_SRCSELECT_MASK, 2919 .clksel_mask = OMAP4_SRCSELECT_MASK,
@@ -2925,7 +2925,7 @@ static struct clk auxclk3_ck = {
2925 .name = "auxclk3_ck", 2925 .name = "auxclk3_ck",
2926 .parent = &sys_clkin_ck, 2926 .parent = &sys_clkin_ck,
2927 .init = &omap2_init_clksel_parent, 2927 .init = &omap2_init_clksel_parent,
2928 .ops = &clkops_omap2_dflt, 2928 .ops = &clkops_omap4_dflt_wait,
2929 .clksel = auxclk_sel, 2929 .clksel = auxclk_sel,
2930 .clksel_reg = OMAP4_SCRM_AUXCLK3, 2930 .clksel_reg = OMAP4_SCRM_AUXCLK3,
2931 .clksel_mask = OMAP4_SRCSELECT_MASK, 2931 .clksel_mask = OMAP4_SRCSELECT_MASK,
@@ -2938,7 +2938,7 @@ static struct clk auxclk4_ck = {
2938 .name = "auxclk4_ck", 2938 .name = "auxclk4_ck",
2939 .parent = &sys_clkin_ck, 2939 .parent = &sys_clkin_ck,
2940 .init = &omap2_init_clksel_parent, 2940 .init = &omap2_init_clksel_parent,
2941 .ops = &clkops_omap2_dflt, 2941 .ops = &clkops_omap4_dflt_wait,
2942 .clksel = auxclk_sel, 2942 .clksel = auxclk_sel,
2943 .clksel_reg = OMAP4_SCRM_AUXCLK4, 2943 .clksel_reg = OMAP4_SCRM_AUXCLK4,
2944 .clksel_mask = OMAP4_SRCSELECT_MASK, 2944 .clksel_mask = OMAP4_SRCSELECT_MASK,
@@ -2951,7 +2951,7 @@ static struct clk auxclk5_ck = {
2951 .name = "auxclk5_ck", 2951 .name = "auxclk5_ck",
2952 .parent = &sys_clkin_ck, 2952 .parent = &sys_clkin_ck,
2953 .init = &omap2_init_clksel_parent, 2953 .init = &omap2_init_clksel_parent,
2954 .ops = &clkops_omap2_dflt, 2954 .ops = &clkops_omap4_dflt_wait,
2955 .clksel = auxclk_sel, 2955 .clksel = auxclk_sel,
2956 .clksel_reg = OMAP4_SCRM_AUXCLK5, 2956 .clksel_reg = OMAP4_SCRM_AUXCLK5,
2957 .clksel_mask = OMAP4_SRCSELECT_MASK, 2957 .clksel_mask = OMAP4_SRCSELECT_MASK,
@@ -3036,6 +3036,14 @@ static struct clk auxclkreq5_ck = {
3036 .recalc = &omap2_clksel_recalc, 3036 .recalc = &omap2_clksel_recalc,
3037}; 3037};
3038 3038
3039static struct clk smp_twd = {
3040 .name = "smp_twd",
3041 .parent = &dpll_mpu_ck,
3042 .ops = &clkops_null,
3043 .fixed_div = 2,
3044 .recalc = &omap_fixed_divisor_recalc,
3045};
3046
3039/* 3047/*
3040 * clkdev 3048 * clkdev
3041 */ 3049 */
@@ -3312,6 +3320,7 @@ static struct omap_clk omap44xx_clks[] = {
3312 CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_44XX), 3320 CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_44XX),
3313 CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_44XX), 3321 CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_44XX),
3314 CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_44XX), 3322 CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_44XX),
3323 CLK(NULL, "smp_twd", &smp_twd, CK_44XX),
3315}; 3324};
3316 3325
3317int __init omap4xxx_clk_init(void) 3326int __init omap4xxx_clk_init(void)
@@ -3320,7 +3329,7 @@ int __init omap4xxx_clk_init(void)
3320 u32 cpu_clkflg = 0; 3329 u32 cpu_clkflg = 0;
3321 3330
3322 if (cpu_is_omap443x()) { 3331 if (cpu_is_omap443x()) {
3323 cpu_mask = RATE_IN_4430; 3332 cpu_mask = RATE_IN_443X;
3324 cpu_clkflg = CK_443X; 3333 cpu_clkflg = CK_443X;
3325 } else if (cpu_is_omap446x()) { 3334 } else if (cpu_is_omap446x()) {
3326 cpu_mask = RATE_IN_446X; 3335 cpu_mask = RATE_IN_446X;
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 6cb6c03293d..0e9aa162754 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -825,7 +825,12 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
825 if (!arch_clkdm || !arch_clkdm->clkdm_clk_enable) 825 if (!arch_clkdm || !arch_clkdm->clkdm_clk_enable)
826 return -EINVAL; 826 return -EINVAL;
827 827
828 if (atomic_inc_return(&clkdm->usecount) > 1) 828 /*
829 * For arch's with no autodeps, clkcm_clk_enable
830 * should be called for every clock instance that is
831 * enabled, so the clkdm can be force woken up.
832 */
833 if ((atomic_inc_return(&clkdm->usecount) > 1) && autodeps)
829 return 0; 834 return 0;
830 835
831 /* Clockdomain now has one enabled downstream clock */ 836 /* Clockdomain now has one enabled downstream clock */
diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c
index a1a4ecd2654..017fb14b302 100644
--- a/arch/arm/mach-omap2/clockdomain44xx.c
+++ b/arch/arm/mach-omap2/clockdomain44xx.c
@@ -97,11 +97,8 @@ static int omap4_clkdm_clk_enable(struct clockdomain *clkdm)
97{ 97{
98 bool hwsup = false; 98 bool hwsup = false;
99 99
100 hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition, 100 /* For every clock enable, force wakeup the clkdm */
101 clkdm->cm_inst, clkdm->clkdm_offs); 101 clkdm_wakeup(clkdm);
102
103 if (!hwsup)
104 clkdm_wakeup(clkdm);
105 102
106 return 0; 103 return 0;
107} 104}
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 66868c5d5a2..af991ff850c 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -344,6 +344,13 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
344 if (c->vcc_aux_disable_is_sleep) 344 if (c->vcc_aux_disable_is_sleep)
345 mmc->slots[0].vcc_aux_disable_is_sleep = 1; 345 mmc->slots[0].vcc_aux_disable_is_sleep = 1;
346 346
347 if (cpu_is_omap44xx()) {
348 if (omap_rev() > OMAP4430_REV_ES1_0)
349 mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
350 if (c->mmc >= 3 && c->mmc <= 5)
351 mmc->slots[0].features |= HSMMC_HAS_48MHZ_MASTER_CLK;
352 }
353
347 /* 354 /*
348 * NOTE: MMC slots should have a Vcc regulator set up. 355 * NOTE: MMC slots should have a Vcc regulator set up.
349 * This may be from a TWL4030-family chip, another 356 * This may be from a TWL4030-family chip, another
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index ecfe93c4b58..23b2ee36cfa 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -64,7 +64,6 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
64 omap_modify_auxcoreboot0(0x200, 0xfffffdff); 64 omap_modify_auxcoreboot0(0x200, 0xfffffdff);
65 flush_cache_all(); 65 flush_cache_all();
66 smp_wmb(); 66 smp_wmb();
67 gic_raise_softirq(cpumask_of(cpu), 1);
68 67
69 /* 68 /*
70 * Now the secondary core is starting up let it run its 69 * Now the secondary core is starting up let it run its
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 256846b02de..b58e2880ad2 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -776,7 +776,7 @@ static struct omap_hwmod omap443x_bandgap_hwmod = {
776 }, 776 },
777 .opt_clks = bandgap443x_opt_clks, 777 .opt_clks = bandgap443x_opt_clks,
778 .opt_clks_cnt = ARRAY_SIZE(bandgap443x_opt_clks), 778 .opt_clks_cnt = ARRAY_SIZE(bandgap443x_opt_clks),
779 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 779 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP443X),
780}; 780};
781 781
782static struct omap_hwmod_opt_clk bandgap446x_opt_clks[] = { 782static struct omap_hwmod_opt_clk bandgap446x_opt_clks[] = {
@@ -1778,7 +1778,7 @@ static struct omap_hwmod omap443x_gpio1_hwmod = {
1778 .dev_attr = &gpio_dev_attr, 1778 .dev_attr = &gpio_dev_attr,
1779 .slaves = omap44xx_gpio1_slaves, 1779 .slaves = omap44xx_gpio1_slaves,
1780 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves), 1780 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves),
1781 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 1781 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP443X),
1782}; 1782};
1783 1783
1784static struct omap_hwmod omap446x_gpio1_hwmod = { 1784static struct omap_hwmod omap446x_gpio1_hwmod = {
@@ -2214,7 +2214,6 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
2214 }, 2214 },
2215 .slaves = omap44xx_i2c1_slaves, 2215 .slaves = omap44xx_i2c1_slaves,
2216 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves), 2216 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves),
2217 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2218 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX), 2217 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
2219}; 2218};
2220 2219
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index d23d979b9c3..32a92e5317b 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -43,6 +43,18 @@
43#define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON) 43#define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON)
44#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | PWRSTS_ON) 44#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | PWRSTS_ON)
45 45
46#define PWRSTS_RET_INA_ON ((1 << PWRDM_POWER_RET) | \
47 (1 << PWRDM_POWER_INACTIVE) | \
48 (1 << PWRDM_POWER_ON))
49
50#define PWRSTS_OFF_INA_ON ((1 << PWRDM_POWER_OFF) | \
51 (1 << PWRDM_POWER_INACTIVE) | \
52 (1 << PWRDM_POWER_ON))
53
54#define PWRSTS_OFF_RET_INA_ON ((1 << PWRDM_POWER_OFF) | \
55 (1 << PWRDM_POWER_RET) | \
56 (1 << PWRDM_POWER_INACTIVE) | \
57 (1 << PWRDM_POWER_ON))
46 58
47/* Powerdomain flags */ 59/* Powerdomain flags */
48#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */ 60#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */
diff --git a/arch/arm/mach-omap2/powerdomains44xx_data.c b/arch/arm/mach-omap2/powerdomains44xx_data.c
index 159fd103949..e970d18f65b 100644
--- a/arch/arm/mach-omap2/powerdomains44xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains44xx_data.c
@@ -36,7 +36,7 @@ static struct powerdomain core_44xx_pwrdm = {
36 .prcm_offs = OMAP4430_PRM_CORE_INST, 36 .prcm_offs = OMAP4430_PRM_CORE_INST,
37 .prcm_partition = OMAP4430_PRM_PARTITION, 37 .prcm_partition = OMAP4430_PRM_PARTITION,
38 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX), 38 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
39 .pwrsts = PWRSTS_RET_ON, 39 .pwrsts = PWRSTS_RET_INA_ON,
40 .pwrsts_logic_ret = PWRSTS_OFF_RET, 40 .pwrsts_logic_ret = PWRSTS_OFF_RET,
41 .banks = 5, 41 .banks = 5,
42 .pwrsts_mem_ret = { 42 .pwrsts_mem_ret = {
@@ -62,7 +62,7 @@ static struct powerdomain gfx_44xx_pwrdm = {
62 .prcm_offs = OMAP4430_PRM_GFX_INST, 62 .prcm_offs = OMAP4430_PRM_GFX_INST,
63 .prcm_partition = OMAP4430_PRM_PARTITION, 63 .prcm_partition = OMAP4430_PRM_PARTITION,
64 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX), 64 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
65 .pwrsts = PWRSTS_OFF_ON, 65 .pwrsts = PWRSTS_OFF_INA_ON,
66 .banks = 1, 66 .banks = 1,
67 .pwrsts_mem_ret = { 67 .pwrsts_mem_ret = {
68 [0] = PWRSTS_OFF, /* gfx_mem */ 68 [0] = PWRSTS_OFF, /* gfx_mem */
@@ -79,7 +79,7 @@ static struct powerdomain abe_44xx_pwrdm = {
79 .prcm_offs = OMAP4430_PRM_ABE_INST, 79 .prcm_offs = OMAP4430_PRM_ABE_INST,
80 .prcm_partition = OMAP4430_PRM_PARTITION, 80 .prcm_partition = OMAP4430_PRM_PARTITION,
81 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX), 81 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
82 .pwrsts = PWRSTS_OFF_RET_ON, 82 .pwrsts = PWRSTS_OFF_RET_INA_ON,
83 .pwrsts_logic_ret = PWRSTS_OFF, 83 .pwrsts_logic_ret = PWRSTS_OFF,
84 .banks = 2, 84 .banks = 2,
85 .pwrsts_mem_ret = { 85 .pwrsts_mem_ret = {
@@ -99,7 +99,7 @@ static struct powerdomain dss_44xx_pwrdm = {
99 .prcm_offs = OMAP4430_PRM_DSS_INST, 99 .prcm_offs = OMAP4430_PRM_DSS_INST,
100 .prcm_partition = OMAP4430_PRM_PARTITION, 100 .prcm_partition = OMAP4430_PRM_PARTITION,
101 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX), 101 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
102 .pwrsts = PWRSTS_OFF_RET_ON, 102 .pwrsts = PWRSTS_OFF_RET_INA_ON,
103 .pwrsts_logic_ret = PWRSTS_OFF, 103 .pwrsts_logic_ret = PWRSTS_OFF,
104 .banks = 1, 104 .banks = 1,
105 .pwrsts_mem_ret = { 105 .pwrsts_mem_ret = {
@@ -117,7 +117,7 @@ static struct powerdomain tesla_44xx_pwrdm = {
117 .prcm_offs = OMAP4430_PRM_TESLA_INST, 117 .prcm_offs = OMAP4430_PRM_TESLA_INST,
118 .prcm_partition = OMAP4430_PRM_PARTITION, 118 .prcm_partition = OMAP4430_PRM_PARTITION,
119 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX), 119 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
120 .pwrsts = PWRSTS_OFF_RET_ON, 120 .pwrsts = PWRSTS_OFF_RET_INA_ON,
121 .pwrsts_logic_ret = PWRSTS_OFF_RET, 121 .pwrsts_logic_ret = PWRSTS_OFF_RET,
122 .banks = 3, 122 .banks = 3,
123 .pwrsts_mem_ret = { 123 .pwrsts_mem_ret = {
@@ -155,7 +155,7 @@ static struct powerdomain cpu0_44xx_pwrdm = {
155 .prcm_offs = OMAP4430_PRCM_MPU_CPU0_INST, 155 .prcm_offs = OMAP4430_PRCM_MPU_CPU0_INST,
156 .prcm_partition = OMAP4430_PRCM_MPU_PARTITION, 156 .prcm_partition = OMAP4430_PRCM_MPU_PARTITION,
157 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX), 157 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
158 .pwrsts = PWRSTS_OFF_RET_ON, 158 .pwrsts = PWRSTS_OFF_RET_INA_ON,
159 .pwrsts_logic_ret = PWRSTS_OFF_RET, 159 .pwrsts_logic_ret = PWRSTS_OFF_RET,
160 .banks = 1, 160 .banks = 1,
161 .pwrsts_mem_ret = { 161 .pwrsts_mem_ret = {
@@ -172,7 +172,7 @@ static struct powerdomain cpu1_44xx_pwrdm = {
172 .prcm_offs = OMAP4430_PRCM_MPU_CPU1_INST, 172 .prcm_offs = OMAP4430_PRCM_MPU_CPU1_INST,
173 .prcm_partition = OMAP4430_PRCM_MPU_PARTITION, 173 .prcm_partition = OMAP4430_PRCM_MPU_PARTITION,
174 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX), 174 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
175 .pwrsts = PWRSTS_OFF_RET_ON, 175 .pwrsts = PWRSTS_OFF_RET_INA_ON,
176 .pwrsts_logic_ret = PWRSTS_OFF_RET, 176 .pwrsts_logic_ret = PWRSTS_OFF_RET,
177 .banks = 1, 177 .banks = 1,
178 .pwrsts_mem_ret = { 178 .pwrsts_mem_ret = {
@@ -204,8 +204,8 @@ static struct powerdomain mpu_443x_pwrdm = {
204 .name = "mpu_pwrdm", 204 .name = "mpu_pwrdm",
205 .prcm_offs = OMAP4430_PRM_MPU_INST, 205 .prcm_offs = OMAP4430_PRM_MPU_INST,
206 .prcm_partition = OMAP4430_PRM_PARTITION, 206 .prcm_partition = OMAP4430_PRM_PARTITION,
207 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 207 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP443X),
208 .pwrsts = PWRSTS_OFF_RET_ON, 208 .pwrsts = PWRSTS_OFF_RET_INA_ON,
209 .pwrsts_logic_ret = PWRSTS_OFF_RET, 209 .pwrsts_logic_ret = PWRSTS_OFF_RET,
210 .banks = 3, 210 .banks = 3,
211 .pwrsts_mem_ret = { 211 .pwrsts_mem_ret = {
@@ -225,7 +225,7 @@ static struct powerdomain mpu_446x_pwrdm = {
225 .prcm_offs = OMAP4430_PRM_MPU_INST, 225 .prcm_offs = OMAP4430_PRM_MPU_INST,
226 .prcm_partition = OMAP4430_PRM_PARTITION, 226 .prcm_partition = OMAP4430_PRM_PARTITION,
227 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP446X), 227 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP446X),
228 .pwrsts = PWRSTS_RET_ON, 228 .pwrsts = PWRSTS_RET_INA_ON,
229 .pwrsts_logic_ret = PWRSTS_OFF_RET, 229 .pwrsts_logic_ret = PWRSTS_OFF_RET,
230 .banks = 2, 230 .banks = 2,
231 .pwrsts_mem_ret = { 231 .pwrsts_mem_ret = {
@@ -244,7 +244,7 @@ static struct powerdomain ivahd_44xx_pwrdm = {
244 .prcm_offs = OMAP4430_PRM_IVAHD_INST, 244 .prcm_offs = OMAP4430_PRM_IVAHD_INST,
245 .prcm_partition = OMAP4430_PRM_PARTITION, 245 .prcm_partition = OMAP4430_PRM_PARTITION,
246 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX), 246 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
247 .pwrsts = PWRSTS_OFF_RET_ON, 247 .pwrsts = PWRSTS_OFF_RET_INA_ON,
248 .pwrsts_logic_ret = PWRSTS_OFF, 248 .pwrsts_logic_ret = PWRSTS_OFF,
249 .banks = 4, 249 .banks = 4,
250 .pwrsts_mem_ret = { 250 .pwrsts_mem_ret = {
@@ -268,7 +268,7 @@ static struct powerdomain cam_44xx_pwrdm = {
268 .prcm_offs = OMAP4430_PRM_CAM_INST, 268 .prcm_offs = OMAP4430_PRM_CAM_INST,
269 .prcm_partition = OMAP4430_PRM_PARTITION, 269 .prcm_partition = OMAP4430_PRM_PARTITION,
270 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX), 270 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
271 .pwrsts = PWRSTS_OFF_ON, 271 .pwrsts = PWRSTS_OFF_INA_ON,
272 .banks = 1, 272 .banks = 1,
273 .pwrsts_mem_ret = { 273 .pwrsts_mem_ret = {
274 [0] = PWRSTS_OFF, /* cam_mem */ 274 [0] = PWRSTS_OFF, /* cam_mem */
@@ -285,7 +285,7 @@ static struct powerdomain l3init_44xx_pwrdm = {
285 .prcm_offs = OMAP4430_PRM_L3INIT_INST, 285 .prcm_offs = OMAP4430_PRM_L3INIT_INST,
286 .prcm_partition = OMAP4430_PRM_PARTITION, 286 .prcm_partition = OMAP4430_PRM_PARTITION,
287 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX), 287 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
288 .pwrsts = PWRSTS_RET_ON, 288 .pwrsts = PWRSTS_OFF_RET_INA_ON,
289 .pwrsts_logic_ret = PWRSTS_OFF_RET, 289 .pwrsts_logic_ret = PWRSTS_OFF_RET,
290 .banks = 1, 290 .banks = 1,
291 .pwrsts_mem_ret = { 291 .pwrsts_mem_ret = {
@@ -303,7 +303,7 @@ static struct powerdomain l4per_44xx_pwrdm = {
303 .prcm_offs = OMAP4430_PRM_L4PER_INST, 303 .prcm_offs = OMAP4430_PRM_L4PER_INST,
304 .prcm_partition = OMAP4430_PRM_PARTITION, 304 .prcm_partition = OMAP4430_PRM_PARTITION,
305 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX), 305 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
306 .pwrsts = PWRSTS_RET_ON, 306 .pwrsts = PWRSTS_RET_INA_ON,
307 .pwrsts_logic_ret = PWRSTS_OFF_RET, 307 .pwrsts_logic_ret = PWRSTS_OFF_RET,
308 .banks = 2, 308 .banks = 2,
309 .pwrsts_mem_ret = { 309 .pwrsts_mem_ret = {
@@ -335,7 +335,7 @@ static struct powerdomain cefuse_44xx_pwrdm = {
335 .prcm_offs = OMAP4430_PRM_CEFUSE_INST, 335 .prcm_offs = OMAP4430_PRM_CEFUSE_INST,
336 .prcm_partition = OMAP4430_PRM_PARTITION, 336 .prcm_partition = OMAP4430_PRM_PARTITION,
337 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX), 337 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX),
338 .pwrsts = PWRSTS_OFF_ON, 338 .pwrsts = PWRSTS_OFF_INA_ON,
339}; 339};
340 340
341/* 341/*
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 1ac361b7b8c..d82464595a2 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -347,7 +347,7 @@ static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
347 if (uart->dma_enabled) 347 if (uart->dma_enabled)
348 idlemode = HWMOD_IDLEMODE_FORCE; 348 idlemode = HWMOD_IDLEMODE_FORCE;
349 else 349 else
350 idlemode = HWMOD_IDLEMODE_SMART; 350 idlemode = HWMOD_IDLEMODE_SMART_WKUP;
351 } else { 351 } else {
352 idlemode = HWMOD_IDLEMODE_NO; 352 idlemode = HWMOD_IDLEMODE_NO;
353 } 353 }
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 973b7dc3e84..12a9ced8b04 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -56,14 +56,14 @@ struct clkops {
56#define RATE_IN_3430ES1 (1 << 2) /* 3430ES1 rates only */ 56#define RATE_IN_3430ES1 (1 << 2) /* 3430ES1 rates only */
57#define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */ 57#define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */
58#define RATE_IN_36XX (1 << 4) 58#define RATE_IN_36XX (1 << 4)
59#define RATE_IN_4430 (1 << 5) 59#define RATE_IN_443X (1 << 5)
60#define RATE_IN_TI816X (1 << 6) 60#define RATE_IN_TI816X (1 << 6)
61#define RATE_IN_446X (1 << 7) 61#define RATE_IN_446X (1 << 7)
62 62
63#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) 63#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
64#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS) 64#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
65#define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX) 65#define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX)
66#define RATE_IN_44XX (RATE_IN_4430 | RATE_IN_446X) 66#define RATE_IN_44XX (RATE_IN_443X | RATE_IN_446X)
67 67
68/* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */ 68/* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
69#define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX) 69#define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX)
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 86b14200e31..3faa25120c5 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -451,14 +451,14 @@ IS_OMAP_TYPE(3517, 0x3517)
451 451
452#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) 452#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
453 453
454#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1 | \ 454#define CHIP_IS_OMAP443X (CHIP_IS_OMAP4430ES1 | \
455 CHIP_IS_OMAP4430ES2 | \ 455 CHIP_IS_OMAP4430ES2 | \
456 CHIP_IS_OMAP4430ES2_1 | \ 456 CHIP_IS_OMAP4430ES2_1 | \
457 CHIP_IS_OMAP4430ES2_2) 457 CHIP_IS_OMAP4430ES2_2)
458 458
459#define CHIP_IS_OMAP446X CHIP_IS_OMAP4460ES1_0 459#define CHIP_IS_OMAP446X CHIP_IS_OMAP4460ES1_0
460 460
461#define CHIP_IS_OMAP44XX (CHIP_IS_OMAP4430 | CHIP_IS_OMAP446X) 461#define CHIP_IS_OMAP44XX (CHIP_IS_OMAP443X | CHIP_IS_OMAP446X)
462 462
463/* 463/*
464 * "GE" here represents "greater than or equal to" in terms of ES 464 * "GE" here represents "greater than or equal to" in terms of ES
diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
index c7b874186c2..f24ed418545 100644
--- a/arch/arm/plat-omap/include/plat/mmc.h
+++ b/arch/arm/plat-omap/include/plat/mmc.h
@@ -108,8 +108,9 @@ struct omap_mmc_platform_data {
108 unsigned vcc_aux_disable_is_sleep:1; 108 unsigned vcc_aux_disable_is_sleep:1;
109 109
110 /* we can put the features above into this variable */ 110 /* we can put the features above into this variable */
111#define HSMMC_HAS_PBIAS (1 << 0) 111#define HSMMC_HAS_PBIAS (1 << 0)
112#define HSMMC_HAS_UPDATED_RESET (1 << 1) 112#define HSMMC_HAS_UPDATED_RESET (1 << 1)
113#define HSMMC_HAS_48MHZ_MASTER_CLK (1 << 2)
113 unsigned features; 114 unsigned features;
114 115
115 int switch_pin; /* gpio (card detect) */ 116 int switch_pin; /* gpio (card detect) */
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 922c77196d6..2f54e4b6d72 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -166,6 +166,7 @@ struct omap_hsmmc_host {
166 unsigned int id; 166 unsigned int id;
167 unsigned int dma_len; 167 unsigned int dma_len;
168 unsigned int dma_sg_idx; 168 unsigned int dma_sg_idx;
169 unsigned int master_clock;
169 unsigned char bus_mode; 170 unsigned char bus_mode;
170 unsigned char power_mode; 171 unsigned char power_mode;
171 u32 *buffer; 172 u32 *buffer;
@@ -676,11 +677,11 @@ static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
676 } 677 }
677 678
678 if (ios->clock) { 679 if (ios->clock) {
679 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock; 680 dsor = host->master_clock / ios->clock;
680 if (dsor < 1) 681 if (dsor < 1)
681 dsor = 1; 682 dsor = 1;
682 683
683 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock) 684 if (host->master_clock / dsor > ios->clock)
684 dsor++; 685 dsor++;
685 686
686 if (dsor > 250) 687 if (dsor > 250)
@@ -1593,11 +1594,11 @@ static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1593 } 1594 }
1594 1595
1595 if (ios->clock) { 1596 if (ios->clock) {
1596 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock; 1597 dsor = host->master_clock / ios->clock;
1597 if (dsor < 1) 1598 if (dsor < 1)
1598 dsor = 1; 1599 dsor = 1;
1599 1600
1600 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock) 1601 if (host->master_clock / dsor > ios->clock)
1601 dsor++; 1602 dsor++;
1602 1603
1603 if (dsor > 250) 1604 if (dsor > 250)
@@ -2078,6 +2079,10 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev)
2078 host->base = ioremap(host->mapbase, SZ_4K); 2079 host->base = ioremap(host->mapbase, SZ_4K);
2079 host->power_mode = -1; 2080 host->power_mode = -1;
2080 2081
2082 host->master_clock = OMAP_MMC_MASTER_CLOCK;
2083 if (mmc_slot(host).features & HSMMC_HAS_48MHZ_MASTER_CLK)
2084 host->master_clock = OMAP_MMC_MASTER_CLOCK / 2;
2085
2081 platform_set_drvdata(pdev, host); 2086 platform_set_drvdata(pdev, host);
2082 INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect); 2087 INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect);
2083 2088
diff --git a/drivers/regulator/twl-regulator.c b/drivers/regulator/twl-regulator.c
index 87fe0f75a56..503c2bc64c8 100644
--- a/drivers/regulator/twl-regulator.c
+++ b/drivers/regulator/twl-regulator.c
@@ -864,7 +864,7 @@ static struct regulator_ops twlsmps_ops = {
864 .desc = { \ 864 .desc = { \
865 .name = #label, \ 865 .name = #label, \
866 .id = TWL6030_REG_##label, \ 866 .id = TWL6030_REG_##label, \
867 .n_voltages = (max_mVolts - min_mVolts)/100, \ 867 .n_voltages = (max_mVolts - min_mVolts)/100 + 1, \
868 .ops = &twl6030ldo_ops, \ 868 .ops = &twl6030ldo_ops, \
869 .type = REGULATOR_VOLTAGE, \ 869 .type = REGULATOR_VOLTAGE, \
870 .owner = THIS_MODULE, \ 870 .owner = THIS_MODULE, \
diff --git a/include/linux/clockchips.h b/include/linux/clockchips.h
index d6733e27af3..267ba73a5f2 100644
--- a/include/linux/clockchips.h
+++ b/include/linux/clockchips.h
@@ -144,6 +144,8 @@ extern int clockevents_program_event(struct clock_event_device *dev,
144 144
145extern void clockevents_handle_noop(struct clock_event_device *dev); 145extern void clockevents_handle_noop(struct clock_event_device *dev);
146 146
147extern int clockevents_reconfigure(struct clock_event_device *ce, u32 freq, u32 minsec);
148
147static inline void 149static inline void
148clockevents_calc_mult_shift(struct clock_event_device *ce, u32 freq, u32 minsec) 150clockevents_calc_mult_shift(struct clock_event_device *ce, u32 freq, u32 minsec)
149{ 151{
diff --git a/kernel/time/clockevents.c b/kernel/time/clockevents.c
index e4c699dfa4e..a8a3d49c94a 100644
--- a/kernel/time/clockevents.c
+++ b/kernel/time/clockevents.c
@@ -133,6 +133,30 @@ int clockevents_program_event(struct clock_event_device *dev, ktime_t expires,
133} 133}
134 134
135/** 135/**
136 * clockevents_reconfigure - Reconfigure and reprogram a clock event device.
137 * @dev: device to modify
138 * @freq: new device frequency
139 * @secr: guaranteed runtime conversion range in seconds
140 *
141 * Reconfigure and reprogram a clock event device in oneshot
142 * mode. Must only be called from low level idle code where
143 * interaction with hrtimers/nohz code etc. is not possible and
144 * guaranteed not to conflict. Must be called with interrupts
145 * disabled!
146 * Returns 0 on success, -ETIME when the event is in the past or
147 * -EINVAL when called with invalid parameters.
148 */
149int clockevents_reconfigure(struct clock_event_device *dev, u32 freq, u32 secr)
150{
151 if (dev->mode != CLOCK_EVT_MODE_ONESHOT)
152 return -EINVAL;
153
154 clockevents_calc_mult_shift(dev, freq, secr ? secr : 1);
155
156 return clockevents_program_event(dev, dev->next_event, ktime_get());
157}
158
159/**
136 * clockevents_register_notifier - register a clock events change listener 160 * clockevents_register_notifier - register a clock events change listener
137 */ 161 */
138int clockevents_register_notifier(struct notifier_block *nb) 162int clockevents_register_notifier(struct notifier_block *nb)
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-11 16:46:40 -0400