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-rw-r--r--arch/arm/mach-omap2/Makefile1
-rw-r--r--arch/arm/mach-omap2/omap_l3_noc.c253
-rw-r--r--arch/arm/mach-omap2/omap_l3_noc.h132
3 files changed, 386 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index e4c9bb3ad89..8ef8711eac9 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -137,6 +137,7 @@ obj-$(CONFIG_OMAP3_EMU) += emu.o
137 137
138# L3 interconnect 138# L3 interconnect
139obj-$(CONFIG_ARCH_OMAP3) += omap_l3_smx.o 139obj-$(CONFIG_ARCH_OMAP3) += omap_l3_smx.o
140obj-$(CONFIG_ARCH_OMAP4) += omap_l3_noc.o
140 141
141obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o 142obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o
142mailbox_mach-objs := mailbox.o 143mailbox_mach-objs := mailbox.o
diff --git a/arch/arm/mach-omap2/omap_l3_noc.c b/arch/arm/mach-omap2/omap_l3_noc.c
new file mode 100644
index 00000000000..82632c24076
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_l3_noc.c
@@ -0,0 +1,253 @@
1/*
2 * OMAP4XXX L3 Interconnect error handling driver
3 *
4 * Copyright (C) 2011 Texas Corporation
5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 * Sricharan <r.sricharan@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
21 * USA
22 */
23#include <linux/init.h>
24#include <linux/io.h>
25#include <linux/platform_device.h>
26#include <linux/interrupt.h>
27#include <linux/kernel.h>
28#include <linux/slab.h>
29
30#include "omap_l3_noc.h"
31
32/*
33 * Interrupt Handler for L3 error detection.
34 * 1) Identify the L3 clockdomain partition to which the error belongs to.
35 * 2) Identify the slave where the error information is logged
36 * 3) Print the logged information.
37 * 4) Add dump stack to provide kernel trace.
38 *
39 * Two Types of errors :
40 * 1) Custom errors in L3 :
41 * Target like DMM/FW/EMIF generates SRESP=ERR error
42 * 2) Standard L3 error:
43 * - Unsupported CMD.
44 * L3 tries to access target while it is idle
45 * - OCP disconnect.
46 * - Address hole error:
47 * If DSS/ISS/FDIF/USBHOSTFS access a target where they
48 * do not have connectivity, the error is logged in
49 * their default target which is DMM2.
50 *
51 * On High Secure devices, firewall errors are possible and those
52 * can be trapped as well. But the trapping is implemented as part
53 * secure software and hence need not be implemented here.
54 */
55static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
56{
57
58 struct omap4_l3 *l3 = _l3;
59 int inttype, i, j;
60 int err_src = 0;
61 u32 std_err_main_addr, std_err_main, err_reg;
62 u32 base, slave_addr, clear;
63 char *source_name;
64
65 /* Get the Type of interrupt */
66 if (irq == l3->app_irq)
67 inttype = L3_APPLICATION_ERROR;
68 else
69 inttype = L3_DEBUG_ERROR;
70
71 for (i = 0; i < L3_MODULES; i++) {
72 /*
73 * Read the regerr register of the clock domain
74 * to determine the source
75 */
76 base = (u32)l3->l3_base[i];
77 err_reg = readl(base + l3_flagmux[i] + (inttype << 3));
78
79 /* Get the corresponding error and analyse */
80 if (err_reg) {
81 /* Identify the source from control status register */
82 for (j = 0; !(err_reg & (1 << j)); j++)
83 ;
84
85 err_src = j;
86 /* Read the stderrlog_main_source from clk domain */
87 std_err_main_addr = base + (*(l3_targ[i] + err_src));
88 std_err_main = readl(std_err_main_addr);
89
90 switch ((std_err_main & CUSTOM_ERROR)) {
91 case STANDARD_ERROR:
92 source_name =
93 l3_targ_stderrlog_main_name[i][err_src];
94
95 slave_addr = std_err_main_addr +
96 L3_SLAVE_ADDRESS_OFFSET;
97 WARN(true, "L3 standard error: SOURCE:%s at address 0x%x\n",
98 source_name, readl(slave_addr));
99 /* clear the std error log*/
100 clear = std_err_main | CLEAR_STDERR_LOG;
101 writel(clear, std_err_main_addr);
102 break;
103
104 case CUSTOM_ERROR:
105 source_name =
106 l3_targ_stderrlog_main_name[i][err_src];
107
108 WARN(true, "CUSTOM SRESP error with SOURCE:%s\n",
109 source_name);
110 /* clear the std error log*/
111 clear = std_err_main | CLEAR_STDERR_LOG;
112 writel(clear, std_err_main_addr);
113 break;
114
115 default:
116 /* Nothing to be handled here as of now */
117 break;
118 }
119 /* Error found so break the for loop */
120 break;
121 }
122 }
123 return IRQ_HANDLED;
124}
125
126static int __init omap4_l3_probe(struct platform_device *pdev)
127{
128 static struct omap4_l3 *l3;
129 struct resource *res;
130 int ret;
131 int irq;
132
133 l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
134 if (!l3)
135 ret = -ENOMEM;
136
137 platform_set_drvdata(pdev, l3);
138 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
139 if (!res) {
140 dev_err(&pdev->dev, "couldn't find resource 0\n");
141 ret = -ENODEV;
142 goto err1;
143 }
144
145 l3->l3_base[0] = ioremap(res->start, resource_size(res));
146 if (!(l3->l3_base[0])) {
147 dev_err(&pdev->dev, "ioremap failed\n");
148 ret = -ENOMEM;
149 goto err2;
150 }
151
152 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
153 if (!res) {
154 dev_err(&pdev->dev, "couldn't find resource 1\n");
155 ret = -ENODEV;
156 goto err3;
157 }
158
159 l3->l3_base[1] = ioremap(res->start, resource_size(res));
160 if (!(l3->l3_base[1])) {
161 dev_err(&pdev->dev, "ioremap failed\n");
162 ret = -ENOMEM;
163 goto err4;
164 }
165
166 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
167 if (!res) {
168 dev_err(&pdev->dev, "couldn't find resource 2\n");
169 ret = -ENODEV;
170 goto err5;
171 }
172
173 l3->l3_base[2] = ioremap(res->start, resource_size(res));
174 if (!(l3->l3_base[2])) {
175 dev_err(&pdev->dev, "ioremap failed\n");
176 ret = -ENOMEM;
177 goto err6;
178 }
179
180 /*
181 * Setup interrupt Handlers
182 */
183 irq = platform_get_irq(pdev, 0);
184 ret = request_irq(irq,
185 l3_interrupt_handler,
186 IRQF_DISABLED, "l3-dbg-irq", l3);
187 if (ret) {
188 pr_crit("L3: request_irq failed to register for 0x%x\n",
189 OMAP44XX_IRQ_L3_DBG);
190 goto err7;
191 }
192 l3->debug_irq = irq;
193
194 irq = platform_get_irq(pdev, 1);
195 ret = request_irq(irq,
196 l3_interrupt_handler,
197 IRQF_DISABLED, "l3-app-irq", l3);
198 if (ret) {
199 pr_crit("L3: request_irq failed to register for 0x%x\n",
200 OMAP44XX_IRQ_L3_APP);
201 goto err8;
202 }
203 l3->app_irq = irq;
204
205 goto err0;
206err8:
207err7:
208 iounmap(l3->l3_base[2]);
209err6:
210err5:
211 iounmap(l3->l3_base[1]);
212err4:
213err3:
214 iounmap(l3->l3_base[0]);
215err2:
216err1:
217 kfree(l3);
218err0:
219 return ret;
220}
221
222static int __exit omap4_l3_remove(struct platform_device *pdev)
223{
224 struct omap4_l3 *l3 = platform_get_drvdata(pdev);
225
226 free_irq(l3->app_irq, l3);
227 free_irq(l3->debug_irq, l3);
228 iounmap(l3->l3_base[0]);
229 iounmap(l3->l3_base[1]);
230 iounmap(l3->l3_base[2]);
231 kfree(l3);
232
233 return 0;
234}
235
236static struct platform_driver omap4_l3_driver = {
237 .remove = __exit_p(omap4_l3_remove),
238 .driver = {
239 .name = "omap_l3_noc",
240 },
241};
242
243static int __init omap4_l3_init(void)
244{
245 return platform_driver_probe(&omap4_l3_driver, omap4_l3_probe);
246}
247postcore_initcall_sync(omap4_l3_init);
248
249static void __exit omap4_l3_exit(void)
250{
251 platform_driver_unregister(&omap4_l3_driver);
252}
253module_exit(omap4_l3_exit);
diff --git a/arch/arm/mach-omap2/omap_l3_noc.h b/arch/arm/mach-omap2/omap_l3_noc.h
new file mode 100644
index 00000000000..359b83348ae
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_l3_noc.h
@@ -0,0 +1,132 @@
1 /*
2 * OMAP4XXX L3 Interconnect error handling driver header
3 *
4 * Copyright (C) 2011 Texas Corporation
5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 * sricharan <r.sricharan@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
21 * USA
22 */
23#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
24#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
25
26/*
27 * L3 register offsets
28 */
29#define L3_MODULES 3
30#define CLEAR_STDERR_LOG (1 << 31)
31#define CUSTOM_ERROR 0x2
32#define STANDARD_ERROR 0x0
33#define INBAND_ERROR 0x0
34#define EMIF_KERRLOG_OFFSET 0x10
35#define L3_SLAVE_ADDRESS_OFFSET 0x14
36#define LOGICAL_ADDR_ERRORLOG 0x4
37#define L3_APPLICATION_ERROR 0x0
38#define L3_DEBUG_ERROR 0x1
39
40u32 l3_flagmux[L3_MODULES] = {
41 0x50C,
42 0x100C,
43 0X020C
44};
45
46/*
47 * L3 Target standard Error register offsets
48 */
49u32 l3_targ_stderrlog_main_clk1[] = {
50 0x148, /* DMM1 */
51 0x248, /* DMM2 */
52 0x348, /* ABE */
53 0x448, /* L4CFG */
54 0x648 /* CLK2 PWR DISC */
55};
56
57u32 l3_targ_stderrlog_main_clk2[] = {
58 0x548, /* CORTEX M3 */
59 0x348, /* DSS */
60 0x148, /* GPMC */
61 0x448, /* ISS */
62 0x748, /* IVAHD */
63 0xD48, /* missing in TRM corresponds to AES1*/
64 0x948, /* L4 PER0*/
65 0x248, /* OCMRAM */
66 0x148, /* missing in TRM corresponds to GPMC sERROR*/
67 0x648, /* SGX */
68 0x848, /* SL2 */
69 0x1648, /* C2C */
70 0x1148, /* missing in TRM corresponds PWR DISC CLK1*/
71 0xF48, /* missing in TRM corrsponds to SHA1*/
72 0xE48, /* missing in TRM corresponds to AES2*/
73 0xC48, /* L4 PER3 */
74 0xA48, /* L4 PER1*/
75 0xB48 /* L4 PER2*/
76};
77
78u32 l3_targ_stderrlog_main_clk3[] = {
79 0x0148 /* EMUSS */
80};
81
82char *l3_targ_stderrlog_main_name[L3_MODULES][18] = {
83 {
84 "DMM1",
85 "DMM2",
86 "ABE",
87 "L4CFG",
88 "CLK2 PWR DISC",
89 },
90 {
91 "CORTEX M3" ,
92 "DSS ",
93 "GPMC ",
94 "ISS ",
95 "IVAHD ",
96 "AES1",
97 "L4 PER0",
98 "OCMRAM ",
99 "GPMC sERROR",
100 "SGX ",
101 "SL2 ",
102 "C2C ",
103 "PWR DISC CLK1",
104 "SHA1",
105 "AES2",
106 "L4 PER3",
107 "L4 PER1",
108 "L4 PER2",
109 },
110 {
111 "EMUSS",
112 },
113};
114
115u32 *l3_targ[L3_MODULES] = {
116 l3_targ_stderrlog_main_clk1,
117 l3_targ_stderrlog_main_clk2,
118 l3_targ_stderrlog_main_clk3,
119};
120
121struct omap4_l3 {
122 struct device *dev;
123 struct clk *ick;
124
125 /* memory base */
126 void __iomem *l3_base[4];
127
128 int debug_irq;
129 int app_irq;
130};
131
132#endif
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-01 14:37:48 -0500