5 files changed, 84 insertions, 44 deletions

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 46d03ccc280..180299e4a83 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -22,7 +22,9 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/bitops.h>
+#include <trace/events/power.h>
 
+#include <asm/cpu.h>
 #include <plat/clock.h>
 #include "clockdomain.h"
 #include <plat/cpu.h>
@@ -261,8 +263,10 @@ void omap2_clk_disable(struct clk *clk)
 
         pr_debug("clock: %s: disabling in hardware\n", clk->name);
 
-        if (clk->ops && clk->ops->disable)
+        if (clk->ops && clk->ops->disable) {
+                trace_clock_disable(clk->name, 0, smp_processor_id());
                 clk->ops->disable(clk);
+        }
 
         if (clk->clkdm)
                 clkdm_clk_disable(clk->clkdm, clk);
@@ -314,6 +318,7 @@ int omap2_clk_enable(struct clk *clk)
         }
 
         if (clk->ops && clk->ops->enable) {
+                trace_clock_enable(clk->name, 1, smp_processor_id());
                 ret = clk->ops->enable(clk);
                 if (ret) {
                         WARN(1, "clock: %s: could not enable: %d\n",
@@ -353,8 +358,10 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
         pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
 
         /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
-        if (clk->set_rate)
+        if (clk->set_rate) {
+                trace_clock_set_rate(clk->name, rate, smp_processor_id());
                 ret = clk->set_rate(clk, rate);
+        }
 
         return ret;
 }
diff --git a/arch/arm/mach-omap2/opp3xxx_data.c b/arch/arm/mach-omap2/opp3xxx_data.c
index d2bd1bd83bf..d95f3f945d4 100644
--- a/arch/arm/mach-omap2/opp3xxx_data.c
+++ b/arch/arm/mach-omap2/opp3xxx_data.c
@@ -89,15 +89,15 @@ struct omap_volt_data omap36xx_vddcore_volt_data[] = {
 
 static struct omap_opp_def __initdata omap34xx_opp_def_list[] = {
         /* MPU OPP1 */
-        OPP_INITIALIZER("mpu", true, 125000000, 975000),
+        OPP_INITIALIZER("mpu", true, 125000000, OMAP3430_VDD_MPU_OPP1_UV),
         /* MPU OPP2 */
-        OPP_INITIALIZER("mpu", true, 250000000, 1075000),
+        OPP_INITIALIZER("mpu", true, 250000000, OMAP3430_VDD_MPU_OPP2_UV),
         /* MPU OPP3 */
-        OPP_INITIALIZER("mpu", true, 500000000, 1200000),
+        OPP_INITIALIZER("mpu", true, 500000000, OMAP3430_VDD_MPU_OPP3_UV),
         /* MPU OPP4 */
-        OPP_INITIALIZER("mpu", true, 550000000, 1270000),
+        OPP_INITIALIZER("mpu", true, 550000000, OMAP3430_VDD_MPU_OPP4_UV),
         /* MPU OPP5 */
-        OPP_INITIALIZER("mpu", true, 600000000, 1350000),
+        OPP_INITIALIZER("mpu", true, 600000000, OMAP3430_VDD_MPU_OPP5_UV),
 
         /*
          * L3 OPP1 - 41.5 MHz is disabled because: The voltage for that OPP is
@@ -107,47 +107,47 @@ static struct omap_opp_def __initdata omap34xx_opp_def_list[] = {
          * impact that frequency will do to the MPU and the whole system in
          * general.
          */
-        OPP_INITIALIZER("l3_main", false, 41500000, 975000),
+        OPP_INITIALIZER("l3_main", false, 41500000, OMAP3430_VDD_CORE_OPP1_UV),
         /* L3 OPP2 */
-        OPP_INITIALIZER("l3_main", true, 83000000, 1050000),
+        OPP_INITIALIZER("l3_main", true, 83000000, OMAP3430_VDD_CORE_OPP2_UV),
         /* L3 OPP3 */
-        OPP_INITIALIZER("l3_main", true, 166000000, 1150000),
+        OPP_INITIALIZER("l3_main", true, 166000000, OMAP3430_VDD_CORE_OPP3_UV),
 
         /* DSP OPP1 */
-        OPP_INITIALIZER("iva", true, 90000000, 975000),
+        OPP_INITIALIZER("iva", true, 90000000, OMAP3430_VDD_MPU_OPP1_UV),
         /* DSP OPP2 */
-        OPP_INITIALIZER("iva", true, 180000000, 1075000),
+        OPP_INITIALIZER("iva", true, 180000000, OMAP3430_VDD_MPU_OPP2_UV),
         /* DSP OPP3 */
-        OPP_INITIALIZER("iva", true, 360000000, 1200000),
+        OPP_INITIALIZER("iva", true, 360000000, OMAP3430_VDD_MPU_OPP3_UV),
         /* DSP OPP4 */
-        OPP_INITIALIZER("iva", true, 400000000, 1270000),
+        OPP_INITIALIZER("iva", true, 400000000, OMAP3430_VDD_MPU_OPP4_UV),
         /* DSP OPP5 */
-        OPP_INITIALIZER("iva", true, 430000000, 1350000),
+        OPP_INITIALIZER("iva", true, 430000000, OMAP3430_VDD_MPU_OPP5_UV),
 };
 
 static struct omap_opp_def __initdata omap36xx_opp_def_list[] = {
         /* MPU OPP1 - OPP50 */
-        OPP_INITIALIZER("mpu", true,  300000000, 1012500),
+        OPP_INITIALIZER("mpu", true,  300000000, OMAP3630_VDD_MPU_OPP50_UV),
         /* MPU OPP2 - OPP100 */
-        OPP_INITIALIZER("mpu", true,  600000000, 1200000),
+        OPP_INITIALIZER("mpu", true,  600000000, OMAP3630_VDD_MPU_OPP100_UV),
         /* MPU OPP3 - OPP-Turbo */
-        OPP_INITIALIZER("mpu", false, 800000000, 1325000),
+        OPP_INITIALIZER("mpu", false, 800000000, OMAP3630_VDD_MPU_OPP120_UV),
         /* MPU OPP4 - OPP-SB */
-        OPP_INITIALIZER("mpu", false, 1000000000, 1375000),
+        OPP_INITIALIZER("mpu", false, 1000000000, OMAP3630_VDD_MPU_OPP1G_UV),
 
         /* L3 OPP1 - OPP50 */
-        OPP_INITIALIZER("l3_main", true, 100000000, 1000000),
+        OPP_INITIALIZER("l3_main", true, 100000000, OMAP3630_VDD_CORE_OPP50_UV),
         /* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */
-        OPP_INITIALIZER("l3_main", true, 200000000, 1200000),
+        OPP_INITIALIZER("l3_main", true, 200000000, OMAP3630_VDD_CORE_OPP100_UV),
 
         /* DSP OPP1 - OPP50 */
-        OPP_INITIALIZER("iva", true,  260000000, 1012500),
+        OPP_INITIALIZER("iva", true,  260000000, OMAP3630_VDD_MPU_OPP50_UV),
         /* DSP OPP2 - OPP100 */
-        OPP_INITIALIZER("iva", true,  520000000, 1200000),
+        OPP_INITIALIZER("iva", true,  520000000, OMAP3630_VDD_MPU_OPP100_UV),
         /* DSP OPP3 - OPP-Turbo */
-        OPP_INITIALIZER("iva", false, 660000000, 1325000),
+        OPP_INITIALIZER("iva", false, 660000000, OMAP3630_VDD_MPU_OPP120_UV),
         /* DSP OPP4 - OPP-SB */
-        OPP_INITIALIZER("iva", false, 800000000, 1375000),
+        OPP_INITIALIZER("iva", false, 800000000, OMAP3630_VDD_MPU_OPP1G_UV),
 };
 
 /**
diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c
index 5030794d73f..2293ba27101 100644
--- a/arch/arm/mach-omap2/opp4xxx_data.c
+++ b/arch/arm/mach-omap2/opp4xxx_data.c
@@ -31,10 +31,10 @@
  * voltage dependent data for each VDD.
  */
 
-#define OMAP4430_VDD_MPU_OPP50_UV               930000
-#define OMAP4430_VDD_MPU_OPP100_UV              1100000
-#define OMAP4430_VDD_MPU_OPPTURBO_UV            1260000
-#define OMAP4430_VDD_MPU_OPPNITRO_UV            1350000
+#define OMAP4430_VDD_MPU_OPP50_UV               1025000
+#define OMAP4430_VDD_MPU_OPP100_UV              1200000
+#define OMAP4430_VDD_MPU_OPPTURBO_UV            1313000
+#define OMAP4430_VDD_MPU_OPPNITRO_UV            1375000
 
 struct omap_volt_data omap44xx_vdd_mpu_volt_data[] = {
         VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP50_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP50, 0xf4, 0x0c),
@@ -44,9 +44,9 @@ struct omap_volt_data omap44xx_vdd_mpu_volt_data[] = {
         VOLT_DATA_DEFINE(0, 0, 0, 0),
 };
 
-#define OMAP4430_VDD_IVA_OPP50_UV               930000
-#define OMAP4430_VDD_IVA_OPP100_UV              1100000
-#define OMAP4430_VDD_IVA_OPPTURBO_UV            1260000
+#define OMAP4430_VDD_IVA_OPP50_UV               1013000
+#define OMAP4430_VDD_IVA_OPP100_UV              1188000
+#define OMAP4430_VDD_IVA_OPPTURBO_UV            1300000
 
 struct omap_volt_data omap44xx_vdd_iva_volt_data[] = {
         VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP50_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP50, 0xf4, 0x0c),
@@ -55,8 +55,8 @@ struct omap_volt_data omap44xx_vdd_iva_volt_data[] = {
         VOLT_DATA_DEFINE(0, 0, 0, 0),
 };
 
-#define OMAP4430_VDD_CORE_OPP50_UV              930000
-#define OMAP4430_VDD_CORE_OPP100_UV             1100000
+#define OMAP4430_VDD_CORE_OPP50_UV              1025000
+#define OMAP4430_VDD_CORE_OPP100_UV             1200000
 
 struct omap_volt_data omap44xx_vdd_core_volt_data[] = {
         VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP50_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP50, 0xf4, 0x0c),
@@ -67,18 +67,24 @@ struct omap_volt_data omap44xx_vdd_core_volt_data[] = {
 
 static struct omap_opp_def __initdata omap44xx_opp_def_list[] = {
         /* MPU OPP1 - OPP50 */
-        OPP_INITIALIZER("mpu", true, 300000000, 1100000),
+        OPP_INITIALIZER("mpu", true, 300000000, OMAP4430_VDD_MPU_OPP50_UV),
         /* MPU OPP2 - OPP100 */
-        OPP_INITIALIZER("mpu", true, 600000000, 1200000),
+        OPP_INITIALIZER("mpu", true, 600000000, OMAP4430_VDD_MPU_OPP100_UV),
         /* MPU OPP3 - OPP-Turbo */
-        OPP_INITIALIZER("mpu", false, 800000000, 1260000),
+        OPP_INITIALIZER("mpu", true, 800000000, OMAP4430_VDD_MPU_OPPTURBO_UV),
         /* MPU OPP4 - OPP-SB */
-        OPP_INITIALIZER("mpu", false, 1008000000, 1350000),
+        OPP_INITIALIZER("mpu", true, 1008000000, OMAP4430_VDD_MPU_OPPNITRO_UV),
         /* L3 OPP1 - OPP50 */
-        OPP_INITIALIZER("l3_main_1", true, 100000000, 930000),
+        OPP_INITIALIZER("l3_main_1", true, 100000000, OMAP4430_VDD_CORE_OPP50_UV),
         /* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */
-        OPP_INITIALIZER("l3_main_1", true, 200000000, 1100000),
-        /* TODO: add IVA, DSP, aess, fdif, gpu */
+        OPP_INITIALIZER("l3_main_1", true, 200000000, OMAP4430_VDD_CORE_OPP100_UV),
+        /* IVA OPP1 - OPP50 */
+        OPP_INITIALIZER("iva", true, 133000000, OMAP4430_VDD_IVA_OPP50_UV),
+        /* IVA OPP2 - OPP100 */
+        OPP_INITIALIZER("iva", true, 266100000, OMAP4430_VDD_IVA_OPP100_UV),
+        /* IVA OPP3 - OPP-Turbo */
+        OPP_INITIALIZER("iva", false, 332000000, OMAP4430_VDD_IVA_OPPTURBO_UV),
+        /* TODO: add DSP, aess, fdif, gpu */
 };
 
 /**
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index b5361a1260f..0c5e3a46a3a 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -29,6 +29,7 @@
 #include <linux/delay.h>
 #include <linux/slab.h>
 #include <linux/console.h>
+#include <trace/events/power.h>
 
 #include <plat/sram.h>
 #include "clockdomain.h"
@@ -514,8 +515,14 @@ static void omap3_pm_idle(void)
         if (omap_irq_pending() || need_resched())
                 goto out;
 
+        trace_power_start(POWER_CSTATE, 1, smp_processor_id());
+        trace_cpu_idle(1, smp_processor_id());
+
         omap_sram_idle();
 
+        trace_power_end(smp_processor_id());
+        trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
+
 out:
         local_fiq_enable();
         local_irq_enable();
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index a11be81997c..49c6513e90d 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -19,12 +19,15 @@
 #include <linux/list.h>
 #include <linux/errno.h>
 #include <linux/string.h>
+#include <trace/events/power.h>
+
 #include "cm2xxx_3xxx.h"
 #include "prcm44xx.h"
 #include "cm44xx.h"
 #include "prm2xxx_3xxx.h"
 #include "prm44xx.h"
 
+#include <asm/cpu.h>
 #include <plat/cpu.h>
 #include "powerdomain.h"
 #include "clockdomain.h"
@@ -32,6 +35,8 @@
 
 #include "pm.h"
 
+#define PWRDM_TRACE_STATES_FLAG (1<<31)
+
 enum {
         PWRDM_STATE_NOW = 0,
         PWRDM_STATE_PREV,
@@ -130,8 +135,7 @@ static void _update_logic_membank_counters(struct powerdomain *pwrdm)
 static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
 {
 
-        int prev;
-        int state;
+        int prev, state, trace_state = 0;
 
         if (pwrdm == NULL)
                 return -EINVAL;
@@ -148,6 +152,17 @@ static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
                         pwrdm->state_counter[prev]++;
                 if (prev == PWRDM_POWER_RET)
                         _update_logic_membank_counters(pwrdm);
+                /*
+                 * If the power domain did not hit the desired state,
+                 * generate a trace event with both the desired and hit states
+                 */
+                if (state != prev) {
+                        trace_state = (PWRDM_TRACE_STATES_FLAG |
+                                       ((state & OMAP_POWERSTATE_MASK) << 8) |
+                                       ((prev & OMAP_POWERSTATE_MASK) << 0));
+                        trace_power_domain_target(pwrdm->name, trace_state,
+                                                  smp_processor_id());
+                }
                 break;
         default:
                 return -EINVAL;
@@ -406,8 +421,13 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
         pr_debug("powerdomain: setting next powerstate for %s to %0x\n",
                  pwrdm->name, pwrst);
 
-        if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst)
+        if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst) {
+                /* Trace the pwrdm desired target state */
+                trace_power_domain_target(pwrdm->name, pwrst,
+                                          smp_processor_id());
+                /* Program the pwrdm desired target state */
                 ret = arch_pwrdm->pwrdm_set_next_pwrst(pwrdm, pwrst);
+        }
 
         return ret;
 }