diff options
| author | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2011-09-01 03:16:42 -0400 |
|---|---|---|
| committer | Paolo Pisati <paolo.pisati@canonical.com> | 2012-08-17 04:18:48 -0400 |
| commit | df9526a3affef8ba00288dd76e98592069922960 (patch) | |
| tree | c05b86501d7683dc4fc1b6d46d4f06233359577f /drivers/video | |
| parent | bfa7e8a4e1a931a4f8554d28091c4da0220a2050 (diff) | |
OMAP: DSS2: HDMI: change regn definition
regn divider is currently programmed to the registers without change,
but when calculating clock frequencies it is used as regn+1.
To make this similar to how DSI handles the dividers this patch changes
the regn value to be used as such for calculations, but the value
programmed to registers is regn-1.
This simplifies the clock frequency calculations, makes it similar to
DSI, and also allows us to use regn value 0 as undefined.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video')
| -rw-r--r-- | drivers/video/omap2/dss/hdmi.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c index b585675072e..af43fb6e71c 100644 --- a/drivers/video/omap2/dss/hdmi.c +++ b/drivers/video/omap2/dss/hdmi.c | |||
| @@ -44,7 +44,7 @@ | |||
| 44 | #define HDMI_DEFAULT_REGN 15 | 44 | #define HDMI_DEFAULT_REGN 15 |
| 45 | #define HDMI_DEFAULT_REGM2 1 | 45 | #define HDMI_DEFAULT_REGM2 1 |
| 46 | #include <plat/edid.h> | 46 | #include <plat/edid.h> |
| 47 | #define HDMI_DEFAULT_REGN 15 | 47 | #define HDMI_DEFAULT_REGN 16 |
| 48 | #define HDMI_DEFAULT_REGM2 1 | 48 | #define HDMI_DEFAULT_REGM2 1 |
| 49 | 49 | ||
| 50 | static struct { | 50 | static struct { |
| @@ -191,7 +191,7 @@ static int hdmi_pll_init(enum hdmi_clk_refsel refsel, int dcofreq, | |||
| 191 | 191 | ||
| 192 | r = hdmi_read_reg(PLLCTRL_CFG1); | 192 | r = hdmi_read_reg(PLLCTRL_CFG1); |
| 193 | r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */ | 193 | r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */ |
| 194 | r = FLD_MOD(r, fmt->regn, 8, 1); /* CFG1_PLL_REGN */ | 194 | r = FLD_MOD(r, fmt->regn - 1, 8, 1); /* CFG1_PLL_REGN */ |
| 195 | 195 | ||
| 196 | hdmi_write_reg(PLLCTRL_CFG1, r); | 196 | hdmi_write_reg(PLLCTRL_CFG1, r); |
| 197 | 197 | ||
| @@ -1050,7 +1050,7 @@ static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy, | |||
| 1050 | else | 1050 | else |
| 1051 | pi->regn = dssdev->clocks.hdmi.regn; | 1051 | pi->regn = dssdev->clocks.hdmi.regn; |
| 1052 | 1052 | ||
| 1053 | refclk = clkin / (pi->regn + 1); | 1053 | refclk = clkin / pi->regn; |
| 1054 | 1054 | ||
| 1055 | /* | 1055 | /* |
| 1056 | * multiplier is pixel_clk/ref_clk | 1056 | * multiplier is pixel_clk/ref_clk |
| @@ -1076,7 +1076,7 @@ static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy, | |||
| 1076 | * is greater than 1000MHz | 1076 | * is greater than 1000MHz |
| 1077 | */ | 1077 | */ |
| 1078 | pi->dcofreq = phy > 1000 * 100; | 1078 | pi->dcofreq = phy > 1000 * 100; |
| 1079 | pi->regsd = ((pi->regm * clkin / 10) / ((pi->regn + 1) * 250) + 5) / 10; | 1079 | pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10; |
| 1080 | 1080 | ||
| 1081 | DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf); | 1081 | DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf); |
| 1082 | DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd); | 1082 | DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd); |
