diff options
| author | Andy Green <andy.green@linaro.org> | 2011-08-25 03:04:54 -0400 |
|---|---|---|
| committer | Paolo Pisati <paolo.pisati@canonical.com> | 2012-08-17 04:18:44 -0400 |
| commit | 0bb92010d4c9a2fa87329cdfd676f53bcd2d33b7 (patch) | |
| tree | 026c263cd044680122076a02af4c303d56b89816 /drivers/video | |
| parent | 764430608e504e0e84311df8a32a0068917a3a9c (diff) | |
debug dss
Signed-off-by: Andy Green <andy.green@linaro.org>
Diffstat (limited to 'drivers/video')
| -rw-r--r-- | drivers/video/omap2/dss/dsi.c | 10 | ||||
| -rw-r--r-- | drivers/video/omap2/dss/hdmi.c | 31 |
2 files changed, 28 insertions, 13 deletions
diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c index 345757cfcbe..e44b467b686 100644 --- a/drivers/video/omap2/dss/dsi.c +++ b/drivers/video/omap2/dss/dsi.c | |||
| @@ -1221,8 +1221,10 @@ static int dsi_pll_power(struct platform_device *dsidev, | |||
| 1221 | { | 1221 | { |
| 1222 | int t = 0; | 1222 | int t = 0; |
| 1223 | 1223 | ||
| 1224 | pr_err("dsi_pll_power\n"); | ||
| 1225 | |||
| 1224 | /* DSI-PLL power command 0x3 is not working */ | 1226 | /* DSI-PLL power command 0x3 is not working */ |
| 1225 | if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) && | 1227 | if (//dss_has_feature(FEAT_DSI_PLL_PWR_BUG) && |
| 1226 | state == DSI_PLL_POWER_ON_DIV) | 1228 | state == DSI_PLL_POWER_ON_DIV) |
| 1227 | state = DSI_PLL_POWER_ON_ALL; | 1229 | state = DSI_PLL_POWER_ON_ALL; |
| 1228 | 1230 | ||
| @@ -1232,7 +1234,7 @@ static int dsi_pll_power(struct platform_device *dsidev, | |||
| 1232 | /* PLL_PWR_STATUS */ | 1234 | /* PLL_PWR_STATUS */ |
| 1233 | while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) { | 1235 | while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) { |
| 1234 | if (++t > 1000) { | 1236 | if (++t > 1000) { |
| 1235 | DSSERR("Failed to set DSI PLL power mode to %d\n", | 1237 | pr_err("********** Failed to set DSI PLL power mode to %d\n", |
| 1236 | state); | 1238 | state); |
| 1237 | return -ENODEV; | 1239 | return -ENODEV; |
| 1238 | } | 1240 | } |
| @@ -1586,7 +1588,7 @@ int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk, | |||
| 1586 | int r = 0; | 1588 | int r = 0; |
| 1587 | enum dsi_pll_power_state pwstate; | 1589 | enum dsi_pll_power_state pwstate; |
| 1588 | 1590 | ||
| 1589 | DSSDBG("PLL init\n"); | 1591 | pr_err("************ PLL init\n"); |
| 1590 | 1592 | ||
| 1591 | if (dsi->vdds_dsi_reg == NULL) { | 1593 | if (dsi->vdds_dsi_reg == NULL) { |
| 1592 | struct regulator *vdds_dsi; | 1594 | struct regulator *vdds_dsi; |
| @@ -4220,7 +4222,7 @@ int omapdss_dsi_display_enable(struct omap_dss_device *dssdev) | |||
| 4220 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | 4222 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 4221 | int r = 0; | 4223 | int r = 0; |
| 4222 | 4224 | ||
| 4223 | DSSDBG("dsi_display_enable\n"); | 4225 | pr_err("dsi_display_enable\n"); |
| 4224 | 4226 | ||
| 4225 | WARN_ON(!dsi_bus_is_locked(dsidev)); | 4227 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
| 4226 | 4228 | ||
diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c index a216a173785..ae69d296bef 100644 --- a/drivers/video/omap2/dss/hdmi.c +++ b/drivers/video/omap2/dss/hdmi.c | |||
| @@ -164,7 +164,7 @@ static inline int hdmi_wait_for_bit_change(const struct hdmi_reg idx, | |||
| 164 | u32 t = 0; | 164 | u32 t = 0; |
| 165 | while (val != REG_GET(idx, b2, b1)) { | 165 | while (val != REG_GET(idx, b2, b1)) { |
| 166 | udelay(1); | 166 | udelay(1); |
| 167 | if (t++ > 10000) | 167 | if (t++ > 20000) |
| 168 | return !val; | 168 | return !val; |
| 169 | } | 169 | } |
| 170 | return val; | 170 | return val; |
| @@ -387,10 +387,15 @@ static int hdmi_wait_softreset(void) | |||
| 387 | return 0; | 387 | return 0; |
| 388 | } | 388 | } |
| 389 | 389 | ||
| 390 | static int hdmi_pll_program(struct hdmi_pll_info *fmt) | 390 | static int hdmi_pll_program(struct hdmi_pll_info *fmt) |
| 391 | { | 391 | { |
| 392 | u16 r = 0; | 392 | u16 r = 0; |
| 393 | enum hdmi_clk_refsel refsel; | 393 | enum hdmi_clk_refsel refsel; |
| 394 | |||
| 395 | /* wait for wrapper reset */ | ||
| 396 | r = hdmi_wait_softreset(); | ||
| 397 | if (r) | ||
| 398 | return r; | ||
| 394 | 399 | ||
| 395 | /* wait for wrapper reset */ | 400 | /* wait for wrapper reset */ |
| 396 | r = hdmi_wait_softreset(); | 401 | r = hdmi_wait_softreset(); |
| @@ -398,22 +403,30 @@ static int hdmi_pll_program(struct hdmi_pll_info *fmt) | |||
| 398 | return r; | 403 | return r; |
| 399 | 404 | ||
| 400 | r = hdmi_set_pll_pwr(HDMI_PLLPWRCMD_ALLOFF); | 405 | r = hdmi_set_pll_pwr(HDMI_PLLPWRCMD_ALLOFF); |
| 401 | if (r) | 406 | if (r) { |
| 407 | pr_err("hdmi_set_pll_pwr says %d\n", r); | ||
| 402 | return r; | 408 | return r; |
| 409 | } | ||
| 403 | 410 | ||
| 404 | r = hdmi_set_pll_pwr(HDMI_PLLPWRCMD_BOTHON_ALLCLKS); | 411 | r = hdmi_set_pll_pwr(HDMI_PLLPWRCMD_BOTHON_ALLCLKS); |
| 405 | if (r) | 412 | if (r) { |
| 413 | pr_err("hdmi_set_pll_pwr on says %d\n", r); | ||
| 406 | return r; | 414 | return r; |
| 415 | } | ||
| 407 | 416 | ||
| 408 | r = hdmi_pll_reset(); | 417 | r = hdmi_pll_reset(); |
| 409 | if (r) | 418 | if (r) { |
| 419 | pr_err("hdmi_pll_reset says %d\n", r); | ||
| 410 | return r; | 420 | return r; |
| 421 | } | ||
| 411 | 422 | ||
| 412 | refsel = HDMI_REFSEL_SYSCLK; | 423 | refsel = HDMI_REFSEL_SYSCLK; |
| 413 | 424 | ||
| 414 | r = hdmi_pll_init(refsel, fmt->dcofreq, fmt, fmt->regsd); | 425 | r = hdmi_pll_init(refsel, fmt->dcofreq, fmt, fmt->regsd); |
| 415 | if (r) | 426 | if (r) { |
| 427 | pr_err("hdmi_pll_init says %d\n", r); | ||
| 416 | return r; | 428 | return r; |
| 429 | } | ||
| 417 | 430 | ||
| 418 | return 0; | 431 | return 0; |
| 419 | } | 432 | } |
