diff options
author | Larry Finger <Larry.Finger@lwfinger.net> | 2011-03-27 17:19:57 -0400 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2011-04-04 16:20:01 -0400 |
commit | 324732848c42bf79988479ee1b4359e15f08154b (patch) | |
tree | c2835df869da35b84274242f3862ed5e171211be /drivers/net/wireless/rtlwifi/pci.c | |
parent | 6d2bd916afe6950b50f750cd82bbb9c6ff58611f (diff) |
rtlwifi: Remove unused/unneeded variables
Remove some unused variables and correct spelling errors.
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/rtlwifi/pci.c')
-rw-r--r-- | drivers/net/wireless/rtlwifi/pci.c | 53 |
1 files changed, 16 insertions, 37 deletions
diff --git a/drivers/net/wireless/rtlwifi/pci.c b/drivers/net/wireless/rtlwifi/pci.c index 9cd7703c2a3..efded435d59 100644 --- a/drivers/net/wireless/rtlwifi/pci.c +++ b/drivers/net/wireless/rtlwifi/pci.c | |||
@@ -113,32 +113,19 @@ static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw) | |||
113 | 113 | ||
114 | /*Set HW definition to determine if it supports ASPM. */ | 114 | /*Set HW definition to determine if it supports ASPM. */ |
115 | switch (rtlpci->const_support_pciaspm) { | 115 | switch (rtlpci->const_support_pciaspm) { |
116 | case 0:{ | 116 | case 0: |
117 | /*Not support ASPM. */ | 117 | /*Not support ASPM. */ |
118 | bool support_aspm = false; | 118 | ppsc->support_aspm = false; |
119 | ppsc->support_aspm = support_aspm; | 119 | break; |
120 | break; | 120 | case 1: |
121 | } | 121 | /*Support ASPM. */ |
122 | case 1:{ | 122 | ppsc->support_aspm = true; |
123 | /*Support ASPM. */ | 123 | ppsc->support_backdoor = true; |
124 | bool support_aspm = true; | 124 | break; |
125 | bool support_backdoor = true; | ||
126 | ppsc->support_aspm = support_aspm; | ||
127 | |||
128 | /*if(priv->oem_id == RT_CID_TOSHIBA && | ||
129 | !priv->ndis_adapter.amd_l1_patch) | ||
130 | support_backdoor = false; */ | ||
131 | |||
132 | ppsc->support_backdoor = support_backdoor; | ||
133 | |||
134 | break; | ||
135 | } | ||
136 | case 2: | 125 | case 2: |
137 | /*ASPM value set by chipset. */ | 126 | /*ASPM value set by chipset. */ |
138 | if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) { | 127 | if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) |
139 | bool support_aspm = true; | 128 | ppsc->support_aspm = true; |
140 | ppsc->support_aspm = support_aspm; | ||
141 | } | ||
142 | break; | 129 | break; |
143 | default: | 130 | default: |
144 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | 131 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, |
@@ -152,13 +139,11 @@ static bool _rtl_pci_platform_switch_device_pci_aspm( | |||
152 | u8 value) | 139 | u8 value) |
153 | { | 140 | { |
154 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | 141 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); |
155 | bool bresult = false; | ||
156 | 142 | ||
157 | value |= 0x40; | 143 | value |= 0x40; |
158 | |||
159 | pci_write_config_byte(rtlpci->pdev, 0x80, value); | 144 | pci_write_config_byte(rtlpci->pdev, 0x80, value); |
160 | 145 | ||
161 | return bresult; | 146 | return false; |
162 | } | 147 | } |
163 | 148 | ||
164 | /*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/ | 149 | /*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/ |
@@ -166,14 +151,11 @@ static bool _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value) | |||
166 | { | 151 | { |
167 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | 152 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); |
168 | u8 buffer; | 153 | u8 buffer; |
169 | bool bresult = false; | ||
170 | 154 | ||
171 | buffer = value; | 155 | buffer = value; |
172 | |||
173 | pci_write_config_byte(rtlpci->pdev, 0x81, value); | 156 | pci_write_config_byte(rtlpci->pdev, 0x81, value); |
174 | bresult = true; | ||
175 | 157 | ||
176 | return bresult; | 158 | return true; |
177 | } | 159 | } |
178 | 160 | ||
179 | /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/ | 161 | /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/ |
@@ -191,6 +173,7 @@ static void rtl_pci_disable_aspm(struct ieee80211_hw *hw) | |||
191 | u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter. | 173 | u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter. |
192 | pcibridge_linkctrlreg; | 174 | pcibridge_linkctrlreg; |
193 | u16 aspmlevel = 0; | 175 | u16 aspmlevel = 0; |
176 | u8 tmp_u1b = 0; | ||
194 | 177 | ||
195 | if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { | 178 | if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { |
196 | RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, | 179 | RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, |
@@ -204,11 +187,8 @@ static void rtl_pci_disable_aspm(struct ieee80211_hw *hw) | |||
204 | _rtl_pci_switch_clk_req(hw, 0x0); | 187 | _rtl_pci_switch_clk_req(hw, 0x0); |
205 | } | 188 | } |
206 | 189 | ||
207 | if (1) { | 190 | /*for promising device will in L0 state after an I/O. */ |
208 | /*for promising device will in L0 state after an I/O. */ | 191 | pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b); |
209 | u8 tmp_u1b; | ||
210 | pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b); | ||
211 | } | ||
212 | 192 | ||
213 | /*Set corresponding value. */ | 193 | /*Set corresponding value. */ |
214 | aspmlevel |= BIT(0) | BIT(1); | 194 | aspmlevel |= BIT(0) | BIT(1); |
@@ -224,7 +204,6 @@ static void rtl_pci_disable_aspm(struct ieee80211_hw *hw) | |||
224 | rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, pcibridge_linkctrlreg); | 204 | rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, pcibridge_linkctrlreg); |
225 | 205 | ||
226 | udelay(50); | 206 | udelay(50); |
227 | |||
228 | } | 207 | } |
229 | 208 | ||
230 | /* | 209 | /* |