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authorLarry Finger <Larry.Finger@lwfinger.net>2010-12-08 12:12:31 -0500
committerJohn W. Linville <linville@tuxdriver.com>2010-12-15 16:17:49 -0500
commit0c8173385e549f95cd80c3fff5aab87b4f881d8d (patch)
treeeb818f70ed027eecbc5e170b046aa0d785168d43 /drivers/net/wireless/rtlwifi/pci.c
parent412b31334b831a8c2909afaca017c5a236ac2dd0 (diff)
rtl8192ce: Add new driver
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/rtlwifi/pci.c')
-rw-r--r--drivers/net/wireless/rtlwifi/pci.c1933
1 files changed, 1933 insertions, 0 deletions
diff --git a/drivers/net/wireless/rtlwifi/pci.c b/drivers/net/wireless/rtlwifi/pci.c
new file mode 100644
index 00000000000..bf3b5748ee1
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/pci.c
@@ -0,0 +1,1933 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "core.h"
31#include "wifi.h"
32#include "pci.h"
33#include "base.h"
34#include "ps.h"
35
36static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
37 INTEL_VENDOR_ID,
38 ATI_VENDOR_ID,
39 AMD_VENDOR_ID,
40 SIS_VENDOR_ID
41};
42
43/* Update PCI dependent default settings*/
44static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
45{
46 struct rtl_priv *rtlpriv = rtl_priv(hw);
47 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
48 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
49 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
50 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
51
52 ppsc->reg_rfps_level = 0;
53 ppsc->b_support_aspm = 0;
54
55 /*Update PCI ASPM setting */
56 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
57 switch (rtlpci->const_pci_aspm) {
58 case 0:
59 /*No ASPM */
60 break;
61
62 case 1:
63 /*ASPM dynamically enabled/disable. */
64 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
65 break;
66
67 case 2:
68 /*ASPM with Clock Req dynamically enabled/disable. */
69 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
70 RT_RF_OFF_LEVL_CLK_REQ);
71 break;
72
73 case 3:
74 /*
75 * Always enable ASPM and Clock Req
76 * from initialization to halt.
77 * */
78 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
79 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
80 RT_RF_OFF_LEVL_CLK_REQ);
81 break;
82
83 case 4:
84 /*
85 * Always enable ASPM without Clock Req
86 * from initialization to halt.
87 * */
88 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
89 RT_RF_OFF_LEVL_CLK_REQ);
90 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
91 break;
92 }
93
94 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
95
96 /*Update Radio OFF setting */
97 switch (rtlpci->const_hwsw_rfoff_d3) {
98 case 1:
99 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
100 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
101 break;
102
103 case 2:
104 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
105 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
106 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
107 break;
108
109 case 3:
110 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
111 break;
112 }
113
114 /*Set HW definition to determine if it supports ASPM. */
115 switch (rtlpci->const_support_pciaspm) {
116 case 0:{
117 /*Not support ASPM. */
118 bool b_support_aspm = false;
119 ppsc->b_support_aspm = b_support_aspm;
120 break;
121 }
122 case 1:{
123 /*Support ASPM. */
124 bool b_support_aspm = true;
125 bool b_support_backdoor = true;
126 ppsc->b_support_aspm = b_support_aspm;
127
128 /*if(priv->oem_id == RT_CID_TOSHIBA &&
129 !priv->ndis_adapter.amd_l1_patch)
130 b_support_backdoor = false; */
131
132 ppsc->b_support_backdoor = b_support_backdoor;
133
134 break;
135 }
136 case 2:
137 /*ASPM value set by chipset. */
138 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) {
139 bool b_support_aspm = true;
140 ppsc->b_support_aspm = b_support_aspm;
141 }
142 break;
143 default:
144 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
145 ("switch case not process\n"));
146 break;
147 }
148}
149
150static bool _rtl_pci_platform_switch_device_pci_aspm(
151 struct ieee80211_hw *hw,
152 u8 value)
153{
154 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
155 bool bresult = false;
156
157 value |= 0x40;
158
159 pci_write_config_byte(rtlpci->pdev, 0x80, value);
160
161 return bresult;
162}
163
164/*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
165static bool _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
166{
167 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
168 u8 buffer;
169 bool bresult = false;
170
171 buffer = value;
172
173 pci_write_config_byte(rtlpci->pdev, 0x81, value);
174 bresult = true;
175
176 return bresult;
177}
178
179/*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
180static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
181{
182 struct rtl_priv *rtlpriv = rtl_priv(hw);
183 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
184 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
185 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
186 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
187 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
188 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
189 /*Retrieve original configuration settings. */
190 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
191 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
192 pcibridge_linkctrlreg;
193 u16 aspmlevel = 0;
194
195 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
196 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
197 ("PCI(Bridge) UNKNOWN.\n"));
198
199 return;
200 }
201
202 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
203 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
204 _rtl_pci_switch_clk_req(hw, 0x0);
205 }
206
207 if (1) {
208 /*for promising device will in L0 state after an I/O. */
209 u8 tmp_u1b;
210 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
211 }
212
213 /*Set corresponding value. */
214 aspmlevel |= BIT(0) | BIT(1);
215 linkctrl_reg &= ~aspmlevel;
216 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
217
218 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
219 udelay(50);
220
221 /*4 Disable Pci Bridge ASPM */
222 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
223 pcicfg_addrport + (num4bytes << 2));
224 rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, pcibridge_linkctrlreg);
225
226 udelay(50);
227
228}
229
230/*
231 *Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
232 *power saving We should follow the sequence to enable
233 *RTL8192SE first then enable Pci Bridge ASPM
234 *or the system will show bluescreen.
235 */
236static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
237{
238 struct rtl_priv *rtlpriv = rtl_priv(hw);
239 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
240 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
241 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
242 u8 pcibridge_busnum = pcipriv->ndis_adapter.pcibridge_busnum;
243 u8 pcibridge_devnum = pcipriv->ndis_adapter.pcibridge_devnum;
244 u8 pcibridge_funcnum = pcipriv->ndis_adapter.pcibridge_funcnum;
245 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
246 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
247 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
248 u16 aspmlevel;
249 u8 u_pcibridge_aspmsetting;
250 u8 u_device_aspmsetting;
251
252 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
253 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
254 ("PCI(Bridge) UNKNOWN.\n"));
255 return;
256 }
257
258 /*4 Enable Pci Bridge ASPM */
259 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
260 pcicfg_addrport + (num4bytes << 2));
261
262 u_pcibridge_aspmsetting =
263 pcipriv->ndis_adapter.pcibridge_linkctrlreg |
264 rtlpci->const_hostpci_aspm_setting;
265
266 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
267 u_pcibridge_aspmsetting &= ~BIT(0);
268
269 rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, u_pcibridge_aspmsetting);
270
271 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
272 ("PlatformEnableASPM():PciBridge busnumber[%x], "
273 "DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n",
274 pcibridge_busnum, pcibridge_devnum, pcibridge_funcnum,
275 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
276 u_pcibridge_aspmsetting));
277
278 udelay(50);
279
280 /*Get ASPM level (with/without Clock Req) */
281 aspmlevel = rtlpci->const_devicepci_aspm_setting;
282 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
283
284 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
285 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
286
287 u_device_aspmsetting |= aspmlevel;
288
289 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
290
291 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
292 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
293 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
294 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
295 }
296 udelay(200);
297}
298
299static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
300{
301 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
302 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
303
304 bool status = false;
305 u8 offset_e0;
306 unsigned offset_e4;
307
308 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
309 pcicfg_addrport + 0xE0);
310 rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, 0xA0);
311
312 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
313 pcicfg_addrport + 0xE0);
314 rtl_pci_raw_read_port_uchar(PCI_CONF_DATA, &offset_e0);
315
316 if (offset_e0 == 0xA0) {
317 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
318 pcicfg_addrport + 0xE4);
319 rtl_pci_raw_read_port_ulong(PCI_CONF_DATA, &offset_e4);
320 if (offset_e4 & BIT(23))
321 status = true;
322 }
323
324 return status;
325}
326
327static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
328{
329 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
330 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
331 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
332 u8 linkctrl_reg;
333 u8 num4bBytes;
334
335 num4bBytes = (capabilityoffset + 0x10) / 4;
336
337 /*Read Link Control Register */
338 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
339 pcicfg_addrport + (num4bBytes << 2));
340 rtl_pci_raw_read_port_uchar(PCI_CONF_DATA, &linkctrl_reg);
341
342 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
343}
344
345static void rtl_pci_parse_configuration(struct pci_dev *pdev,
346 struct ieee80211_hw *hw)
347{
348 struct rtl_priv *rtlpriv = rtl_priv(hw);
349 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
350
351 u8 tmp;
352 int pos;
353 u8 linkctrl_reg;
354
355 /*Link Control Register */
356 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
357 pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &linkctrl_reg);
358 pcipriv->ndis_adapter.linkctrl_reg = linkctrl_reg;
359
360 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
361 ("Link Control Register =%x\n",
362 pcipriv->ndis_adapter.linkctrl_reg));
363
364 pci_read_config_byte(pdev, 0x98, &tmp);
365 tmp |= BIT(4);
366 pci_write_config_byte(pdev, 0x98, tmp);
367
368 tmp = 0x17;
369 pci_write_config_byte(pdev, 0x70f, tmp);
370}
371
372static void _rtl_pci_initialize_adapter_common(struct ieee80211_hw *hw)
373{
374 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
375
376 _rtl_pci_update_default_setting(hw);
377
378 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
379 /*Always enable ASPM & Clock Req. */
380 rtl_pci_enable_aspm(hw);
381 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
382 }
383
384}
385
386static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
387{
388 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
389
390 /*close ASPM for AMD defaultly */
391 rtlpci->const_amdpci_aspm = 0;
392
393 /*
394 * ASPM PS mode.
395 * 0 - Disable ASPM,
396 * 1 - Enable ASPM without Clock Req,
397 * 2 - Enable ASPM with Clock Req,
398 * 3 - Alwyas Enable ASPM with Clock Req,
399 * 4 - Always Enable ASPM without Clock Req.
400 * set defult to RTL8192CE:3 RTL8192E:2
401 * */
402 rtlpci->const_pci_aspm = 3;
403
404 /*Setting for PCI-E device */
405 rtlpci->const_devicepci_aspm_setting = 0x03;
406
407 /*Setting for PCI-E bridge */
408 rtlpci->const_hostpci_aspm_setting = 0x02;
409
410 /*
411 * In Hw/Sw Radio Off situation.
412 * 0 - Default,
413 * 1 - From ASPM setting without low Mac Pwr,
414 * 2 - From ASPM setting with low Mac Pwr,
415 * 3 - Bus D3
416 * set default to RTL8192CE:0 RTL8192SE:2
417 */
418 rtlpci->const_hwsw_rfoff_d3 = 0;
419
420 /*
421 * This setting works for those device with
422 * backdoor ASPM setting such as EPHY setting.
423 * 0 - Not support ASPM,
424 * 1 - Support ASPM,
425 * 2 - According to chipset.
426 */
427 rtlpci->const_support_pciaspm = 1;
428
429 _rtl_pci_initialize_adapter_common(hw);
430}
431
432static void _rtl_pci_io_handler_init(struct device *dev,
433 struct ieee80211_hw *hw)
434{
435 struct rtl_priv *rtlpriv = rtl_priv(hw);
436
437 rtlpriv->io.dev = dev;
438
439 rtlpriv->io.write8_async = pci_write8_async;
440 rtlpriv->io.write16_async = pci_write16_async;
441 rtlpriv->io.write32_async = pci_write32_async;
442
443 rtlpriv->io.read8_sync = pci_read8_sync;
444 rtlpriv->io.read16_sync = pci_read16_sync;
445 rtlpriv->io.read32_sync = pci_read32_sync;
446
447}
448
449static void _rtl_pci_io_handler_release(struct ieee80211_hw *hw)
450{
451}
452
453static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
454{
455 struct rtl_priv *rtlpriv = rtl_priv(hw);
456 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
457
458 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
459
460 while (skb_queue_len(&ring->queue)) {
461 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
462 struct sk_buff *skb;
463 struct ieee80211_tx_info *info;
464
465 u8 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) entry, true,
466 HW_DESC_OWN);
467
468 /*
469 *beacon packet will only use the first
470 *descriptor defautly,and the own may not
471 *be cleared by the hardware
472 */
473 if (own)
474 return;
475 ring->idx = (ring->idx + 1) % ring->entries;
476
477 skb = __skb_dequeue(&ring->queue);
478 pci_unmap_single(rtlpci->pdev,
479 le32_to_cpu(rtlpriv->cfg->ops->
480 get_desc((u8 *) entry, true,
481 HW_DESC_TXBUFF_ADDR)),
482 skb->len, PCI_DMA_TODEVICE);
483
484 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
485 ("new ring->idx:%d, "
486 "free: skb_queue_len:%d, free: seq:%x\n",
487 ring->idx,
488 skb_queue_len(&ring->queue),
489 *(u16 *) (skb->data + 22)));
490
491 info = IEEE80211_SKB_CB(skb);
492 ieee80211_tx_info_clear_status(info);
493
494 info->flags |= IEEE80211_TX_STAT_ACK;
495 /*info->status.rates[0].count = 1; */
496
497 ieee80211_tx_status_irqsafe(hw, skb);
498
499 if ((ring->entries - skb_queue_len(&ring->queue))
500 == 2) {
501
502 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
503 ("more desc left, wake"
504 "skb_queue@%d,ring->idx = %d,"
505 "skb_queue_len = 0x%d\n",
506 prio, ring->idx,
507 skb_queue_len(&ring->queue)));
508
509 ieee80211_wake_queue(hw,
510 skb_get_queue_mapping
511 (skb));
512 }
513
514 skb = NULL;
515 }
516
517 if (((rtlpriv->link_info.num_rx_inperiod +
518 rtlpriv->link_info.num_tx_inperiod) > 8) ||
519 (rtlpriv->link_info.num_rx_inperiod > 2)) {
520 rtl_lps_leave(hw);
521 }
522}
523
524static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
525{
526 struct rtl_priv *rtlpriv = rtl_priv(hw);
527 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
528 int rx_queue_idx = RTL_PCI_RX_MPDU_QUEUE;
529
530 struct ieee80211_rx_status rx_status = { 0 };
531 unsigned int count = rtlpci->rxringcount;
532 u8 own;
533 u8 tmp_one;
534 u32 bufferaddress;
535 bool unicast = false;
536
537 struct rtl_stats stats = {
538 .signal = 0,
539 .noise = -98,
540 .rate = 0,
541 };
542
543 /*RX NORMAL PKT */
544 while (count--) {
545 /*rx descriptor */
546 struct rtl_rx_desc *pdesc = &rtlpci->rx_ring[rx_queue_idx].desc[
547 rtlpci->rx_ring[rx_queue_idx].idx];
548 /*rx pkt */
549 struct sk_buff *skb = rtlpci->rx_ring[rx_queue_idx].rx_buf[
550 rtlpci->rx_ring[rx_queue_idx].idx];
551
552 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
553 false, HW_DESC_OWN);
554
555 if (own) {
556 /*wait data to be filled by hardware */
557 return;
558 } else {
559 struct ieee80211_hdr *hdr;
560 u16 fc;
561 struct sk_buff *new_skb = NULL;
562
563 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
564 &rx_status,
565 (u8 *) pdesc, skb);
566
567 pci_unmap_single(rtlpci->pdev,
568 *((dma_addr_t *) skb->cb),
569 rtlpci->rxbuffersize,
570 PCI_DMA_FROMDEVICE);
571
572 skb_put(skb, rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
573 false,
574 HW_DESC_RXPKT_LEN));
575 skb_reserve(skb,
576 stats.rx_drvinfo_size + stats.rx_bufshift);
577
578 /*
579 *NOTICE This can not be use for mac80211,
580 *this is done in mac80211 code,
581 *if you done here sec DHCP will fail
582 *skb_trim(skb, skb->len - 4);
583 */
584
585 hdr = (struct ieee80211_hdr *)(skb->data);
586 fc = le16_to_cpu(hdr->frame_control);
587
588 if (!stats.b_crc) {
589 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status,
590 sizeof(rx_status));
591
592 if (is_broadcast_ether_addr(hdr->addr1))
593 ;/*TODO*/
594 else {
595 if (is_multicast_ether_addr(hdr->addr1))
596 ;/*TODO*/
597 else {
598 unicast = true;
599 rtlpriv->stats.rxbytesunicast +=
600 skb->len;
601 }
602 }
603
604 rtl_is_special_data(hw, skb, false);
605
606 if (ieee80211_is_data(fc)) {
607 rtlpriv->cfg->ops->led_control(hw,
608 LED_CTL_RX);
609
610 if (unicast)
611 rtlpriv->link_info.
612 num_rx_inperiod++;
613 }
614
615 if (unlikely(!rtl_action_proc(hw, skb, false)))
616 dev_kfree_skb_any(skb);
617 else
618 ieee80211_rx_irqsafe(hw, skb);
619 } else {
620 dev_kfree_skb_any(skb);
621 }
622
623 if (((rtlpriv->link_info.num_rx_inperiod +
624 rtlpriv->link_info.num_tx_inperiod) > 8) ||
625 (rtlpriv->link_info.num_rx_inperiod > 2)) {
626 rtl_lps_leave(hw);
627 }
628
629 new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
630 if (unlikely(!new_skb)) {
631 RT_TRACE(rtlpriv, (COMP_INTR | COMP_RECV),
632 DBG_DMESG,
633 ("can't alloc skb for rx\n"));
634 goto done;
635 }
636 skb = new_skb;
637 /*skb->dev = dev; */
638
639 rtlpci->rx_ring[rx_queue_idx].rx_buf[rtlpci->
640 rx_ring
641 [rx_queue_idx].
642 idx] = skb;
643 *((dma_addr_t *) skb->cb) =
644 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
645 rtlpci->rxbuffersize,
646 PCI_DMA_FROMDEVICE);
647
648 }
649done:
650 bufferaddress = cpu_to_le32(*((dma_addr_t *) skb->cb));
651 tmp_one = 1;
652 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, false,
653 HW_DESC_RXBUFF_ADDR,
654 (u8 *)&bufferaddress);
655 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false, HW_DESC_RXOWN,
656 (u8 *)&tmp_one);
657 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
658 HW_DESC_RXPKT_LEN,
659 (u8 *)&rtlpci->rxbuffersize);
660
661 if (rtlpci->rx_ring[rx_queue_idx].idx ==
662 rtlpci->rxringcount - 1)
663 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
664 HW_DESC_RXERO,
665 (u8 *)&tmp_one);
666
667 rtlpci->rx_ring[rx_queue_idx].idx =
668 (rtlpci->rx_ring[rx_queue_idx].idx + 1) %
669 rtlpci->rxringcount;
670 }
671
672}
673
674void _rtl_pci_tx_interrupt(struct ieee80211_hw *hw)
675{
676 struct rtl_priv *rtlpriv = rtl_priv(hw);
677 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
678 int prio;
679
680 for (prio = 0; prio < RTL_PCI_MAX_TX_QUEUE_COUNT; prio++) {
681 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
682
683 while (skb_queue_len(&ring->queue)) {
684 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
685 struct sk_buff *skb;
686 struct ieee80211_tx_info *info;
687 u8 own;
688
689 /*
690 *beacon packet will only use the first
691 *descriptor defautly, and the own may not
692 *be cleared by the hardware, and
693 *beacon will free in prepare beacon
694 */
695 if (prio == BEACON_QUEUE || prio == TXCMD_QUEUE ||
696 prio == HCCA_QUEUE)
697 break;
698
699 own = (u8)rtlpriv->cfg->ops->get_desc((u8 *)entry,
700 true,
701 HW_DESC_OWN);
702
703 if (own)
704 break;
705
706 skb = __skb_dequeue(&ring->queue);
707 pci_unmap_single(rtlpci->pdev,
708 le32_to_cpu(rtlpriv->cfg->ops->
709 get_desc((u8 *) entry,
710 true,
711 HW_DESC_TXBUFF_ADDR)),
712 skb->len, PCI_DMA_TODEVICE);
713
714 ring->idx = (ring->idx + 1) % ring->entries;
715
716 info = IEEE80211_SKB_CB(skb);
717 ieee80211_tx_info_clear_status(info);
718
719 info->flags |= IEEE80211_TX_STAT_ACK;
720 /*info->status.rates[0].count = 1; */
721
722 ieee80211_tx_status_irqsafe(hw, skb);
723
724 if ((ring->entries - skb_queue_len(&ring->queue))
725 == 2 && prio != BEACON_QUEUE) {
726 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
727 ("more desc left, wake "
728 "skb_queue@%d,ring->idx = %d,"
729 "skb_queue_len = 0x%d\n",
730 prio, ring->idx,
731 skb_queue_len(&ring->queue)));
732
733 ieee80211_wake_queue(hw,
734 skb_get_queue_mapping
735 (skb));
736 }
737
738 skb = NULL;
739 }
740 }
741}
742
743static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
744{
745 struct ieee80211_hw *hw = dev_id;
746 struct rtl_priv *rtlpriv = rtl_priv(hw);
747 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
748 unsigned long flags;
749 u32 inta = 0;
750 u32 intb = 0;
751
752 if (rtlpci->irq_enabled == 0)
753 return IRQ_HANDLED;
754
755 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
756
757 /*read ISR: 4/8bytes */
758 rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb);
759
760 /*Shared IRQ or HW disappared */
761 if (!inta || inta == 0xffff)
762 goto done;
763
764 /*<1> beacon related */
765 if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) {
766 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
767 ("beacon ok interrupt!\n"));
768 }
769
770 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) {
771 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
772 ("beacon err interrupt!\n"));
773 }
774
775 if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) {
776 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
777 ("beacon interrupt!\n"));
778 }
779
780 if (inta & rtlpriv->cfg->maps[RTL_IMR_BcnInt]) {
781 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
782 ("prepare beacon for interrupt!\n"));
783 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
784 }
785
786 /*<3> Tx related */
787 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
788 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, ("IMR_TXFOVW!\n"));
789
790 if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
791 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
792 ("Manage ok interrupt!\n"));
793 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
794 }
795
796 if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
797 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
798 ("HIGH_QUEUE ok interrupt!\n"));
799 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
800 }
801
802 if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
803 rtlpriv->link_info.num_tx_inperiod++;
804
805 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
806 ("BK Tx OK interrupt!\n"));
807 _rtl_pci_tx_isr(hw, BK_QUEUE);
808 }
809
810 if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
811 rtlpriv->link_info.num_tx_inperiod++;
812
813 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
814 ("BE TX OK interrupt!\n"));
815 _rtl_pci_tx_isr(hw, BE_QUEUE);
816 }
817
818 if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
819 rtlpriv->link_info.num_tx_inperiod++;
820
821 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
822 ("VI TX OK interrupt!\n"));
823 _rtl_pci_tx_isr(hw, VI_QUEUE);
824 }
825
826 if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
827 rtlpriv->link_info.num_tx_inperiod++;
828
829 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
830 ("Vo TX OK interrupt!\n"));
831 _rtl_pci_tx_isr(hw, VO_QUEUE);
832 }
833
834 /*<2> Rx related */
835 if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
836 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, ("Rx ok interrupt!\n"));
837 tasklet_schedule(&rtlpriv->works.irq_tasklet);
838 }
839
840 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
841 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
842 ("rx descriptor unavailable!\n"));
843 tasklet_schedule(&rtlpriv->works.irq_tasklet);
844 }
845
846 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
847 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, ("rx overflow !\n"));
848 tasklet_schedule(&rtlpriv->works.irq_tasklet);
849 }
850
851 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
852 return IRQ_HANDLED;
853
854done:
855 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
856 return IRQ_HANDLED;
857}
858
859static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
860{
861 _rtl_pci_rx_interrupt(hw);
862}
863
864static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
865{
866 struct rtl_priv *rtlpriv = rtl_priv(hw);
867 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
868 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
869 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
870 struct ieee80211_hdr *hdr = NULL;
871 struct ieee80211_tx_info *info = NULL;
872 struct sk_buff *pskb = NULL;
873 struct rtl_tx_desc *pdesc = NULL;
874 unsigned int queue_index;
875 u8 temp_one = 1;
876
877 ring = &rtlpci->tx_ring[BEACON_QUEUE];
878 pskb = __skb_dequeue(&ring->queue);
879 if (pskb)
880 kfree_skb(pskb);
881
882 /*NB: the beacon data buffer must be 32-bit aligned. */
883 pskb = ieee80211_beacon_get(hw, mac->vif);
884 if (pskb == NULL)
885 return;
886 hdr = (struct ieee80211_hdr *)(pskb->data);
887 info = IEEE80211_SKB_CB(pskb);
888
889 queue_index = BEACON_QUEUE;
890
891 pdesc = &ring->desc[0];
892 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
893 info, pskb, queue_index);
894
895 __skb_queue_tail(&ring->queue, pskb);
896
897 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, true, HW_DESC_OWN,
898 (u8 *)&temp_one);
899
900 return;
901}
902
903static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
904{
905 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
906 u8 i;
907
908 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
909 rtlpci->txringcount[i] = RT_TXDESC_NUM;
910
911 /*
912 *we just alloc 2 desc for beacon queue,
913 *because we just need first desc in hw beacon.
914 */
915 rtlpci->txringcount[BEACON_QUEUE] = 2;
916
917 /*
918 *BE queue need more descriptor for performance
919 *consideration or, No more tx desc will happen,
920 *and may cause mac80211 mem leakage.
921 */
922 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
923
924 rtlpci->rxbuffersize = 9100; /*2048/1024; */
925 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */
926}
927
928static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
929 struct pci_dev *pdev)
930{
931 struct rtl_priv *rtlpriv = rtl_priv(hw);
932 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
933 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
934 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
935 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
936
937 rtlpci->up_first_time = true;
938 rtlpci->being_init_adapter = false;
939
940 rtlhal->hw = hw;
941 rtlpci->pdev = pdev;
942
943 ppsc->b_inactiveps = false;
944 ppsc->b_leisure_ps = true;
945 ppsc->b_fwctrl_lps = true;
946 ppsc->b_reg_fwctrl_lps = 3;
947 ppsc->reg_max_lps_awakeintvl = 5;
948
949 if (ppsc->b_reg_fwctrl_lps == 1)
950 ppsc->fwctrl_psmode = FW_PS_MIN_MODE;
951 else if (ppsc->b_reg_fwctrl_lps == 2)
952 ppsc->fwctrl_psmode = FW_PS_MAX_MODE;
953 else if (ppsc->b_reg_fwctrl_lps == 3)
954 ppsc->fwctrl_psmode = FW_PS_DTIM_MODE;
955
956 /*Tx/Rx related var */
957 _rtl_pci_init_trx_var(hw);
958
959 /*IBSS*/ mac->beacon_interval = 100;
960
961 /*AMPDU*/ mac->min_space_cfg = 0;
962 mac->max_mss_density = 0;
963 /*set sane AMPDU defaults */
964 mac->current_ampdu_density = 7;
965 mac->current_ampdu_factor = 3;
966
967 /*QOS*/ rtlpci->acm_method = eAcmWay2_SW;
968
969 /*task */
970 tasklet_init(&rtlpriv->works.irq_tasklet,
971 (void (*)(unsigned long))_rtl_pci_irq_tasklet,
972 (unsigned long)hw);
973 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
974 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
975 (unsigned long)hw);
976}
977
978static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
979 unsigned int prio, unsigned int entries)
980{
981 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
982 struct rtl_priv *rtlpriv = rtl_priv(hw);
983 struct rtl_tx_desc *ring;
984 dma_addr_t dma;
985 u32 nextdescaddress;
986 int i;
987
988 ring = pci_alloc_consistent(rtlpci->pdev,
989 sizeof(*ring) * entries, &dma);
990
991 if (!ring || (unsigned long)ring & 0xFF) {
992 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
993 ("Cannot allocate TX ring (prio = %d)\n", prio));
994 return -ENOMEM;
995 }
996
997 memset(ring, 0, sizeof(*ring) * entries);
998 rtlpci->tx_ring[prio].desc = ring;
999 rtlpci->tx_ring[prio].dma = dma;
1000 rtlpci->tx_ring[prio].idx = 0;
1001 rtlpci->tx_ring[prio].entries = entries;
1002 skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1003
1004 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1005 ("queue:%d, ring_addr:%p\n", prio, ring));
1006
1007 for (i = 0; i < entries; i++) {
1008 nextdescaddress = cpu_to_le32((u32) dma +
1009 ((i + 1) % entries) *
1010 sizeof(*ring));
1011
1012 rtlpriv->cfg->ops->set_desc((u8 *)&(ring[i]),
1013 true, HW_DESC_TX_NEXTDESC_ADDR,
1014 (u8 *)&nextdescaddress);
1015 }
1016
1017 return 0;
1018}
1019
1020static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw)
1021{
1022 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1023 struct rtl_priv *rtlpriv = rtl_priv(hw);
1024 struct rtl_rx_desc *entry = NULL;
1025 int i, rx_queue_idx;
1026 u8 tmp_one = 1;
1027
1028 /*
1029 *rx_queue_idx 0:RX_MPDU_QUEUE
1030 *rx_queue_idx 1:RX_CMD_QUEUE
1031 */
1032 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1033 rx_queue_idx++) {
1034 rtlpci->rx_ring[rx_queue_idx].desc =
1035 pci_alloc_consistent(rtlpci->pdev,
1036 sizeof(*rtlpci->rx_ring[rx_queue_idx].
1037 desc) * rtlpci->rxringcount,
1038 &rtlpci->rx_ring[rx_queue_idx].dma);
1039
1040 if (!rtlpci->rx_ring[rx_queue_idx].desc ||
1041 (unsigned long)rtlpci->rx_ring[rx_queue_idx].desc & 0xFF) {
1042 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1043 ("Cannot allocate RX ring\n"));
1044 return -ENOMEM;
1045 }
1046
1047 memset(rtlpci->rx_ring[rx_queue_idx].desc, 0,
1048 sizeof(*rtlpci->rx_ring[rx_queue_idx].desc) *
1049 rtlpci->rxringcount);
1050
1051 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1052
1053 for (i = 0; i < rtlpci->rxringcount; i++) {
1054 struct sk_buff *skb =
1055 dev_alloc_skb(rtlpci->rxbuffersize);
1056 u32 bufferaddress;
1057 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1058 if (!skb)
1059 return 0;
1060
1061 /*skb->dev = dev; */
1062
1063 rtlpci->rx_ring[rx_queue_idx].rx_buf[i] = skb;
1064
1065 /*
1066 *just set skb->cb to mapping addr
1067 *for pci_unmap_single use
1068 */
1069 *((dma_addr_t *) skb->cb) =
1070 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
1071 rtlpci->rxbuffersize,
1072 PCI_DMA_FROMDEVICE);
1073
1074 bufferaddress = cpu_to_le32(*((dma_addr_t *)skb->cb));
1075 rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1076 HW_DESC_RXBUFF_ADDR,
1077 (u8 *)&bufferaddress);
1078 rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1079 HW_DESC_RXPKT_LEN,
1080 (u8 *)&rtlpci->
1081 rxbuffersize);
1082 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1083 HW_DESC_RXOWN,
1084 (u8 *)&tmp_one);
1085 }
1086
1087 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1088 HW_DESC_RXERO, (u8 *)&tmp_one);
1089 }
1090 return 0;
1091}
1092
1093static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1094 unsigned int prio)
1095{
1096 struct rtl_priv *rtlpriv = rtl_priv(hw);
1097 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1098 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1099
1100 while (skb_queue_len(&ring->queue)) {
1101 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
1102 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1103
1104 pci_unmap_single(rtlpci->pdev,
1105 le32_to_cpu(rtlpriv->cfg->
1106 ops->get_desc((u8 *) entry, true,
1107 HW_DESC_TXBUFF_ADDR)),
1108 skb->len, PCI_DMA_TODEVICE);
1109 kfree_skb(skb);
1110 ring->idx = (ring->idx + 1) % ring->entries;
1111 }
1112
1113 pci_free_consistent(rtlpci->pdev,
1114 sizeof(*ring->desc) * ring->entries,
1115 ring->desc, ring->dma);
1116 ring->desc = NULL;
1117}
1118
1119static void _rtl_pci_free_rx_ring(struct rtl_pci *rtlpci)
1120{
1121 int i, rx_queue_idx;
1122
1123 /*rx_queue_idx 0:RX_MPDU_QUEUE */
1124 /*rx_queue_idx 1:RX_CMD_QUEUE */
1125 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1126 rx_queue_idx++) {
1127 for (i = 0; i < rtlpci->rxringcount; i++) {
1128 struct sk_buff *skb =
1129 rtlpci->rx_ring[rx_queue_idx].rx_buf[i];
1130 if (!skb)
1131 continue;
1132
1133 pci_unmap_single(rtlpci->pdev,
1134 *((dma_addr_t *) skb->cb),
1135 rtlpci->rxbuffersize,
1136 PCI_DMA_FROMDEVICE);
1137 kfree_skb(skb);
1138 }
1139
1140 pci_free_consistent(rtlpci->pdev,
1141 sizeof(*rtlpci->rx_ring[rx_queue_idx].
1142 desc) * rtlpci->rxringcount,
1143 rtlpci->rx_ring[rx_queue_idx].desc,
1144 rtlpci->rx_ring[rx_queue_idx].dma);
1145 rtlpci->rx_ring[rx_queue_idx].desc = NULL;
1146 }
1147}
1148
1149static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1150{
1151 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1152 int ret;
1153 int i;
1154
1155 ret = _rtl_pci_init_rx_ring(hw);
1156 if (ret)
1157 return ret;
1158
1159 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1160 ret = _rtl_pci_init_tx_ring(hw, i,
1161 rtlpci->txringcount[i]);
1162 if (ret)
1163 goto err_free_rings;
1164 }
1165
1166 return 0;
1167
1168err_free_rings:
1169 _rtl_pci_free_rx_ring(rtlpci);
1170
1171 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1172 if (rtlpci->tx_ring[i].desc)
1173 _rtl_pci_free_tx_ring(hw, i);
1174
1175 return 1;
1176}
1177
1178static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1179{
1180 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1181 u32 i;
1182
1183 /*free rx rings */
1184 _rtl_pci_free_rx_ring(rtlpci);
1185
1186 /*free tx rings */
1187 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1188 _rtl_pci_free_tx_ring(hw, i);
1189
1190 return 0;
1191}
1192
1193int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1194{
1195 struct rtl_priv *rtlpriv = rtl_priv(hw);
1196 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1197 int i, rx_queue_idx;
1198 unsigned long flags;
1199 u8 tmp_one = 1;
1200
1201 /*rx_queue_idx 0:RX_MPDU_QUEUE */
1202 /*rx_queue_idx 1:RX_CMD_QUEUE */
1203 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1204 rx_queue_idx++) {
1205 /*
1206 *force the rx_ring[RX_MPDU_QUEUE/
1207 *RX_CMD_QUEUE].idx to the first one
1208 */
1209 if (rtlpci->rx_ring[rx_queue_idx].desc) {
1210 struct rtl_rx_desc *entry = NULL;
1211
1212 for (i = 0; i < rtlpci->rxringcount; i++) {
1213 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1214 rtlpriv->cfg->ops->set_desc((u8 *) entry,
1215 false,
1216 HW_DESC_RXOWN,
1217 (u8 *)&tmp_one);
1218 }
1219 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1220 }
1221 }
1222
1223 /*
1224 *after reset, release previous pending packet,
1225 *and force the tx idx to the first one
1226 */
1227 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1228 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1229 if (rtlpci->tx_ring[i].desc) {
1230 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1231
1232 while (skb_queue_len(&ring->queue)) {
1233 struct rtl_tx_desc *entry =
1234 &ring->desc[ring->idx];
1235 struct sk_buff *skb =
1236 __skb_dequeue(&ring->queue);
1237
1238 pci_unmap_single(rtlpci->pdev,
1239 le32_to_cpu(rtlpriv->cfg->ops->
1240 get_desc((u8 *)
1241 entry,
1242 true,
1243 HW_DESC_TXBUFF_ADDR)),
1244 skb->len, PCI_DMA_TODEVICE);
1245 kfree_skb(skb);
1246 ring->idx = (ring->idx + 1) % ring->entries;
1247 }
1248 ring->idx = 0;
1249 }
1250 }
1251
1252 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1253
1254 return 0;
1255}
1256
1257unsigned int _rtl_mac_to_hwqueue(u16 fc,
1258 unsigned int mac80211_queue_index)
1259{
1260 unsigned int hw_queue_index;
1261
1262 if (unlikely(ieee80211_is_beacon(fc))) {
1263 hw_queue_index = BEACON_QUEUE;
1264 goto out;
1265 }
1266
1267 if (ieee80211_is_mgmt(fc)) {
1268 hw_queue_index = MGNT_QUEUE;
1269 goto out;
1270 }
1271
1272 switch (mac80211_queue_index) {
1273 case 0:
1274 hw_queue_index = VO_QUEUE;
1275 break;
1276 case 1:
1277 hw_queue_index = VI_QUEUE;
1278 break;
1279 case 2:
1280 hw_queue_index = BE_QUEUE;;
1281 break;
1282 case 3:
1283 hw_queue_index = BK_QUEUE;
1284 break;
1285 default:
1286 hw_queue_index = BE_QUEUE;
1287 RT_ASSERT(false, ("QSLT_BE queue, skb_queue:%d\n",
1288 mac80211_queue_index));
1289 break;
1290 }
1291
1292out:
1293 return hw_queue_index;
1294}
1295
1296int rtl_pci_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
1297{
1298 struct rtl_priv *rtlpriv = rtl_priv(hw);
1299 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1300 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1301 struct rtl8192_tx_ring *ring;
1302 struct rtl_tx_desc *pdesc;
1303 u8 idx;
1304 unsigned int queue_index, hw_queue;
1305 unsigned long flags;
1306 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
1307 u16 fc = le16_to_cpu(hdr->frame_control);
1308 u8 *pda_addr = hdr->addr1;
1309 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1310 /*ssn */
1311 u8 *qc = NULL;
1312 u8 tid = 0;
1313 u16 seq_number = 0;
1314 u8 own;
1315 u8 temp_one = 1;
1316
1317 if (ieee80211_is_mgmt(fc))
1318 rtl_tx_mgmt_proc(hw, skb);
1319 rtl_action_proc(hw, skb, true);
1320
1321 queue_index = skb_get_queue_mapping(skb);
1322 hw_queue = _rtl_mac_to_hwqueue(fc, queue_index);
1323
1324 if (is_multicast_ether_addr(pda_addr))
1325 rtlpriv->stats.txbytesmulticast += skb->len;
1326 else if (is_broadcast_ether_addr(pda_addr))
1327 rtlpriv->stats.txbytesbroadcast += skb->len;
1328 else
1329 rtlpriv->stats.txbytesunicast += skb->len;
1330
1331 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1332
1333 ring = &rtlpci->tx_ring[hw_queue];
1334 if (hw_queue != BEACON_QUEUE)
1335 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1336 ring->entries;
1337 else
1338 idx = 0;
1339
1340 pdesc = &ring->desc[idx];
1341 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
1342 true, HW_DESC_OWN);
1343
1344 if ((own == 1) && (hw_queue != BEACON_QUEUE)) {
1345 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1346 ("No more TX desc@%d, ring->idx = %d,"
1347 "idx = %d, skb_queue_len = 0x%d\n",
1348 hw_queue, ring->idx, idx,
1349 skb_queue_len(&ring->queue)));
1350
1351 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1352 return skb->len;
1353 }
1354
1355 /*
1356 *if(ieee80211_is_nullfunc(fc)) {
1357 * spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1358 * return 1;
1359 *}
1360 */
1361
1362 if (ieee80211_is_data_qos(fc)) {
1363 qc = ieee80211_get_qos_ctl(hdr);
1364 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
1365
1366 seq_number = mac->tids[tid].seq_number;
1367 seq_number &= IEEE80211_SCTL_SEQ;
1368 /*
1369 *hdr->seq_ctrl = hdr->seq_ctrl &
1370 *cpu_to_le16(IEEE80211_SCTL_FRAG);
1371 *hdr->seq_ctrl |= cpu_to_le16(seq_number);
1372 */
1373
1374 seq_number += 1;
1375 }
1376
1377 if (ieee80211_is_data(fc))
1378 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1379
1380 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
1381 info, skb, hw_queue);
1382
1383 __skb_queue_tail(&ring->queue, skb);
1384
1385 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, true,
1386 HW_DESC_OWN, (u8 *)&temp_one);
1387
1388 if (!ieee80211_has_morefrags(hdr->frame_control)) {
1389 if (qc)
1390 mac->tids[tid].seq_number = seq_number;
1391 }
1392
1393 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1394 hw_queue != BEACON_QUEUE) {
1395
1396 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1397 ("less desc left, stop skb_queue@%d, "
1398 "ring->idx = %d,"
1399 "idx = %d, skb_queue_len = 0x%d\n",
1400 hw_queue, ring->idx, idx,
1401 skb_queue_len(&ring->queue)));
1402
1403 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1404 }
1405
1406 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1407
1408 rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1409
1410 return 0;
1411}
1412
1413void rtl_pci_deinit(struct ieee80211_hw *hw)
1414{
1415 struct rtl_priv *rtlpriv = rtl_priv(hw);
1416 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1417
1418 _rtl_pci_deinit_trx_ring(hw);
1419
1420 synchronize_irq(rtlpci->pdev->irq);
1421 tasklet_kill(&rtlpriv->works.irq_tasklet);
1422
1423 flush_workqueue(rtlpriv->works.rtl_wq);
1424 destroy_workqueue(rtlpriv->works.rtl_wq);
1425
1426}
1427
1428int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
1429{
1430 struct rtl_priv *rtlpriv = rtl_priv(hw);
1431 int err;
1432
1433 _rtl_pci_init_struct(hw, pdev);
1434
1435 err = _rtl_pci_init_trx_ring(hw);
1436 if (err) {
1437 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1438 ("tx ring initialization failed"));
1439 return err;
1440 }
1441
1442 return 1;
1443}
1444
1445int rtl_pci_start(struct ieee80211_hw *hw)
1446{
1447 struct rtl_priv *rtlpriv = rtl_priv(hw);
1448 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1449 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1450 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1451
1452 int err;
1453
1454 rtl_pci_reset_trx_ring(hw);
1455
1456 rtlpci->driver_is_goingto_unload = false;
1457 err = rtlpriv->cfg->ops->hw_init(hw);
1458 if (err) {
1459 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1460 ("Failed to config hardware!\n"));
1461 return err;
1462 }
1463
1464 rtlpriv->cfg->ops->enable_interrupt(hw);
1465 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("enable_interrupt OK\n"));
1466
1467 rtl_init_rx_config(hw);
1468
1469 /*should after adapter start and interrupt enable. */
1470 set_hal_start(rtlhal);
1471
1472 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1473
1474 rtlpci->up_first_time = false;
1475
1476 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("OK\n"));
1477 return 0;
1478}
1479
1480void rtl_pci_stop(struct ieee80211_hw *hw)
1481{
1482 struct rtl_priv *rtlpriv = rtl_priv(hw);
1483 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1484 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1485 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1486 unsigned long flags;
1487 u8 RFInProgressTimeOut = 0;
1488
1489 /*
1490 *should before disable interrrupt&adapter
1491 *and will do it immediately.
1492 */
1493 set_hal_stop(rtlhal);
1494
1495 rtlpriv->cfg->ops->disable_interrupt(hw);
1496
1497 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1498 while (ppsc->rfchange_inprogress) {
1499 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1500 if (RFInProgressTimeOut > 100) {
1501 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1502 break;
1503 }
1504 mdelay(1);
1505 RFInProgressTimeOut++;
1506 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1507 }
1508 ppsc->rfchange_inprogress = true;
1509 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1510
1511 rtlpci->driver_is_goingto_unload = true;
1512 rtlpriv->cfg->ops->hw_disable(hw);
1513 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1514
1515 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1516 ppsc->rfchange_inprogress = false;
1517 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1518
1519 rtl_pci_enable_aspm(hw);
1520}
1521
1522static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1523 struct ieee80211_hw *hw)
1524{
1525 struct rtl_priv *rtlpriv = rtl_priv(hw);
1526 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1527 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1528 struct pci_dev *bridge_pdev = pdev->bus->self;
1529 u16 venderid;
1530 u16 deviceid;
1531 u8 revisionid;
1532 u16 irqline;
1533 u8 tmp;
1534
1535 venderid = pdev->vendor;
1536 deviceid = pdev->device;
1537 pci_read_config_byte(pdev, 0x8, &revisionid);
1538 pci_read_config_word(pdev, 0x3C, &irqline);
1539
1540 if (deviceid == RTL_PCI_8192_DID ||
1541 deviceid == RTL_PCI_0044_DID ||
1542 deviceid == RTL_PCI_0047_DID ||
1543 deviceid == RTL_PCI_8192SE_DID ||
1544 deviceid == RTL_PCI_8174_DID ||
1545 deviceid == RTL_PCI_8173_DID ||
1546 deviceid == RTL_PCI_8172_DID ||
1547 deviceid == RTL_PCI_8171_DID) {
1548 switch (revisionid) {
1549 case RTL_PCI_REVISION_ID_8192PCIE:
1550 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1551 ("8192 PCI-E is found - "
1552 "vid/did=%x/%x\n", venderid, deviceid));
1553 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1554 break;
1555 case RTL_PCI_REVISION_ID_8192SE:
1556 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1557 ("8192SE is found - "
1558 "vid/did=%x/%x\n", venderid, deviceid));
1559 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1560 break;
1561 default:
1562 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1563 ("Err: Unknown device - "
1564 "vid/did=%x/%x\n", venderid, deviceid));
1565 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1566 break;
1567
1568 }
1569 } else if (deviceid == RTL_PCI_8192CET_DID ||
1570 deviceid == RTL_PCI_8192CE_DID ||
1571 deviceid == RTL_PCI_8191CE_DID ||
1572 deviceid == RTL_PCI_8188CE_DID) {
1573 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1574 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1575 ("8192C PCI-E is found - "
1576 "vid/did=%x/%x\n", venderid, deviceid));
1577 } else {
1578 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1579 ("Err: Unknown device -"
1580 " vid/did=%x/%x\n", venderid, deviceid));
1581
1582 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1583 }
1584
1585 /*find bus info */
1586 pcipriv->ndis_adapter.busnumber = pdev->bus->number;
1587 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
1588 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
1589
1590 /*find bridge info */
1591 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
1592 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
1593 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
1594 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
1595 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1596 ("Pci Bridge Vendor is found index: %d\n",
1597 tmp));
1598 break;
1599 }
1600 }
1601
1602 if (pcipriv->ndis_adapter.pcibridge_vendor !=
1603 PCI_BRIDGE_VENDOR_UNKNOWN) {
1604 pcipriv->ndis_adapter.pcibridge_busnum =
1605 bridge_pdev->bus->number;
1606 pcipriv->ndis_adapter.pcibridge_devnum =
1607 PCI_SLOT(bridge_pdev->devfn);
1608 pcipriv->ndis_adapter.pcibridge_funcnum =
1609 PCI_FUNC(bridge_pdev->devfn);
1610 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
1611 bridge_pdev->pcie_cap;
1612 pcipriv->ndis_adapter.pcicfg_addrport =
1613 (pcipriv->ndis_adapter.pcibridge_busnum << 16) |
1614 (pcipriv->ndis_adapter.pcibridge_devnum << 11) |
1615 (pcipriv->ndis_adapter.pcibridge_funcnum << 8) | (1 << 31);
1616 pcipriv->ndis_adapter.num4bytes =
1617 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
1618
1619 rtl_pci_get_linkcontrol_field(hw);
1620
1621 if (pcipriv->ndis_adapter.pcibridge_vendor ==
1622 PCI_BRIDGE_VENDOR_AMD) {
1623 pcipriv->ndis_adapter.amd_l1_patch =
1624 rtl_pci_get_amd_l1_patch(hw);
1625 }
1626 }
1627
1628 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1629 ("pcidev busnumber:devnumber:funcnumber:"
1630 "vendor:link_ctl %d:%d:%d:%x:%x\n",
1631 pcipriv->ndis_adapter.busnumber,
1632 pcipriv->ndis_adapter.devnumber,
1633 pcipriv->ndis_adapter.funcnumber,
1634 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg));
1635
1636 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1637 ("pci_bridge busnumber:devnumber:funcnumber:vendor:"
1638 "pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
1639 pcipriv->ndis_adapter.pcibridge_busnum,
1640 pcipriv->ndis_adapter.pcibridge_devnum,
1641 pcipriv->ndis_adapter.pcibridge_funcnum,
1642 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
1643 pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
1644 pcipriv->ndis_adapter.pcibridge_linkctrlreg,
1645 pcipriv->ndis_adapter.amd_l1_patch));
1646
1647 rtl_pci_parse_configuration(pdev, hw);
1648
1649 return true;
1650}
1651
1652int __devinit rtl_pci_probe(struct pci_dev *pdev,
1653 const struct pci_device_id *id)
1654{
1655 struct ieee80211_hw *hw = NULL;
1656
1657 struct rtl_priv *rtlpriv = NULL;
1658 struct rtl_pci_priv *pcipriv = NULL;
1659 struct rtl_pci *rtlpci;
1660 unsigned long pmem_start, pmem_len, pmem_flags;
1661 int err;
1662
1663 err = pci_enable_device(pdev);
1664 if (err) {
1665 RT_ASSERT(false,
1666 ("%s : Cannot enable new PCI device\n",
1667 pci_name(pdev)));
1668 return err;
1669 }
1670
1671 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1672 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1673 RT_ASSERT(false, ("Unable to obtain 32bit DMA "
1674 "for consistent allocations\n"));
1675 pci_disable_device(pdev);
1676 return -ENOMEM;
1677 }
1678 }
1679
1680 pci_set_master(pdev);
1681
1682 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
1683 sizeof(struct rtl_priv), &rtl_ops);
1684 if (!hw) {
1685 RT_ASSERT(false,
1686 ("%s : ieee80211 alloc failed\n", pci_name(pdev)));
1687 err = -ENOMEM;
1688 goto fail1;
1689 }
1690
1691 SET_IEEE80211_DEV(hw, &pdev->dev);
1692 pci_set_drvdata(pdev, hw);
1693
1694 rtlpriv = hw->priv;
1695 pcipriv = (void *)rtlpriv->priv;
1696 pcipriv->dev.pdev = pdev;
1697
1698 /*
1699 *init dbgp flags before all
1700 *other functions, because we will
1701 *use it in other funtions like
1702 *RT_TRACE/RT_PRINT/RTL_PRINT_DATA
1703 *you can not use these macro
1704 *before this
1705 */
1706 rtl_dbgp_flag_init(hw);
1707
1708 /* MEM map */
1709 err = pci_request_regions(pdev, KBUILD_MODNAME);
1710 if (err) {
1711 RT_ASSERT(false, ("Can't obtain PCI resources\n"));
1712 return err;
1713 }
1714
1715 pmem_start = pci_resource_start(pdev, 2);
1716 pmem_len = pci_resource_len(pdev, 2);
1717 pmem_flags = pci_resource_flags(pdev, 2);
1718
1719 /*shared mem start */
1720 rtlpriv->io.pci_mem_start =
1721 (unsigned long)pci_iomap(pdev, 2, pmem_len);
1722 if (rtlpriv->io.pci_mem_start == 0) {
1723 RT_ASSERT(false, ("Can't map PCI mem\n"));
1724 goto fail2;
1725 }
1726
1727 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1728 ("mem mapped space: start: 0x%08lx len:%08lx "
1729 "flags:%08lx, after map:0x%08lx\n",
1730 pmem_start, pmem_len, pmem_flags,
1731 rtlpriv->io.pci_mem_start));
1732
1733 /* Disable Clk Request */
1734 pci_write_config_byte(pdev, 0x81, 0);
1735 /* leave D3 mode */
1736 pci_write_config_byte(pdev, 0x44, 0);
1737 pci_write_config_byte(pdev, 0x04, 0x06);
1738 pci_write_config_byte(pdev, 0x04, 0x07);
1739
1740 /* init cfg & intf_ops */
1741 rtlpriv->rtlhal.interface = INTF_PCI;
1742 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
1743 rtlpriv->intf_ops = &rtl_pci_ops;
1744
1745 /* find adapter */
1746 _rtl_pci_find_adapter(pdev, hw);
1747
1748 /* Init IO handler */
1749 _rtl_pci_io_handler_init(&pdev->dev, hw);
1750
1751 /*like read eeprom and so on */
1752 rtlpriv->cfg->ops->read_eeprom_info(hw);
1753
1754 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
1755 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1756 ("Can't init_sw_vars.\n"));
1757 goto fail3;
1758 }
1759
1760 rtlpriv->cfg->ops->init_sw_leds(hw);
1761
1762 /*aspm */
1763 rtl_pci_init_aspm(hw);
1764
1765 /* Init mac80211 sw */
1766 err = rtl_init_core(hw);
1767 if (err) {
1768 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1769 ("Can't allocate sw for mac80211.\n"));
1770 goto fail3;
1771 }
1772
1773 /* Init PCI sw */
1774 err = !rtl_pci_init(hw, pdev);
1775 if (err) {
1776 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1777 ("Failed to init PCI.\n"));
1778 goto fail3;
1779 }
1780
1781 err = ieee80211_register_hw(hw);
1782 if (err) {
1783 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1784 ("Can't register mac80211 hw.\n"));
1785 goto fail3;
1786 } else {
1787 rtlpriv->mac80211.mac80211_registered = 1;
1788 }
1789
1790 err = sysfs_create_group(&pdev->dev.kobj, &rtl_attribute_group);
1791 if (err) {
1792 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1793 ("failed to create sysfs device attributes\n"));
1794 goto fail3;
1795 }
1796
1797 /*init rfkill */
1798 rtl_init_rfkill(hw);
1799
1800 rtlpci = rtl_pcidev(pcipriv);
1801 err = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
1802 IRQF_SHARED, KBUILD_MODNAME, hw);
1803 if (err) {
1804 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1805 ("%s: failed to register IRQ handler\n",
1806 wiphy_name(hw->wiphy)));
1807 goto fail3;
1808 } else {
1809 rtlpci->irq_alloc = 1;
1810 }
1811
1812 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
1813 return 0;
1814
1815fail3:
1816 pci_set_drvdata(pdev, NULL);
1817 rtl_deinit_core(hw);
1818 _rtl_pci_io_handler_release(hw);
1819 ieee80211_free_hw(hw);
1820
1821 if (rtlpriv->io.pci_mem_start != 0)
1822 pci_iounmap(pdev, (void *)rtlpriv->io.pci_mem_start);
1823
1824fail2:
1825 pci_release_regions(pdev);
1826
1827fail1:
1828
1829 pci_disable_device(pdev);
1830
1831 return -ENODEV;
1832
1833}
1834EXPORT_SYMBOL(rtl_pci_probe);
1835
1836void rtl_pci_disconnect(struct pci_dev *pdev)
1837{
1838 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
1839 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1840 struct rtl_priv *rtlpriv = rtl_priv(hw);
1841 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
1842 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
1843
1844 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
1845
1846 sysfs_remove_group(&pdev->dev.kobj, &rtl_attribute_group);
1847
1848 /*ieee80211_unregister_hw will call ops_stop */
1849 if (rtlmac->mac80211_registered == 1) {
1850 ieee80211_unregister_hw(hw);
1851 rtlmac->mac80211_registered = 0;
1852 } else {
1853 rtl_deinit_deferred_work(hw);
1854 rtlpriv->intf_ops->adapter_stop(hw);
1855 }
1856
1857 /*deinit rfkill */
1858 rtl_deinit_rfkill(hw);
1859
1860 rtl_pci_deinit(hw);
1861 rtl_deinit_core(hw);
1862 rtlpriv->cfg->ops->deinit_sw_leds(hw);
1863 _rtl_pci_io_handler_release(hw);
1864 rtlpriv->cfg->ops->deinit_sw_vars(hw);
1865
1866 if (rtlpci->irq_alloc) {
1867 free_irq(rtlpci->pdev->irq, hw);
1868 rtlpci->irq_alloc = 0;
1869 }
1870
1871 if (rtlpriv->io.pci_mem_start != 0) {
1872 pci_iounmap(pdev, (void *)rtlpriv->io.pci_mem_start);
1873 pci_release_regions(pdev);
1874 }
1875
1876 pci_disable_device(pdev);
1877 pci_set_drvdata(pdev, NULL);
1878
1879 ieee80211_free_hw(hw);
1880}
1881EXPORT_SYMBOL(rtl_pci_disconnect);
1882
1883/***************************************
1884kernel pci power state define:
1885PCI_D0 ((pci_power_t __force) 0)
1886PCI_D1 ((pci_power_t __force) 1)
1887PCI_D2 ((pci_power_t __force) 2)
1888PCI_D3hot ((pci_power_t __force) 3)
1889PCI_D3cold ((pci_power_t __force) 4)
1890PCI_UNKNOWN ((pci_power_t __force) 5)
1891
1892This function is called when system
1893goes into suspend state mac80211 will
1894call rtl_mac_stop() from the mac80211
1895suspend function first, So there is
1896no need to call hw_disable here.
1897****************************************/
1898int rtl_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1899{
1900 pci_save_state(pdev);
1901 pci_disable_device(pdev);
1902 pci_set_power_state(pdev, PCI_D3hot);
1903
1904 return 0;
1905}
1906EXPORT_SYMBOL(rtl_pci_suspend);
1907
1908int rtl_pci_resume(struct pci_dev *pdev)
1909{
1910 int ret;
1911
1912 pci_set_power_state(pdev, PCI_D0);
1913 ret = pci_enable_device(pdev);
1914 if (ret) {
1915 RT_ASSERT(false, ("ERR: <======\n"));
1916 return ret;
1917 }
1918
1919 pci_restore_state(pdev);
1920
1921 return 0;
1922}
1923EXPORT_SYMBOL(rtl_pci_resume);
1924
1925struct rtl_intf_ops rtl_pci_ops = {
1926 .adapter_start = rtl_pci_start,
1927 .adapter_stop = rtl_pci_stop,
1928 .adapter_tx = rtl_pci_tx,
1929 .reset_trx_ring = rtl_pci_reset_trx_ring,
1930
1931 .disable_aspm = rtl_pci_disable_aspm,
1932 .enable_aspm = rtl_pci_enable_aspm,
1933};
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-25 15:19:22 -0400