aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/cassini.c
diff options
context:
space:
mode:
authorDavid S. Miller <davem@davemloft.net>2011-04-11 16:44:25 -0400
committerDavid S. Miller <davem@davemloft.net>2011-04-11 16:44:25 -0400
commit1c01a80cfec6f806246f31ff2680cd3639b30e67 (patch)
tree0b554aad2ec1da71ecf6339d4ba51617bfe1dc3c /drivers/net/cassini.c
parentc44d79950b2daa1025e62eede73e4e4a274d1ef3 (diff)
parent4a9f65f6304a00f6473e83b19c1e83caa1e42530 (diff)
Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
Conflicts: drivers/net/smsc911x.c
Diffstat (limited to 'drivers/net/cassini.c')
-rw-r--r--drivers/net/cassini.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/net/cassini.c b/drivers/net/cassini.c
index 3437613f045..143a28c666a 100644
--- a/drivers/net/cassini.c
+++ b/drivers/net/cassini.c
@@ -51,7 +51,7 @@
51 * TX has 4 queues. currently these queues are used in a round-robin 51 * TX has 4 queues. currently these queues are used in a round-robin
52 * fashion for load balancing. They can also be used for QoS. for that 52 * fashion for load balancing. They can also be used for QoS. for that
53 * to work, however, QoS information needs to be exposed down to the driver 53 * to work, however, QoS information needs to be exposed down to the driver
54 * level so that subqueues get targetted to particular transmit rings. 54 * level so that subqueues get targeted to particular transmit rings.
55 * alternatively, the queues can be configured via use of the all-purpose 55 * alternatively, the queues can be configured via use of the all-purpose
56 * ioctl. 56 * ioctl.
57 * 57 *
@@ -5165,7 +5165,7 @@ err_out_free_res:
5165 pci_release_regions(pdev); 5165 pci_release_regions(pdev);
5166 5166
5167err_write_cacheline: 5167err_write_cacheline:
5168 /* Try to restore it in case the error occured after we 5168 /* Try to restore it in case the error occurred after we
5169 * set it. 5169 * set it.
5170 */ 5170 */
5171 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, orig_cacheline_size); 5171 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, orig_cacheline_size);