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authorAlex Deucher <alexander.deucher@amd.com>2011-10-25 20:17:45 -0400
committerBrad Figg <brad.figg@canonical.com>2012-01-23 18:35:22 -0500
commit3c34c5543ec5455f40ae8ec16100b35674a38499 (patch)
treeee97ff089533d937c8a96ab58f2b16bb3d350753 /drivers/gpu/drm/radeon
parentc28f8cdac7b78ed7d3ee82230eb50964dbb1b0d6 (diff)
drm/radeon/kms/atom: rework encoder dpms
BugLink: http://bugs.launchpad.net/bugs/825777 The existing function was getting too big and complex. Break it down into a more manageable set of functions. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com> (cherry picked from commit c41384f8279f6eeecfe186976f67c2a513f3c81b) Acked-by: Seth Forshee <seth.forshee@canonical.com> Signed-off-by: Wen-chien Jesse Sung <jesse.sung@canonical.com> Signed-off-by: Tim Gardner <tim.gardner@canonical.com> Signed-off-by: Brad Figg <brad.figg@canonical.com>
Diffstat (limited to 'drivers/gpu/drm/radeon')
-rw-r--r--drivers/gpu/drm/radeon/radeon_encoders.c338
1 files changed, 186 insertions, 152 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index 310714e62a4..ab2bbd72113 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -1356,45 +1356,25 @@ atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1356} 1356}
1357 1357
1358static void 1358static void
1359radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) 1359radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1360{ 1360{
1361 struct drm_device *dev = encoder->dev; 1361 struct drm_device *dev = encoder->dev;
1362 struct radeon_device *rdev = dev->dev_private; 1362 struct radeon_device *rdev = dev->dev_private;
1363 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1363 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1364 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1365 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 1364 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1366 int index = 0; 1365 int index = 0;
1367 bool is_dig = false;
1368 bool is_dce5_dac = false;
1369 bool is_dce5_dvo = false;
1370 1366
1371 memset(&args, 0, sizeof(args)); 1367 memset(&args, 0, sizeof(args));
1372 1368
1373 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1374 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1375 radeon_encoder->active_device);
1376 switch (radeon_encoder->encoder_id) { 1369 switch (radeon_encoder->encoder_id) {
1377 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1370 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1378 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1371 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1379 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); 1372 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1380 break; 1373 break;
1381 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1382 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1383 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1384 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1385 is_dig = true;
1386 break;
1387 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1374 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1388 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1375 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1389 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1390 break;
1391 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1376 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1392 if (ASIC_IS_DCE5(rdev)) 1377 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1393 is_dce5_dvo = true;
1394 else if (ASIC_IS_DCE3(rdev))
1395 is_dig = true;
1396 else
1397 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1398 break; 1378 break;
1399 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1379 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1400 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1380 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
@@ -1407,16 +1387,12 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1407 break; 1387 break;
1408 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1388 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1409 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1389 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1410 if (ASIC_IS_DCE5(rdev)) 1390 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1411 is_dce5_dac = true; 1391 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1412 else { 1392 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1413 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1393 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1414 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1394 else
1415 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1395 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1416 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1417 else
1418 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1419 }
1420 break; 1396 break;
1421 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1397 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1422 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1398 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
@@ -1427,138 +1403,196 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1427 else 1403 else
1428 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); 1404 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1429 break; 1405 break;
1406 default:
1407 return;
1430 } 1408 }
1431 1409
1432 if (is_dig) { 1410 switch (mode) {
1433 switch (mode) { 1411 case DRM_MODE_DPMS_ON:
1434 case DRM_MODE_DPMS_ON: 1412 args.ucAction = ATOM_ENABLE;
1435 /* some early dce3.2 boards have a bug in their transmitter control table */ 1413 /* workaround for DVOOutputControl on some RS690 systems */
1436 if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730)) 1414 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1437 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1415 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1438 else 1416 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1439 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); 1417 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1440 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) { 1418 WREG32(RADEON_BIOS_3_SCRATCH, reg);
1441 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1419 } else
1420 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1421 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1422 args.ucAction = ATOM_LCD_BLON;
1423 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1424 }
1425 break;
1426 case DRM_MODE_DPMS_STANDBY:
1427 case DRM_MODE_DPMS_SUSPEND:
1428 case DRM_MODE_DPMS_OFF:
1429 args.ucAction = ATOM_DISABLE;
1430 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1431 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1432 args.ucAction = ATOM_LCD_BLOFF;
1433 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1434 }
1435 break;
1436 }
1437}
1442 1438
1443 if (connector && 1439static void
1444 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 1440radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1445 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1441{
1446 struct radeon_connector_atom_dig *radeon_dig_connector = 1442 struct drm_device *dev = encoder->dev;
1447 radeon_connector->con_priv; 1443 struct radeon_device *rdev = dev->dev_private;
1448 atombios_set_edp_panel_power(connector, 1444 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1449 ATOM_TRANSMITTER_ACTION_POWER_ON); 1445 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1450 radeon_dig_connector->edp_on = true; 1446 struct radeon_connector *radeon_connector = NULL;
1451 } 1447 struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1452 if (ASIC_IS_DCE4(rdev))
1453 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1454 radeon_dp_link_train(encoder, connector);
1455 if (ASIC_IS_DCE4(rdev))
1456 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1457 }
1458 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1459 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1460 break;
1461 case DRM_MODE_DPMS_STANDBY:
1462 case DRM_MODE_DPMS_SUSPEND:
1463 case DRM_MODE_DPMS_OFF:
1464 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1465 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1466 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1467 1448
1468 if (ASIC_IS_DCE4(rdev)) 1449 if (connector) {
1469 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); 1450 radeon_connector = to_radeon_connector(connector);
1470 if (connector && 1451 radeon_dig_connector = radeon_connector->con_priv;
1471 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 1452 }
1472 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1453
1473 struct radeon_connector_atom_dig *radeon_dig_connector = 1454 switch (mode) {
1474 radeon_connector->con_priv; 1455 case DRM_MODE_DPMS_ON:
1475 atombios_set_edp_panel_power(connector, 1456 /* some early dce3.2 boards have a bug in their transmitter control table */
1476 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1457 if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730))
1477 radeon_dig_connector->edp_on = false; 1458 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1478 } 1459 else
1460 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1461 if ((atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) && connector) {
1462 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1463 atombios_set_edp_panel_power(connector,
1464 ATOM_TRANSMITTER_ACTION_POWER_ON);
1465 radeon_dig_connector->edp_on = true;
1479 } 1466 }
1480 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1467 if (ASIC_IS_DCE4(rdev))
1481 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 1468 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1482 break; 1469 radeon_dp_link_train(encoder, connector);
1483 } 1470 if (ASIC_IS_DCE4(rdev))
1484 } else if (is_dce5_dac) { 1471 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1485 switch (mode) {
1486 case DRM_MODE_DPMS_ON:
1487 atombios_dac_setup(encoder, ATOM_ENABLE);
1488 break;
1489 case DRM_MODE_DPMS_STANDBY:
1490 case DRM_MODE_DPMS_SUSPEND:
1491 case DRM_MODE_DPMS_OFF:
1492 atombios_dac_setup(encoder, ATOM_DISABLE);
1493 break;
1494 }
1495 } else if (is_dce5_dvo) {
1496 switch (mode) {
1497 case DRM_MODE_DPMS_ON:
1498 atombios_dvo_setup(encoder, ATOM_ENABLE);
1499 break;
1500 case DRM_MODE_DPMS_STANDBY:
1501 case DRM_MODE_DPMS_SUSPEND:
1502 case DRM_MODE_DPMS_OFF:
1503 atombios_dvo_setup(encoder, ATOM_DISABLE);
1504 break;
1505 } 1472 }
1506 } else { 1473 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1507 switch (mode) { 1474 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1508 case DRM_MODE_DPMS_ON: 1475 break;
1509 args.ucAction = ATOM_ENABLE; 1476 case DRM_MODE_DPMS_STANDBY:
1510 /* workaround for DVOOutputControl on some RS690 systems */ 1477 case DRM_MODE_DPMS_SUSPEND:
1511 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) { 1478 case DRM_MODE_DPMS_OFF:
1512 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH); 1479 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1513 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE); 1480 if ((atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) && connector) {
1514 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1481 if (ASIC_IS_DCE4(rdev))
1515 WREG32(RADEON_BIOS_3_SCRATCH, reg); 1482 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1516 } else 1483 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1517 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1484 atombios_set_edp_panel_power(connector,
1518 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1485 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1519 args.ucAction = ATOM_LCD_BLON; 1486 radeon_dig_connector->edp_on = false;
1520 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1521 }
1522 break;
1523 case DRM_MODE_DPMS_STANDBY:
1524 case DRM_MODE_DPMS_SUSPEND:
1525 case DRM_MODE_DPMS_OFF:
1526 args.ucAction = ATOM_DISABLE;
1527 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1528 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1529 args.ucAction = ATOM_LCD_BLOFF;
1530 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1531 } 1487 }
1532 break;
1533 } 1488 }
1489 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1490 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1491 break;
1534 } 1492 }
1493}
1535 1494
1536 if (ext_encoder) { 1495static void
1537 switch (mode) { 1496radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
1538 case DRM_MODE_DPMS_ON: 1497 struct drm_encoder *ext_encoder,
1539 default: 1498 int mode)
1540 if (ASIC_IS_DCE41(rdev)) { 1499{
1541 atombios_external_encoder_setup(encoder, ext_encoder, 1500 struct drm_device *dev = encoder->dev;
1542 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT); 1501 struct radeon_device *rdev = dev->dev_private;
1543 atombios_external_encoder_setup(encoder, ext_encoder, 1502
1544 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF); 1503 switch (mode) {
1545 } else 1504 case DRM_MODE_DPMS_ON:
1546 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); 1505 default:
1547 break; 1506 if (ASIC_IS_DCE41(rdev)) {
1548 case DRM_MODE_DPMS_STANDBY: 1507 atombios_external_encoder_setup(encoder, ext_encoder,
1549 case DRM_MODE_DPMS_SUSPEND: 1508 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1550 case DRM_MODE_DPMS_OFF: 1509 atombios_external_encoder_setup(encoder, ext_encoder,
1551 if (ASIC_IS_DCE41(rdev)) { 1510 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1552 atombios_external_encoder_setup(encoder, ext_encoder, 1511 } else
1553 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING); 1512 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1554 atombios_external_encoder_setup(encoder, ext_encoder, 1513 break;
1555 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT); 1514 case DRM_MODE_DPMS_STANDBY:
1556 } else 1515 case DRM_MODE_DPMS_SUSPEND:
1557 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE); 1516 case DRM_MODE_DPMS_OFF:
1558 break; 1517 if (ASIC_IS_DCE41(rdev)) {
1559 } 1518 atombios_external_encoder_setup(encoder, ext_encoder,
1519 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1520 atombios_external_encoder_setup(encoder, ext_encoder,
1521 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1522 } else
1523 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1524 break;
1525 }
1526}
1527
1528static void
1529radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1530{
1531 struct drm_device *dev = encoder->dev;
1532 struct radeon_device *rdev = dev->dev_private;
1533 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1534 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1535
1536 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1537 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1538 radeon_encoder->active_device);
1539 switch (radeon_encoder->encoder_id) {
1540 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1541 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1542 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1543 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1544 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1545 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1546 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1547 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1548 radeon_atom_encoder_dpms_avivo(encoder, mode);
1549 break;
1550 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1551 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1552 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1553 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1554 radeon_atom_encoder_dpms_dig(encoder, mode);
1555 break;
1556 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1557 if (ASIC_IS_DCE5(rdev)) {
1558 switch (mode) {
1559 case DRM_MODE_DPMS_ON:
1560 atombios_dvo_setup(encoder, ATOM_ENABLE);
1561 break;
1562 case DRM_MODE_DPMS_STANDBY:
1563 case DRM_MODE_DPMS_SUSPEND:
1564 case DRM_MODE_DPMS_OFF:
1565 atombios_dvo_setup(encoder, ATOM_DISABLE);
1566 break;
1567 }
1568 } else if (ASIC_IS_DCE3(rdev))
1569 radeon_atom_encoder_dpms_dig(encoder, mode);
1570 else
1571 radeon_atom_encoder_dpms_avivo(encoder, mode);
1572 break;
1573 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1574 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1575 if (ASIC_IS_DCE5(rdev)) {
1576 switch (mode) {
1577 case DRM_MODE_DPMS_ON:
1578 atombios_dac_setup(encoder, ATOM_ENABLE);
1579 break;
1580 case DRM_MODE_DPMS_STANDBY:
1581 case DRM_MODE_DPMS_SUSPEND:
1582 case DRM_MODE_DPMS_OFF:
1583 atombios_dac_setup(encoder, ATOM_DISABLE);
1584 break;
1585 }
1586 } else
1587 radeon_atom_encoder_dpms_avivo(encoder, mode);
1588 break;
1589 default:
1590 return;
1560 } 1591 }
1561 1592
1593 if (ext_encoder)
1594 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
1595
1562 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1596 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1563 1597
1564} 1598}
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-28 12:14:11 -0400