x86: handle PAT more like other CPU features

Impact: Cleanup

When PAT was originally introduced, it was handled specially for a few
reasons:

- PAT bugs are hard to track down, so we wanted to maintain a
  whitelist of CPUs.
- The i386 and x86-64 CPUID code was not yet unified.

Both of these are now obsolete, so handle PAT like any other features,
including ordinary feature blacklisting due to known bugs.

Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>

3 files changed, 12 insertions, 36 deletions

diff --git a/arch/x86/kernel/cpu/addon_cpuid_features.c b/arch/x86/kernel/cpu/addon_cpuid_features.c
index 2cf23634b6d..4e581fdc0a5 100644
--- a/arch/x86/kernel/cpu/addon_cpuid_features.c
+++ b/arch/x86/kernel/cpu/addon_cpuid_features.c
@@ -143,37 +143,3 @@ void __cpuinit detect_extended_topology(struct cpuinfo_x86 *c)
         return;
 #endif
 }
-
-#ifdef CONFIG_X86_PAT
-void __cpuinit validate_pat_support(struct cpuinfo_x86 *c)
-{
-        if (!cpu_has_pat)
-                pat_disable("PAT not supported by CPU.");
-
-        switch (c->x86_vendor) {
-        case X86_VENDOR_INTEL:
-                /*
-                 * There is a known erratum on Pentium III and Core Solo
-                 * and Core Duo CPUs.
-                 * " Page with PAT set to WC while associated MTRR is UC
-                 *   may consolidate to UC "
-                 * Because of this erratum, it is better to stick with
-                 * setting WC in MTRR rather than using PAT on these CPUs.
-                 *
-                 * Enable PAT WC only on P4, Core 2 or later CPUs.
-                 */
-                if (c->x86 > 0x6 || (c->x86 == 6 && c->x86_model >= 15))
-                        return;
-
-                pat_disable("PAT WC disabled due to known CPU erratum.");
-                return;
-
-        case X86_VENDOR_AMD:
-        case X86_VENDOR_CENTAUR:
-        case X86_VENDOR_TRANSMETA:
-                return;
-        }
-
-        pat_disable("PAT disabled. Not yet verified on this CPU type.");
-}
-#endif
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 83492b1f93b..0f8656361e0 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -570,8 +570,6 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c)
         if (this_cpu->c_early_init)
                 this_cpu->c_early_init(c);
 
-        validate_pat_support(c);
-
 #ifdef CONFIG_SMP
         c->cpu_index = boot_cpu_id;
 #endif
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 8ea6929e974..20ce03acf04 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -50,6 +50,18 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
                 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
         }
 
+        /*
+         * There is a known erratum on Pentium III and Core Solo
+         * and Core Duo CPUs.
+         * " Page with PAT set to WC while associated MTRR is UC
+         *   may consolidate to UC "
+         * Because of this erratum, it is better to stick with
+         * setting WC in MTRR rather than using PAT on these CPUs.
+         *
+         * Enable PAT WC only on P4, Core 2 or later CPUs.
+         */
+        if (c->x86 == 6 && c->x86_model < 15)
+                clear_cpu_cap(c, X86_FEATURE_PAT);
 }
 
 #ifdef CONFIG_X86_32