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authorLinus Torvalds <torvalds@linux-foundation.org>2011-06-16 12:46:24 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-06-16 12:46:24 -0400
commitf8f44f09eaa2bfb40651e7fc6054d65c8091499a (patch)
treed68df2dca22c6450b1cbb43cd314a47557920187 /arch/sh/mm/cache-debugfs.c
parentf49cc57cc9d1686bdca068c40bc43f1690aa02d3 (diff)
parent261a9af671a79b750cb170bac620601d686535c1 (diff)
Merge branch 'sh-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-3.x
* 'sh-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-3.x: sh: sh7724: Add USBHS DMAEngine support sh: ecovec: Add renesas_usbhs support sh, exec: remove redundant set_fs(USER_DS) drivers: sh: resume enabled clocks fix dmaengine: shdma: SH_DMAC_MAX_CHANNELS message fix sh: Fix up xchg/cmpxchg corruption with gUSA RB. sh: Remove compressed kernel libgcc dependency. sh: fix wrong icache/dcache address-array start addr in cache-debugfs.
Diffstat (limited to 'arch/sh/mm/cache-debugfs.c')
-rw-r--r--arch/sh/mm/cache-debugfs.c25
1 files changed, 5 insertions, 20 deletions
diff --git a/arch/sh/mm/cache-debugfs.c b/arch/sh/mm/cache-debugfs.c
index 52411462c40..11572519803 100644
--- a/arch/sh/mm/cache-debugfs.c
+++ b/arch/sh/mm/cache-debugfs.c
@@ -26,9 +26,9 @@ static int cache_seq_show(struct seq_file *file, void *iter)
26{ 26{
27 unsigned int cache_type = (unsigned int)file->private; 27 unsigned int cache_type = (unsigned int)file->private;
28 struct cache_info *cache; 28 struct cache_info *cache;
29 unsigned int waysize, way, cache_size; 29 unsigned int waysize, way;
30 unsigned long ccr, base; 30 unsigned long ccr;
31 static unsigned long addrstart = 0; 31 unsigned long addrstart = 0;
32 32
33 /* 33 /*
34 * Go uncached immediately so we don't skew the results any 34 * Go uncached immediately so we don't skew the results any
@@ -45,28 +45,13 @@ static int cache_seq_show(struct seq_file *file, void *iter)
45 } 45 }
46 46
47 if (cache_type == CACHE_TYPE_DCACHE) { 47 if (cache_type == CACHE_TYPE_DCACHE) {
48 base = CACHE_OC_ADDRESS_ARRAY; 48 addrstart = CACHE_OC_ADDRESS_ARRAY;
49 cache = &current_cpu_data.dcache; 49 cache = &current_cpu_data.dcache;
50 } else { 50 } else {
51 base = CACHE_IC_ADDRESS_ARRAY; 51 addrstart = CACHE_IC_ADDRESS_ARRAY;
52 cache = &current_cpu_data.icache; 52 cache = &current_cpu_data.icache;
53 } 53 }
54 54
55 /*
56 * Due to the amount of data written out (depending on the cache size),
57 * we may be iterated over multiple times. In this case, keep track of
58 * the entry position in addrstart, and rewind it when we've hit the
59 * end of the cache.
60 *
61 * Likewise, the same code is used for multiple caches, so care must
62 * be taken for bouncing addrstart back and forth so the appropriate
63 * cache is hit.
64 */
65 cache_size = cache->ways * cache->sets * cache->linesz;
66 if (((addrstart & 0xff000000) != base) ||
67 (addrstart & 0x00ffffff) > cache_size)
68 addrstart = base;
69
70 waysize = cache->sets; 55 waysize = cache->sets;
71 56
72 /* 57 /*