diff options
author | Paul Mundt <lethal@linux-sh.org> | 2011-01-13 01:21:27 -0500 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2011-01-13 01:21:27 -0500 |
commit | ef7fc9026fe6adef13870c6b2cb4642b6193af67 (patch) | |
tree | 6f41f996de6e76161fdfc60a197ec42f0aa0ec7d /arch/sh/kernel/cpu/sh4a/setup-sh7723.c | |
parent | fac6c2a891a3e7255e4440f09a4c7da954043ba9 (diff) | |
parent | f43dc23d5ea91fca257be02138a255f02d98e806 (diff) |
Merge branch 'common/serial-rework' into sh-latest
Diffstat (limited to 'arch/sh/kernel/cpu/sh4a/setup-sh7723.c')
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/setup-sh7723.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c index d7641221ee4..072382280f9 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c | |||
@@ -24,6 +24,8 @@ | |||
24 | static struct plat_sci_port scif0_platform_data = { | 24 | static struct plat_sci_port scif0_platform_data = { |
25 | .mapbase = 0xffe00000, | 25 | .mapbase = 0xffe00000, |
26 | .flags = UPF_BOOT_AUTOCONF, | 26 | .flags = UPF_BOOT_AUTOCONF, |
27 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
28 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
27 | .type = PORT_SCIF, | 29 | .type = PORT_SCIF, |
28 | .irqs = { 80, 80, 80, 80 }, | 30 | .irqs = { 80, 80, 80, 80 }, |
29 | }; | 31 | }; |
@@ -39,6 +41,8 @@ static struct platform_device scif0_device = { | |||
39 | static struct plat_sci_port scif1_platform_data = { | 41 | static struct plat_sci_port scif1_platform_data = { |
40 | .mapbase = 0xffe10000, | 42 | .mapbase = 0xffe10000, |
41 | .flags = UPF_BOOT_AUTOCONF, | 43 | .flags = UPF_BOOT_AUTOCONF, |
44 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
45 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
42 | .type = PORT_SCIF, | 46 | .type = PORT_SCIF, |
43 | .irqs = { 81, 81, 81, 81 }, | 47 | .irqs = { 81, 81, 81, 81 }, |
44 | }; | 48 | }; |
@@ -54,6 +58,8 @@ static struct platform_device scif1_device = { | |||
54 | static struct plat_sci_port scif2_platform_data = { | 58 | static struct plat_sci_port scif2_platform_data = { |
55 | .mapbase = 0xffe20000, | 59 | .mapbase = 0xffe20000, |
56 | .flags = UPF_BOOT_AUTOCONF, | 60 | .flags = UPF_BOOT_AUTOCONF, |
61 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
62 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
57 | .type = PORT_SCIF, | 63 | .type = PORT_SCIF, |
58 | .irqs = { 82, 82, 82, 82 }, | 64 | .irqs = { 82, 82, 82, 82 }, |
59 | }; | 65 | }; |
@@ -69,6 +75,8 @@ static struct platform_device scif2_device = { | |||
69 | static struct plat_sci_port scif3_platform_data = { | 75 | static struct plat_sci_port scif3_platform_data = { |
70 | .mapbase = 0xa4e30000, | 76 | .mapbase = 0xa4e30000, |
71 | .flags = UPF_BOOT_AUTOCONF, | 77 | .flags = UPF_BOOT_AUTOCONF, |
78 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
79 | .scbrr_algo_id = SCBRR_ALGO_3, | ||
72 | .type = PORT_SCIFA, | 80 | .type = PORT_SCIFA, |
73 | .irqs = { 56, 56, 56, 56 }, | 81 | .irqs = { 56, 56, 56, 56 }, |
74 | }; | 82 | }; |
@@ -84,6 +92,8 @@ static struct platform_device scif3_device = { | |||
84 | static struct plat_sci_port scif4_platform_data = { | 92 | static struct plat_sci_port scif4_platform_data = { |
85 | .mapbase = 0xa4e40000, | 93 | .mapbase = 0xa4e40000, |
86 | .flags = UPF_BOOT_AUTOCONF, | 94 | .flags = UPF_BOOT_AUTOCONF, |
95 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
96 | .scbrr_algo_id = SCBRR_ALGO_3, | ||
87 | .type = PORT_SCIFA, | 97 | .type = PORT_SCIFA, |
88 | .irqs = { 88, 88, 88, 88 }, | 98 | .irqs = { 88, 88, 88, 88 }, |
89 | }; | 99 | }; |
@@ -99,6 +109,8 @@ static struct platform_device scif4_device = { | |||
99 | static struct plat_sci_port scif5_platform_data = { | 109 | static struct plat_sci_port scif5_platform_data = { |
100 | .mapbase = 0xa4e50000, | 110 | .mapbase = 0xa4e50000, |
101 | .flags = UPF_BOOT_AUTOCONF, | 111 | .flags = UPF_BOOT_AUTOCONF, |
112 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
113 | .scbrr_algo_id = SCBRR_ALGO_3, | ||
102 | .type = PORT_SCIFA, | 114 | .type = PORT_SCIFA, |
103 | .irqs = { 109, 109, 109, 109 }, | 115 | .irqs = { 109, 109, 109, 109 }, |
104 | }; | 116 | }; |