diff options
author | Paul Mundt <lethal@linux-sh.org> | 2008-07-28 19:09:44 -0400 |
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committer | Paul Mundt <lethal@linux-sh.org> | 2008-07-28 19:09:44 -0400 |
commit | f15cbe6f1a4b4d9df59142fc8e4abb973302cf44 (patch) | |
tree | 774d7b11abaaf33561ab8268bf51ddd9ceb79025 /arch/sh/include/cpu-sh2a/cpu/cacheflush.h | |
parent | 25326277d8d1393d1c66240e6255aca780f9e3eb (diff) |
sh: migrate to arch/sh/include/
This follows the sparc changes a439fe51a1f8eb087c22dd24d69cebae4a3addac.
Most of the moving about was done with Sam's directions at:
http://marc.info/?l=linux-sh&m=121724823706062&w=2
with subsequent hacking and fixups entirely my fault.
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/include/cpu-sh2a/cpu/cacheflush.h')
-rw-r--r-- | arch/sh/include/cpu-sh2a/cpu/cacheflush.h | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/arch/sh/include/cpu-sh2a/cpu/cacheflush.h b/arch/sh/include/cpu-sh2a/cpu/cacheflush.h new file mode 100644 index 00000000000..2979efb26de --- /dev/null +++ b/arch/sh/include/cpu-sh2a/cpu/cacheflush.h | |||
@@ -0,0 +1,44 @@ | |||
1 | /* | ||
2 | * include/asm-sh/cpu-sh2/cacheflush.h | ||
3 | * | ||
4 | * Copyright (C) 2003 Paul Mundt | ||
5 | * | ||
6 | * This file is subject to the terms and conditions of the GNU General Public | ||
7 | * License. See the file "COPYING" in the main directory of this archive | ||
8 | * for more details. | ||
9 | */ | ||
10 | #ifndef __ASM_CPU_SH2_CACHEFLUSH_H | ||
11 | #define __ASM_CPU_SH2_CACHEFLUSH_H | ||
12 | |||
13 | /* | ||
14 | * Cache flushing: | ||
15 | * | ||
16 | * - flush_cache_all() flushes entire cache | ||
17 | * - flush_cache_mm(mm) flushes the specified mm context's cache lines | ||
18 | * - flush_cache_dup mm(mm) handles cache flushing when forking | ||
19 | * - flush_cache_page(mm, vmaddr, pfn) flushes a single page | ||
20 | * - flush_cache_range(vma, start, end) flushes a range of pages | ||
21 | * | ||
22 | * - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache | ||
23 | * - flush_icache_range(start, end) flushes(invalidates) a range for icache | ||
24 | * - flush_icache_page(vma, pg) flushes(invalidates) a page for icache | ||
25 | * | ||
26 | * Caches are indexed (effectively) by physical address on SH-2, so | ||
27 | * we don't need them. | ||
28 | */ | ||
29 | #define flush_cache_all() do { } while (0) | ||
30 | #define flush_cache_mm(mm) do { } while (0) | ||
31 | #define flush_cache_dup_mm(mm) do { } while (0) | ||
32 | #define flush_cache_range(vma, start, end) do { } while (0) | ||
33 | #define flush_cache_page(vma, vmaddr, pfn) do { } while (0) | ||
34 | #define flush_dcache_page(page) do { } while (0) | ||
35 | #define flush_dcache_mmap_lock(mapping) do { } while (0) | ||
36 | #define flush_dcache_mmap_unlock(mapping) do { } while (0) | ||
37 | #define flush_icache_range(start, end) do { } while (0) | ||
38 | #define flush_icache_page(vma,pg) do { } while (0) | ||
39 | #define flush_icache_user_range(vma,pg,adr,len) do { } while (0) | ||
40 | #define flush_cache_sigtramp(vaddr) do { } while (0) | ||
41 | |||
42 | #define p3_cache_init() do { } while (0) | ||
43 | #endif /* __ASM_CPU_SH2_CACHEFLUSH_H */ | ||
44 | |||