MN10300: And Panasonic AM34 subarch and implement SMP

Implement the Panasonic MN10300 AM34 CPU subarch and implement SMP support for
MN10300.  Also implement support for the MN2WS0060 processor and the ASB2364
evaluation board which are AM34 based.

Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: David Howells <dhowells@redhat.com>

1 files changed, 10 insertions, 31 deletions

diff --git a/arch/mn10300/kernel/rtc.c b/arch/mn10300/kernel/rtc.c
index 4eef0e7224f..e9e20f9a4dd 100644
--- a/arch/mn10300/kernel/rtc.c
+++ b/arch/mn10300/kernel/rtc.c
@@ -20,18 +20,22 @@
 DEFINE_SPINLOCK(rtc_lock);
 EXPORT_SYMBOL(rtc_lock);
 
-/* time for RTC to update itself in ioclks */
-static unsigned long mn10300_rtc_update_period;
-
+/*
+ * Read the current RTC time
+ */
 void read_persistent_clock(struct timespec *ts)
 {
         struct rtc_time tm;
 
         get_rtc_time(&tm);
 
-        ts->tv_sec = mktime(tm.tm_year, tm.tm_mon, tm.tm_mday,
-                      tm.tm_hour, tm.tm_min, tm.tm_sec);
         ts->tv_nsec = 0;
+        ts->tv_sec = mktime(tm.tm_year, tm.tm_mon, tm.tm_mday,
+                            tm.tm_hour, tm.tm_min, tm.tm_sec);
+
+        /* if rtc is way off in the past, set something reasonable */
+        if (ts->tv_sec < 0)
+                ts->tv_sec = mktime(2009, 1, 1, 12, 0, 0);
 }
 
 /*
@@ -115,39 +119,14 @@ int update_persistent_clock(struct timespec now)
  */
 void __init calibrate_clock(void)
 {
-        unsigned long count0, counth, count1;
         unsigned char status;
 
         /* make sure the RTC is running and is set to operate in 24hr mode */
         status = RTSRC;
         RTCRB |= RTCRB_SET;
         RTCRB |= RTCRB_TM_24HR;
+        RTCRB &= ~RTCRB_DM_BINARY;
         RTCRA |= RTCRA_DVR;
         RTCRA &= ~RTCRA_DVR;
         RTCRB &= ~RTCRB_SET;
-
-        /* work out the clock speed by counting clock cycles between ends of
-         * the RTC update cycle - track the RTC through one complete update
-         * cycle (1 second)
-         */
-        startup_timestamp_counter();
-
-        while (!(RTCRA & RTCRA_UIP)) {}
-        while ((RTCRA & RTCRA_UIP)) {}
-
-        count0 = TMTSCBC;
-
-        while (!(RTCRA & RTCRA_UIP)) {}
-
-        counth = TMTSCBC;
-
-        while ((RTCRA & RTCRA_UIP)) {}
-
-        count1 = TMTSCBC;
-
-        shutdown_timestamp_counter();
-
-        MN10300_TSCCLK = count0 - count1; /* the timers count down */
-        mn10300_rtc_update_period = counth - count1;
-        MN10300_TSC_PER_HZ = MN10300_TSCCLK / HZ;
 }