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authorLinus Torvalds <torvalds@linux-foundation.org>2010-02-27 19:19:22 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2010-02-27 19:19:22 -0500
commitf1dd6ad599732fc89f36fdd65a2c2cf3c63a8711 (patch)
tree5092207128e47cba99dc0fe373fff6a36f4cb4b8 /arch/mips/mm/uasm.c
parent8d37a371b6869920e6c40c495c68eabba1ef3909 (diff)
parente10b234b3c4e255d3300a486c4ac15b43253ac6d (diff)
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (141 commits) MIPS: Alchemy: defconfig updates MIPS: Alchemy: Fix Au1100 ethernet build failure MIPS: Alchemy: Repair db1500/bosporus builds MIPS: ARC: Cleanup unused definitions from sgialib.h MIPS: Cobalt: convert legacy port addresses to GT-64111 bus addresses MIPS: Alchemy: use 36bit addresses for PCMCIA resources. MIPS: Cobalt: Fix theoretical port aliasing issue MIPS: Use ALIGN(x, bytes) instead of __ALIGN_MASK(x, bytes - 1) MIPS: Crazy spinlock speed test. MIPS: Optimize spinlocks. MIPS: Alchemy: devboard PM needs to save CPLD registers. MIPS: PowerTV: Eliminate duplicate opcode definition macros MIPS: Lemote 2F: Move printks out of port_access_lock. MIPS: PNX833x: Convert IRQ controller locks to raw spinlocks. MIPS: Octeon: Replace spinlock with raw_spinlocks in dma-octeon.c. MIPS: Octeon: Replace rwlocks in irq_chip handlers with raw_spinlocks. MIPS: Octeon: Convert octeon_irq_msi_lock to raw spinlock. MIPS: Loongson: Remove pointless sample_lock from oprofile code. MIPS: SNI: Convert sni_rm200_i8259A_lock to raw spinlock. MIPS: i8259: Convert IRQ controller lock to raw spinlock. ...
Diffstat (limited to 'arch/mips/mm/uasm.c')
-rw-r--r--arch/mips/mm/uasm.c12
1 files changed, 8 insertions, 4 deletions
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
index 0a165c5179a..1581e985246 100644
--- a/arch/mips/mm/uasm.c
+++ b/arch/mips/mm/uasm.c
@@ -19,8 +19,7 @@
19#include <asm/inst.h> 19#include <asm/inst.h>
20#include <asm/elf.h> 20#include <asm/elf.h>
21#include <asm/bugs.h> 21#include <asm/bugs.h>
22 22#include <asm/uasm.h>
23#include "uasm.h"
24 23
25enum fields { 24enum fields {
26 RS = 0x001, 25 RS = 0x001,
@@ -63,8 +62,9 @@ enum opcode {
63 insn_dsrl32, insn_drotr, insn_dsubu, insn_eret, insn_j, insn_jal, 62 insn_dsrl32, insn_drotr, insn_dsubu, insn_eret, insn_j, insn_jal,
64 insn_jr, insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, 63 insn_jr, insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0,
65 insn_mtc0, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd, 64 insn_mtc0, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd,
66 insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw, 65 insn_sd, insn_sll, insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw,
67 insn_tlbp, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, insn_dins 66 insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori,
67 insn_dins
68}; 68};
69 69
70struct insn { 70struct insn {
@@ -126,9 +126,11 @@ static struct insn insn_table[] __cpuinitdata = {
126 { insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE }, 126 { insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE },
127 { insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE }, 127 { insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE },
128 { insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE }, 128 { insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE },
129 { insn_rotr, M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE },
129 { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD }, 130 { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD },
130 { insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 131 { insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
131 { insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 }, 132 { insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 },
133 { insn_tlbr, M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0 },
132 { insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 }, 134 { insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 },
133 { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 }, 135 { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 },
134 { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD }, 136 { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD },
@@ -379,9 +381,11 @@ I_u2s3u1(_sd)
379I_u2u1u3(_sll) 381I_u2u1u3(_sll)
380I_u2u1u3(_sra) 382I_u2u1u3(_sra)
381I_u2u1u3(_srl) 383I_u2u1u3(_srl)
384I_u2u1u3(_rotr)
382I_u3u1u2(_subu) 385I_u3u1u2(_subu)
383I_u2s3u1(_sw) 386I_u2s3u1(_sw)
384I_0(_tlbp) 387I_0(_tlbp)
388I_0(_tlbr)
385I_0(_tlbwi) 389I_0(_tlbwi)
386I_0(_tlbwr) 390I_0(_tlbwr)
387I_u3u1u2(_xor) 391I_u3u1u2(_xor)