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author | Linus Torvalds <torvalds@linux-foundation.org> | 2010-02-27 19:19:22 -0500 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2010-02-27 19:19:22 -0500 |
commit | f1dd6ad599732fc89f36fdd65a2c2cf3c63a8711 (patch) | |
tree | 5092207128e47cba99dc0fe373fff6a36f4cb4b8 /arch/mips/kernel/cpu-probe.c | |
parent | 8d37a371b6869920e6c40c495c68eabba1ef3909 (diff) | |
parent | e10b234b3c4e255d3300a486c4ac15b43253ac6d (diff) |
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (141 commits)
MIPS: Alchemy: defconfig updates
MIPS: Alchemy: Fix Au1100 ethernet build failure
MIPS: Alchemy: Repair db1500/bosporus builds
MIPS: ARC: Cleanup unused definitions from sgialib.h
MIPS: Cobalt: convert legacy port addresses to GT-64111 bus addresses
MIPS: Alchemy: use 36bit addresses for PCMCIA resources.
MIPS: Cobalt: Fix theoretical port aliasing issue
MIPS: Use ALIGN(x, bytes) instead of __ALIGN_MASK(x, bytes - 1)
MIPS: Crazy spinlock speed test.
MIPS: Optimize spinlocks.
MIPS: Alchemy: devboard PM needs to save CPLD registers.
MIPS: PowerTV: Eliminate duplicate opcode definition macros
MIPS: Lemote 2F: Move printks out of port_access_lock.
MIPS: PNX833x: Convert IRQ controller locks to raw spinlocks.
MIPS: Octeon: Replace spinlock with raw_spinlocks in dma-octeon.c.
MIPS: Octeon: Replace rwlocks in irq_chip handlers with raw_spinlocks.
MIPS: Octeon: Convert octeon_irq_msi_lock to raw spinlock.
MIPS: Loongson: Remove pointless sample_lock from oprofile code.
MIPS: SNI: Convert sni_rm200_i8259A_lock to raw spinlock.
MIPS: i8259: Convert IRQ controller lock to raw spinlock.
...
Diffstat (limited to 'arch/mips/kernel/cpu-probe.c')
-rw-r--r-- | arch/mips/kernel/cpu-probe.c | 30 |
1 files changed, 25 insertions, 5 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 758ad426c57..be5bb16be4e 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c | |||
@@ -162,6 +162,7 @@ void __init check_wait(void) | |||
162 | case CPU_BCM6348: | 162 | case CPU_BCM6348: |
163 | case CPU_BCM6358: | 163 | case CPU_BCM6358: |
164 | case CPU_CAVIUM_OCTEON: | 164 | case CPU_CAVIUM_OCTEON: |
165 | case CPU_CAVIUM_OCTEON_PLUS: | ||
165 | cpu_wait = r4k_wait; | 166 | cpu_wait = r4k_wait; |
166 | break; | 167 | break; |
167 | 168 | ||
@@ -700,6 +701,19 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c) | |||
700 | return config3 & MIPS_CONF_M; | 701 | return config3 & MIPS_CONF_M; |
701 | } | 702 | } |
702 | 703 | ||
704 | static inline unsigned int decode_config4(struct cpuinfo_mips *c) | ||
705 | { | ||
706 | unsigned int config4; | ||
707 | |||
708 | config4 = read_c0_config4(); | ||
709 | |||
710 | if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT | ||
711 | && cpu_has_tlb) | ||
712 | c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; | ||
713 | |||
714 | return config4 & MIPS_CONF_M; | ||
715 | } | ||
716 | |||
703 | static void __cpuinit decode_configs(struct cpuinfo_mips *c) | 717 | static void __cpuinit decode_configs(struct cpuinfo_mips *c) |
704 | { | 718 | { |
705 | int ok; | 719 | int ok; |
@@ -718,6 +732,8 @@ static void __cpuinit decode_configs(struct cpuinfo_mips *c) | |||
718 | ok = decode_config2(c); | 732 | ok = decode_config2(c); |
719 | if (ok) | 733 | if (ok) |
720 | ok = decode_config3(c); | 734 | ok = decode_config3(c); |
735 | if (ok) | ||
736 | ok = decode_config4(c); | ||
721 | 737 | ||
722 | mips_probe_watch_registers(c); | 738 | mips_probe_watch_registers(c); |
723 | } | 739 | } |
@@ -731,9 +747,6 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) | |||
731 | __cpu_name[cpu] = "MIPS 4Kc"; | 747 | __cpu_name[cpu] = "MIPS 4Kc"; |
732 | break; | 748 | break; |
733 | case PRID_IMP_4KEC: | 749 | case PRID_IMP_4KEC: |
734 | c->cputype = CPU_4KEC; | ||
735 | __cpu_name[cpu] = "MIPS 4KEc"; | ||
736 | break; | ||
737 | case PRID_IMP_4KECR2: | 750 | case PRID_IMP_4KECR2: |
738 | c->cputype = CPU_4KEC; | 751 | c->cputype = CPU_4KEC; |
739 | __cpu_name[cpu] = "MIPS 4KEc"; | 752 | __cpu_name[cpu] = "MIPS 4KEc"; |
@@ -899,12 +912,18 @@ static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) | |||
899 | case PRID_IMP_CAVIUM_CN38XX: | 912 | case PRID_IMP_CAVIUM_CN38XX: |
900 | case PRID_IMP_CAVIUM_CN31XX: | 913 | case PRID_IMP_CAVIUM_CN31XX: |
901 | case PRID_IMP_CAVIUM_CN30XX: | 914 | case PRID_IMP_CAVIUM_CN30XX: |
915 | c->cputype = CPU_CAVIUM_OCTEON; | ||
916 | __cpu_name[cpu] = "Cavium Octeon"; | ||
917 | goto platform; | ||
902 | case PRID_IMP_CAVIUM_CN58XX: | 918 | case PRID_IMP_CAVIUM_CN58XX: |
903 | case PRID_IMP_CAVIUM_CN56XX: | 919 | case PRID_IMP_CAVIUM_CN56XX: |
904 | case PRID_IMP_CAVIUM_CN50XX: | 920 | case PRID_IMP_CAVIUM_CN50XX: |
905 | case PRID_IMP_CAVIUM_CN52XX: | 921 | case PRID_IMP_CAVIUM_CN52XX: |
906 | c->cputype = CPU_CAVIUM_OCTEON; | 922 | c->cputype = CPU_CAVIUM_OCTEON_PLUS; |
907 | __cpu_name[cpu] = "Cavium Octeon"; | 923 | __cpu_name[cpu] = "Cavium Octeon+"; |
924 | platform: | ||
925 | if (cpu == 0) | ||
926 | __elf_platform = "octeon"; | ||
908 | break; | 927 | break; |
909 | default: | 928 | default: |
910 | printk(KERN_INFO "Unknown Octeon chip!\n"); | 929 | printk(KERN_INFO "Unknown Octeon chip!\n"); |
@@ -914,6 +933,7 @@ static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) | |||
914 | } | 933 | } |
915 | 934 | ||
916 | const char *__cpu_name[NR_CPUS]; | 935 | const char *__cpu_name[NR_CPUS]; |
936 | const char *__elf_platform; | ||
917 | 937 | ||
918 | __cpuinit void cpu_probe(void) | 938 | __cpuinit void cpu_probe(void) |
919 | { | 939 | { |