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authorRajendra Nayak <rnayak@ti.com>2011-07-24 15:57:43 -0400
committerPaolo Pisati <paolo.pisati@canonical.com>2012-08-17 04:18:02 -0400
commit5f939357279c17d2a96388d38f31213500e52fed (patch)
treef8242b05d9b30913939959dce80f1f507f96ed76 /arch/arm
parent087b6bf79a34cdaa306c0f0ea109152e6d95b8ca (diff)
OMAP4: clocks: distinguish 4430 and 4460
OMAP4460 platform has a few clock nodes which are added and a few which are missing (compared to the 4430 platform) rename current 4430 definitions to 44XX and followon patches will introduce the 4460 changes Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c659
-rw-r--r--arch/arm/plat-omap/include/plat/clkdev_omap.h2
-rw-r--r--arch/arm/plat-omap/include/plat/clock.h2
3 files changed, 335 insertions, 328 deletions
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 8c965671b4d..ee11cd43af7 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * OMAP4 Clock data 2 * OMAP44xx Clock data
3 * 3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc. 4 * Copyright (C) 2009-2011 Texas Instruments Incorporated
5 * Copyright (C) 2009-2010 Nokia Corporation 5 * Copyright (C) 2009-2010 Nokia Corporation
6 * 6 *
7 * Paul Walmsley (paul@pwsan.com) 7 * Paul Walmsley (paul@pwsan.com)
@@ -127,42 +127,42 @@ static struct clk virt_38400000_ck = {
127}; 127};
128 128
129static const struct clksel_rate div_1_0_rates[] = { 129static const struct clksel_rate div_1_0_rates[] = {
130 { .div = 1, .val = 0, .flags = RATE_IN_4430 }, 130 { .div = 1, .val = 0, .flags = RATE_IN_44XX },
131 { .div = 0 }, 131 { .div = 0 },
132}; 132};
133 133
134static const struct clksel_rate div_1_1_rates[] = { 134static const struct clksel_rate div_1_1_rates[] = {
135 { .div = 1, .val = 1, .flags = RATE_IN_4430 }, 135 { .div = 1, .val = 1, .flags = RATE_IN_44XX },
136 { .div = 0 }, 136 { .div = 0 },
137}; 137};
138 138
139static const struct clksel_rate div_1_2_rates[] = { 139static const struct clksel_rate div_1_2_rates[] = {
140 { .div = 1, .val = 2, .flags = RATE_IN_4430 }, 140 { .div = 1, .val = 2, .flags = RATE_IN_44XX },
141 { .div = 0 }, 141 { .div = 0 },
142}; 142};
143 143
144static const struct clksel_rate div_1_3_rates[] = { 144static const struct clksel_rate div_1_3_rates[] = {
145 { .div = 1, .val = 3, .flags = RATE_IN_4430 }, 145 { .div = 1, .val = 3, .flags = RATE_IN_44XX },
146 { .div = 0 }, 146 { .div = 0 },
147}; 147};
148 148
149static const struct clksel_rate div_1_4_rates[] = { 149static const struct clksel_rate div_1_4_rates[] = {
150 { .div = 1, .val = 4, .flags = RATE_IN_4430 }, 150 { .div = 1, .val = 4, .flags = RATE_IN_44XX },
151 { .div = 0 }, 151 { .div = 0 },
152}; 152};
153 153
154static const struct clksel_rate div_1_5_rates[] = { 154static const struct clksel_rate div_1_5_rates[] = {
155 { .div = 1, .val = 5, .flags = RATE_IN_4430 }, 155 { .div = 1, .val = 5, .flags = RATE_IN_44XX },
156 { .div = 0 }, 156 { .div = 0 },
157}; 157};
158 158
159static const struct clksel_rate div_1_6_rates[] = { 159static const struct clksel_rate div_1_6_rates[] = {
160 { .div = 1, .val = 6, .flags = RATE_IN_4430 }, 160 { .div = 1, .val = 6, .flags = RATE_IN_44XX },
161 { .div = 0 }, 161 { .div = 0 },
162}; 162};
163 163
164static const struct clksel_rate div_1_7_rates[] = { 164static const struct clksel_rate div_1_7_rates[] = {
165 { .div = 1, .val = 7, .flags = RATE_IN_4430 }, 165 { .div = 1, .val = 7, .flags = RATE_IN_44XX },
166 { .div = 0 }, 166 { .div = 0 },
167}; 167};
168 168
@@ -285,37 +285,37 @@ static struct clk dpll_abe_x2_ck = {
285}; 285};
286 286
287static const struct clksel_rate div31_1to31_rates[] = { 287static const struct clksel_rate div31_1to31_rates[] = {
288 { .div = 1, .val = 1, .flags = RATE_IN_4430 }, 288 { .div = 1, .val = 1, .flags = RATE_IN_44XX },
289 { .div = 2, .val = 2, .flags = RATE_IN_4430 }, 289 { .div = 2, .val = 2, .flags = RATE_IN_44XX },
290 { .div = 3, .val = 3, .flags = RATE_IN_4430 }, 290 { .div = 3, .val = 3, .flags = RATE_IN_44XX },
291 { .div = 4, .val = 4, .flags = RATE_IN_4430 }, 291 { .div = 4, .val = 4, .flags = RATE_IN_44XX },
292 { .div = 5, .val = 5, .flags = RATE_IN_4430 }, 292 { .div = 5, .val = 5, .flags = RATE_IN_44XX },
293 { .div = 6, .val = 6, .flags = RATE_IN_4430 }, 293 { .div = 6, .val = 6, .flags = RATE_IN_44XX },
294 { .div = 7, .val = 7, .flags = RATE_IN_4430 }, 294 { .div = 7, .val = 7, .flags = RATE_IN_44XX },
295 { .div = 8, .val = 8, .flags = RATE_IN_4430 }, 295 { .div = 8, .val = 8, .flags = RATE_IN_44XX },
296 { .div = 9, .val = 9, .flags = RATE_IN_4430 }, 296 { .div = 9, .val = 9, .flags = RATE_IN_44XX },
297 { .div = 10, .val = 10, .flags = RATE_IN_4430 }, 297 { .div = 10, .val = 10, .flags = RATE_IN_44XX },
298 { .div = 11, .val = 11, .flags = RATE_IN_4430 }, 298 { .div = 11, .val = 11, .flags = RATE_IN_44XX },
299 { .div = 12, .val = 12, .flags = RATE_IN_4430 }, 299 { .div = 12, .val = 12, .flags = RATE_IN_44XX },
300 { .div = 13, .val = 13, .flags = RATE_IN_4430 }, 300 { .div = 13, .val = 13, .flags = RATE_IN_44XX },
301 { .div = 14, .val = 14, .flags = RATE_IN_4430 }, 301 { .div = 14, .val = 14, .flags = RATE_IN_44XX },
302 { .div = 15, .val = 15, .flags = RATE_IN_4430 }, 302 { .div = 15, .val = 15, .flags = RATE_IN_44XX },
303 { .div = 16, .val = 16, .flags = RATE_IN_4430 }, 303 { .div = 16, .val = 16, .flags = RATE_IN_44XX },
304 { .div = 17, .val = 17, .flags = RATE_IN_4430 }, 304 { .div = 17, .val = 17, .flags = RATE_IN_44XX },
305 { .div = 18, .val = 18, .flags = RATE_IN_4430 }, 305 { .div = 18, .val = 18, .flags = RATE_IN_44XX },
306 { .div = 19, .val = 19, .flags = RATE_IN_4430 }, 306 { .div = 19, .val = 19, .flags = RATE_IN_44XX },
307 { .div = 20, .val = 20, .flags = RATE_IN_4430 }, 307 { .div = 20, .val = 20, .flags = RATE_IN_44XX },
308 { .div = 21, .val = 21, .flags = RATE_IN_4430 }, 308 { .div = 21, .val = 21, .flags = RATE_IN_44XX },
309 { .div = 22, .val = 22, .flags = RATE_IN_4430 }, 309 { .div = 22, .val = 22, .flags = RATE_IN_44XX },
310 { .div = 23, .val = 23, .flags = RATE_IN_4430 }, 310 { .div = 23, .val = 23, .flags = RATE_IN_44XX },
311 { .div = 24, .val = 24, .flags = RATE_IN_4430 }, 311 { .div = 24, .val = 24, .flags = RATE_IN_44XX },
312 { .div = 25, .val = 25, .flags = RATE_IN_4430 }, 312 { .div = 25, .val = 25, .flags = RATE_IN_44XX },
313 { .div = 26, .val = 26, .flags = RATE_IN_4430 }, 313 { .div = 26, .val = 26, .flags = RATE_IN_44XX },
314 { .div = 27, .val = 27, .flags = RATE_IN_4430 }, 314 { .div = 27, .val = 27, .flags = RATE_IN_44XX },
315 { .div = 28, .val = 28, .flags = RATE_IN_4430 }, 315 { .div = 28, .val = 28, .flags = RATE_IN_44XX },
316 { .div = 29, .val = 29, .flags = RATE_IN_4430 }, 316 { .div = 29, .val = 29, .flags = RATE_IN_44XX },
317 { .div = 30, .val = 30, .flags = RATE_IN_4430 }, 317 { .div = 30, .val = 30, .flags = RATE_IN_44XX },
318 { .div = 31, .val = 31, .flags = RATE_IN_4430 }, 318 { .div = 31, .val = 31, .flags = RATE_IN_44XX },
319 { .div = 0 }, 319 { .div = 0 },
320}; 320};
321 321
@@ -345,9 +345,9 @@ static struct clk abe_24m_fclk = {
345}; 345};
346 346
347static const struct clksel_rate div3_1to4_rates[] = { 347static const struct clksel_rate div3_1to4_rates[] = {
348 { .div = 1, .val = 0, .flags = RATE_IN_4430 }, 348 { .div = 1, .val = 0, .flags = RATE_IN_44XX },
349 { .div = 2, .val = 1, .flags = RATE_IN_4430 }, 349 { .div = 2, .val = 1, .flags = RATE_IN_44XX },
350 { .div = 4, .val = 2, .flags = RATE_IN_4430 }, 350 { .div = 4, .val = 2, .flags = RATE_IN_44XX },
351 { .div = 0 }, 351 { .div = 0 },
352}; 352};
353 353
@@ -369,8 +369,8 @@ static struct clk abe_clk = {
369}; 369};
370 370
371static const struct clksel_rate div2_1to2_rates[] = { 371static const struct clksel_rate div2_1to2_rates[] = {
372 { .div = 1, .val = 0, .flags = RATE_IN_4430 }, 372 { .div = 1, .val = 0, .flags = RATE_IN_44XX },
373 { .div = 2, .val = 1, .flags = RATE_IN_4430 }, 373 { .div = 2, .val = 1, .flags = RATE_IN_44XX },
374 { .div = 0 }, 374 { .div = 0 },
375}; 375};
376 376
@@ -542,10 +542,10 @@ static struct clk div_core_ck = {
542}; 542};
543 543
544static const struct clksel_rate div4_1to8_rates[] = { 544static const struct clksel_rate div4_1to8_rates[] = {
545 { .div = 1, .val = 0, .flags = RATE_IN_4430 }, 545 { .div = 1, .val = 0, .flags = RATE_IN_44XX },
546 { .div = 2, .val = 1, .flags = RATE_IN_4430 }, 546 { .div = 2, .val = 1, .flags = RATE_IN_44XX },
547 { .div = 4, .val = 2, .flags = RATE_IN_4430 }, 547 { .div = 4, .val = 2, .flags = RATE_IN_44XX },
548 { .div = 8, .val = 3, .flags = RATE_IN_4430 }, 548 { .div = 8, .val = 3, .flags = RATE_IN_44XX },
549 { .div = 0 }, 549 { .div = 0 },
550}; 550};
551 551
@@ -1099,8 +1099,8 @@ static struct clk func_24mc_fclk = {
1099}; 1099};
1100 1100
1101static const struct clksel_rate div2_4to8_rates[] = { 1101static const struct clksel_rate div2_4to8_rates[] = {
1102 { .div = 4, .val = 0, .flags = RATE_IN_4430 }, 1102 { .div = 4, .val = 0, .flags = RATE_IN_44XX },
1103 { .div = 8, .val = 1, .flags = RATE_IN_4430 }, 1103 { .div = 8, .val = 1, .flags = RATE_IN_44XX },
1104 { .div = 0 }, 1104 { .div = 0 },
1105}; 1105};
1106 1106
@@ -1130,8 +1130,8 @@ static struct clk func_48mc_fclk = {
1130}; 1130};
1131 1131
1132static const struct clksel_rate div2_2to4_rates[] = { 1132static const struct clksel_rate div2_2to4_rates[] = {
1133 { .div = 2, .val = 0, .flags = RATE_IN_4430 }, 1133 { .div = 2, .val = 0, .flags = RATE_IN_44XX },
1134 { .div = 4, .val = 1, .flags = RATE_IN_4430 }, 1134 { .div = 4, .val = 1, .flags = RATE_IN_44XX },
1135 { .div = 0 }, 1135 { .div = 0 },
1136}; 1136};
1137 1137
@@ -1183,8 +1183,8 @@ static struct clk hsmmc6_fclk = {
1183}; 1183};
1184 1184
1185static const struct clksel_rate div2_1to8_rates[] = { 1185static const struct clksel_rate div2_1to8_rates[] = {
1186 { .div = 1, .val = 0, .flags = RATE_IN_4430 }, 1186 { .div = 1, .val = 0, .flags = RATE_IN_44XX },
1187 { .div = 8, .val = 1, .flags = RATE_IN_4430 }, 1187 { .div = 8, .val = 1, .flags = RATE_IN_44XX },
1188 { .div = 0 }, 1188 { .div = 0 },
1189}; 1189};
1190 1190
@@ -2751,8 +2751,8 @@ static struct clk usb_tll_hs_ick = {
2751}; 2751};
2752 2752
2753static const struct clksel_rate div2_14to18_rates[] = { 2753static const struct clksel_rate div2_14to18_rates[] = {
2754 { .div = 14, .val = 0, .flags = RATE_IN_4430 }, 2754 { .div = 14, .val = 0, .flags = RATE_IN_44XX },
2755 { .div = 18, .val = 1, .flags = RATE_IN_4430 }, 2755 { .div = 18, .val = 1, .flags = RATE_IN_44XX },
2756 { .div = 0 }, 2756 { .div = 0 },
2757}; 2757};
2758 2758
@@ -3015,284 +3015,287 @@ static struct clk auxclkreq5_ck = {
3015 */ 3015 */
3016 3016
3017static struct omap_clk omap44xx_clks[] = { 3017static struct omap_clk omap44xx_clks[] = {
3018 CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck, CK_443X), 3018 CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck, CK_44XX),
3019 CLK(NULL, "pad_clks_ck", &pad_clks_ck, CK_443X), 3019 CLK(NULL, "pad_clks_ck", &pad_clks_ck, CK_44XX),
3020 CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck, CK_443X), 3020 CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck, CK_44XX),
3021 CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_443X), 3021 CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_44XX),
3022 CLK(NULL, "slimbus_clk", &slimbus_clk, CK_443X), 3022 CLK(NULL, "slimbus_clk", &slimbus_clk, CK_44XX),
3023 CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_443X), 3023 CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_44XX),
3024 CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_443X), 3024 CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_44XX),
3025 CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_443X), 3025 CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_44XX),
3026 CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_443X), 3026 CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_44XX),
3027 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_443X), 3027 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_44XX),
3028 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_443X), 3028 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_44XX),
3029 CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X), 3029 CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_44XX),
3030 CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X), 3030 CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_44XX),
3031 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X), 3031 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_44XX),
3032 CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck, CK_443X), 3032 CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck, CK_44XX),
3033 CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X), 3033 CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_44XX),
3034 CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X), 3034 CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_44XX),
3035 CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X), 3035 CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_44XX),
3036 CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X), 3036 CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_44XX),
3037 CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X), 3037 CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_44XX),
3038 CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X), 3038 CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_44XX),
3039 CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X), 3039 CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_44XX),
3040 CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_443X), 3040 CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_44XX),
3041 CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X), 3041 CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_44XX),
3042 CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X), 3042 CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_44XX),
3043 CLK(NULL, "abe_clk", &abe_clk, CK_443X), 3043 CLK(NULL, "abe_clk", &abe_clk, CK_44XX),
3044 CLK(NULL, "aess_fclk", &aess_fclk, CK_443X), 3044 CLK(NULL, "aess_fclk", &aess_fclk, CK_44XX),
3045 CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, CK_443X), 3045 CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, CK_44XX),
3046 CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X), 3046 CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_44XX),
3047 CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X), 3047 CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_44XX),
3048 CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_443X), 3048 CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_44XX),
3049 CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck, CK_443X), 3049 CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck, CK_44XX),
3050 CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X), 3050 CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_44XX),
3051 CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X), 3051 CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_44XX),
3052 CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X), 3052 CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_44XX),
3053 CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, CK_443X), 3053 CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, CK_44XX),
3054 CLK(NULL, "div_core_ck", &div_core_ck, CK_443X), 3054 CLK(NULL, "div_core_ck", &div_core_ck, CK_44XX),
3055 CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X), 3055 CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_44XX),
3056 CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X), 3056 CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_44XX),
3057 CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, CK_443X), 3057 CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, CK_44XX),
3058 CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X), 3058 CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_44XX),
3059 CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X), 3059 CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_44XX),
3060 CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck, CK_443X), 3060 CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck, CK_44XX),
3061 CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck, CK_443X), 3061 CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck, CK_44XX),
3062 CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X), 3062 CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_44XX),
3063 CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X), 3063 CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_44XX),
3064 CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck, CK_443X), 3064 CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck, CK_44XX),
3065 CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, CK_443X), 3065 CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, CK_44XX),
3066 CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, CK_443X), 3066 CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, CK_44XX),
3067 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X), 3067 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_44XX),
3068 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X), 3068 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_44XX),
3069 CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X), 3069 CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_44XX),
3070 CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X), 3070 CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_44XX),
3071 CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X), 3071 CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_44XX),
3072 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X), 3072 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_44XX),
3073 CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_443X), 3073 CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_44XX),
3074 CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X), 3074 CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_44XX),
3075 CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck, CK_443X), 3075 CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck, CK_44XX),
3076 CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, CK_443X), 3076 CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, CK_44XX),
3077 CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X), 3077 CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_44XX),
3078 CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X), 3078 CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_44XX),
3079 CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X), 3079 CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_44XX),
3080 CLK(NULL, "dpll_unipro_ck", &dpll_unipro_ck, CK_443X), 3080 CLK(NULL, "dpll_unipro_ck", &dpll_unipro_ck, CK_44XX),
3081 CLK(NULL, "dpll_unipro_x2_ck", &dpll_unipro_x2_ck, CK_443X), 3081 CLK(NULL, "dpll_unipro_x2_ck", &dpll_unipro_x2_ck, CK_44XX),
3082 CLK(NULL, "dpll_unipro_m2x2_ck", &dpll_unipro_m2x2_ck, CK_443X), 3082 CLK(NULL, "dpll_unipro_m2x2_ck", &dpll_unipro_m2x2_ck, CK_44XX),
3083 CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X), 3083 CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_44XX),
3084 CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X), 3084 CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_44XX),
3085 CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X), 3085 CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_44XX),
3086 CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_443X), 3086 CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_44XX),
3087 CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck, CK_443X), 3087 CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck, CK_44XX),
3088 CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_443X), 3088 CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_44XX),
3089 CLK(NULL, "func_24m_clk", &func_24m_clk, CK_443X), 3089 CLK(NULL, "func_24m_clk", &func_24m_clk, CK_44XX),
3090 CLK(NULL, "func_24mc_fclk", &func_24mc_fclk, CK_443X), 3090 CLK(NULL, "func_24mc_fclk", &func_24mc_fclk, CK_44XX),
3091 CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_443X), 3091 CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_44XX),
3092 CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X), 3092 CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_44XX),
3093 CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X), 3093 CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_44XX),
3094 CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X), 3094 CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_44XX),
3095 CLK(NULL, "hsmmc6_fclk", &hsmmc6_fclk, CK_443X), 3095 CLK(NULL, "hsmmc6_fclk", &hsmmc6_fclk, CK_44XX),
3096 CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X), 3096 CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_44XX),
3097 CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X), 3097 CLK(NULL, "l3_div_ck", &l3_div_ck, CK_44XX),
3098 CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X), 3098 CLK(NULL, "l4_div_ck", &l4_div_ck, CK_44XX),
3099 CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X), 3099 CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_44XX),
3100 CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X), 3100 CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_44XX),
3101 CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X), 3101 CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_44XX),
3102 CLK(NULL, "mcasp2_fclk", &mcasp2_fclk, CK_443X), 3102 CLK(NULL, "mcasp2_fclk", &mcasp2_fclk, CK_44XX),
3103 CLK(NULL, "mcasp3_fclk", &mcasp3_fclk, CK_443X), 3103 CLK(NULL, "mcasp3_fclk", &mcasp3_fclk, CK_44XX),
3104 CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X), 3104 CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_44XX),
3105 CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X), 3105 CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_44XX),
3106 CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X), 3106 CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_44XX),
3107 CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X), 3107 CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_44XX),
3108 CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X), 3108 CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_44XX),
3109 CLK(NULL, "aes1_fck", &aes1_fck, CK_443X), 3109 CLK(NULL, "aes1_fck", &aes1_fck, CK_44XX),
3110 CLK(NULL, "aes2_fck", &aes2_fck, CK_443X), 3110 CLK(NULL, "aes2_fck", &aes2_fck, CK_44XX),
3111 CLK(NULL, "aess_fck", &aess_fck, CK_443X), 3111 CLK(NULL, "aess_fck", &aess_fck, CK_44XX),
3112 CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X), 3112 CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_44XX),
3113 CLK(NULL, "des3des_fck", &des3des_fck, CK_443X), 3113 CLK(NULL, "des3des_fck", &des3des_fck, CK_44XX),
3114 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), 3114 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_44XX),
3115 CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), 3115 CLK(NULL, "dmic_fck", &dmic_fck, CK_44XX),
3116 CLK(NULL, "dsp_fck", &dsp_fck, CK_443X), 3116 CLK(NULL, "dsp_fck", &dsp_fck, CK_44XX),
3117 CLK("omapdss_dss", "sys_clk", &dss_sys_clk, CK_443X), 3117 CLK("omapdss_dss", "sys_clk", &dss_sys_clk, CK_44XX),
3118 CLK("omapdss_dss", "tv_clk", &dss_tv_clk, CK_443X), 3118 CLK("omapdss_dss", "tv_clk", &dss_tv_clk, CK_44XX),
3119 CLK("omapdss_dss", "video_clk", &dss_48mhz_clk, CK_443X), 3119 CLK("omapdss_dss", "video_clk", &dss_48mhz_clk, CK_44XX),
3120 CLK("omapdss_dss", "fck", &dss_dss_clk, CK_443X), 3120 CLK("omapdss_dss", "fck", &dss_dss_clk, CK_44XX),
3121 CLK("omapdss_dss", "ick", &dss_fck, CK_443X), 3121 CLK("omapdss_dss", "ick", &dss_fck, CK_44XX),
3122 CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X), 3122 CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_44XX),
3123 CLK(NULL, "emif1_fck", &emif1_fck, CK_443X), 3123 CLK(NULL, "emif1_fck", &emif1_fck, CK_44XX),
3124 CLK(NULL, "emif2_fck", &emif2_fck, CK_443X), 3124 CLK(NULL, "emif2_fck", &emif2_fck, CK_44XX),
3125 CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), 3125 CLK(NULL, "fdif_fck", &fdif_fck, CK_44XX),
3126 CLK(NULL, "fpka_fck", &fpka_fck, CK_443X), 3126 CLK(NULL, "fpka_fck", &fpka_fck, CK_44XX),
3127 CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_443X), 3127 CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_44XX),
3128 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X), 3128 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_44XX),
3129 CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_443X), 3129 CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_44XX),
3130 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X), 3130 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_44XX),
3131 CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_443X), 3131 CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_44XX),
3132 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X), 3132 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_44XX),
3133 CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_443X), 3133 CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_44XX),
3134 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X), 3134 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_44XX),
3135 CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_443X), 3135 CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_44XX),
3136 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X), 3136 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_44XX),
3137 CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_443X), 3137 CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_44XX),
3138 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X), 3138 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_44XX),
3139 CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X), 3139 CLK(NULL, "gpmc_ick", &gpmc_ick, CK_44XX),
3140 CLK(NULL, "gpu_fck", &gpu_fck, CK_443X), 3140 CLK(NULL, "gpu_fck", &gpu_fck, CK_44XX),
3141 CLK("omap2_hdq.0", "fck", &hdq1w_fck, CK_443X), 3141 CLK("omap2_hdq.0", "fck", &hdq1w_fck, CK_44XX),
3142 CLK(NULL, "hsi_fck", &hsi_fck, CK_443X), 3142 CLK(NULL, "hsi_fck", &hsi_fck, CK_44XX),
3143 CLK("omap_i2c.1", "fck", &i2c1_fck, CK_443X), 3143 CLK("omap_i2c.1", "fck", &i2c1_fck, CK_44XX),
3144 CLK("omap_i2c.2", "fck", &i2c2_fck, CK_443X), 3144 CLK("omap_i2c.2", "fck", &i2c2_fck, CK_44XX),
3145 CLK("omap_i2c.3", "fck", &i2c3_fck, CK_443X), 3145 CLK("omap_i2c.3", "fck", &i2c3_fck, CK_44XX),
3146 CLK("omap_i2c.4", "fck", &i2c4_fck, CK_443X), 3146 CLK("omap_i2c.4", "fck", &i2c4_fck, CK_44XX),
3147 CLK(NULL, "ipu_fck", &ipu_fck, CK_443X), 3147 CLK(NULL, "ipu_fck", &ipu_fck, CK_44XX),
3148 CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X), 3148 CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_44XX),
3149 CLK(NULL, "iss_fck", &iss_fck, CK_443X), 3149 CLK(NULL, "iss_fck", &iss_fck, CK_44XX),
3150 CLK(NULL, "iva_fck", &iva_fck, CK_443X), 3150 CLK(NULL, "iva_fck", &iva_fck, CK_44XX),
3151 CLK(NULL, "kbd_fck", &kbd_fck, CK_443X), 3151 CLK(NULL, "kbd_fck", &kbd_fck, CK_44XX),
3152 CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_443X), 3152 CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_44XX),
3153 CLK(NULL, "l3_main_3_ick", &l3_main_3_ick, CK_443X), 3153 CLK(NULL, "l3_main_3_ick", &l3_main_3_ick, CK_44XX),
3154 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), 3154 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_44XX),
3155 CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X), 3155 CLK(NULL, "mcasp_fck", &mcasp_fck, CK_44XX),
3156 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), 3156 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_44XX),
3157 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_443X), 3157 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_44XX),
3158 CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X), 3158 CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_44XX),
3159 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_443X), 3159 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_44XX),
3160 CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X), 3160 CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_44XX),
3161 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_443X), 3161 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_44XX),
3162 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), 3162 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_44XX),
3163 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_443X), 3163 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_44XX),
3164 CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X), 3164 CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_44XX),
3165 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_443X), 3165 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_44XX),
3166 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X), 3166 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_44XX),
3167 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X), 3167 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_44XX),
3168 CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_443X), 3168 CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_44XX),
3169 CLK("omap_hsmmc.0", "fck", &mmc1_fck, CK_443X), 3169 CLK("omap_hsmmc.0", "fck", &mmc1_fck, CK_44XX),
3170 CLK("omap_hsmmc.1", "fck", &mmc2_fck, CK_443X), 3170 CLK("omap_hsmmc.1", "fck", &mmc2_fck, CK_44XX),
3171 CLK("omap_hsmmc.2", "fck", &mmc3_fck, CK_443X), 3171 CLK("omap_hsmmc.2", "fck", &mmc3_fck, CK_44XX),
3172 CLK("omap_hsmmc.3", "fck", &mmc4_fck, CK_443X), 3172 CLK("omap_hsmmc.3", "fck", &mmc4_fck, CK_44XX),
3173 CLK("omap_hsmmc.4", "fck", &mmc5_fck, CK_443X), 3173 CLK("omap_hsmmc.4", "fck", &mmc5_fck, CK_44XX),
3174 CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X), 3174 CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_44XX),
3175 CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X), 3175 CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_44XX),
3176 CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X), 3176 CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_44XX),
3177 CLK("omap_rng", "ick", &rng_ick, CK_443X), 3177 CLK("omap_rng", "ick", &rng_ick, CK_44XX),
3178 CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X), 3178 CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_44XX),
3179 CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X), 3179 CLK(NULL, "sl2if_ick", &sl2if_ick, CK_44XX),
3180 CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X), 3180 CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_44XX),
3181 CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X), 3181 CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_44XX),
3182 CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X), 3182 CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_44XX),
3183 CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X), 3183 CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_44XX),
3184 CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X), 3184 CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_44XX),
3185 CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X), 3185 CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_44XX),
3186 CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X), 3186 CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_44XX),
3187 CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X), 3187 CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_44XX),
3188 CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X), 3188 CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_44XX),
3189 CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X), 3189 CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_44XX),
3190 CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X), 3190 CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_44XX),
3191 CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X), 3191 CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_44XX),
3192 CLK(NULL, "gpt1_fck", &timer1_fck, CK_443X), 3192 CLK(NULL, "gpt1_fck", &timer1_fck, CK_44XX),
3193 CLK(NULL, "gpt10_fck", &timer10_fck, CK_443X), 3193 CLK(NULL, "gpt10_fck", &timer10_fck, CK_44XX),
3194 CLK(NULL, "gpt11_fck", &timer11_fck, CK_443X), 3194 CLK(NULL, "gpt11_fck", &timer11_fck, CK_44XX),
3195 CLK(NULL, "gpt2_fck", &timer2_fck, CK_443X), 3195 CLK(NULL, "gpt2_fck", &timer2_fck, CK_44XX),
3196 CLK(NULL, "gpt3_fck", &timer3_fck, CK_443X), 3196 CLK(NULL, "gpt3_fck", &timer3_fck, CK_44XX),
3197 CLK(NULL, "gpt4_fck", &timer4_fck, CK_443X), 3197 CLK(NULL, "gpt4_fck", &timer4_fck, CK_44XX),
3198 CLK(NULL, "gpt5_fck", &timer5_fck, CK_443X), 3198 CLK(NULL, "gpt5_fck", &timer5_fck, CK_44XX),
3199 CLK(NULL, "gpt6_fck", &timer6_fck, CK_443X), 3199 CLK(NULL, "gpt6_fck", &timer6_fck, CK_44XX),
3200 CLK(NULL, "gpt7_fck", &timer7_fck, CK_443X), 3200 CLK(NULL, "gpt7_fck", &timer7_fck, CK_44XX),
3201 CLK(NULL, "gpt8_fck", &timer8_fck, CK_443X), 3201 CLK(NULL, "gpt8_fck", &timer8_fck, CK_44XX),
3202 CLK(NULL, "gpt9_fck", &timer9_fck, CK_443X), 3202 CLK(NULL, "gpt9_fck", &timer9_fck, CK_44XX),
3203 CLK(NULL, "uart1_fck", &uart1_fck, CK_443X), 3203 CLK(NULL, "uart1_fck", &uart1_fck, CK_44XX),
3204 CLK(NULL, "uart2_fck", &uart2_fck, CK_443X), 3204 CLK(NULL, "uart2_fck", &uart2_fck, CK_44XX),
3205 CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), 3205 CLK(NULL, "uart3_fck", &uart3_fck, CK_44XX),
3206 CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), 3206 CLK(NULL, "uart4_fck", &uart4_fck, CK_44XX),
3207 CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), 3207 CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_44XX),
3208 CLK("usbhs-omap.0", "fs_fck", &usb_host_fs_fck, CK_443X), 3208 CLK("usbhs-omap.0", "fs_fck", &usb_host_fs_fck, CK_44XX),
3209 CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X), 3209 CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_44XX),
3210 CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X), 3210 CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_44XX),
3211 CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X), 3211 CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_44XX),
3212 CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X), 3212 CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_44XX),
3213 CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X), 3213 CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_44XX),
3214 CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X), 3214 CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_44XX),
3215 CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X), 3215 CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_44XX),
3216 CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X), 3216 CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_44XX),
3217 CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X), 3217 CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_44XX),
3218 CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X), 3218 CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_44XX),
3219 CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X), 3219 CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_44XX),
3220 CLK("usbhs-omap.0", "hs_fck", &usb_host_hs_fck, CK_443X), 3220 CLK("usbhs-omap.0", "hs_fck", &usb_host_hs_fck, CK_44XX),
3221 CLK("usbhs-omap.0", "usbhost_ick", &dummy_ck, CK_443X), 3221 CLK("usbhs-omap.0", "usbhost_ick", &dummy_ck, CK_44XX),
3222 CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X), 3222 CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_44XX),
3223 CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X), 3223 CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_44XX),
3224 CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X), 3224 CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_44XX),
3225 CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X), 3225 CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_44XX),
3226 CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X), 3226 CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_44XX),
3227 CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X), 3227 CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_44XX),
3228 CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X), 3228 CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_44XX),
3229 CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X), 3229 CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_44XX),
3230 CLK("usbhs-omap.0", "usbtll_ick", &usb_tll_hs_ick, CK_443X), 3230 CLK("usbhs-omap.0", "usbtll_ick", &usb_tll_hs_ick, CK_44XX),
3231 CLK("usbhs-omap.0", "usbtll_fck", &dummy_ck, CK_443X), 3231 CLK("usbhs-omap.0", "usbtll_fck", &dummy_ck, CK_44XX),
3232 CLK(NULL, "usim_ck", &usim_ck, CK_443X), 3232 CLK(NULL, "usim_ck", &usim_ck, CK_44XX),
3233 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), 3233 CLK(NULL, "usim_fclk", &usim_fclk, CK_44XX),
3234 CLK(NULL, "usim_fck", &usim_fck, CK_443X), 3234 CLK(NULL, "usim_fck", &usim_fck, CK_44XX),
3235 CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X), 3235 CLK("omap_wdt", "fck", &wd_timer2_fck, CK_44XX),
3236 CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X), 3236 CLK(NULL, "mailboxes_ick", &dummy_ck, CK_44XX),
3237 CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X), 3237 CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_44XX),
3238 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), 3238 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_44XX),
3239 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), 3239 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_44XX),
3240 CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X), 3240 CLK(NULL, "gpmc_ck", &dummy_ck, CK_44XX),
3241 CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X), 3241 CLK(NULL, "gpt1_ick", &dummy_ck, CK_44XX),
3242 CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X), 3242 CLK(NULL, "gpt2_ick", &dummy_ck, CK_44XX),
3243 CLK(NULL, "gpt3_ick", &dummy_ck, CK_443X), 3243 CLK(NULL, "gpt3_ick", &dummy_ck, CK_44XX),
3244 CLK(NULL, "gpt4_ick", &dummy_ck, CK_443X), 3244 CLK(NULL, "gpt4_ick", &dummy_ck, CK_44XX),
3245 CLK(NULL, "gpt5_ick", &dummy_ck, CK_443X), 3245 CLK(NULL, "gpt5_ick", &dummy_ck, CK_44XX),
3246 CLK(NULL, "gpt6_ick", &dummy_ck, CK_443X), 3246 CLK(NULL, "gpt6_ick", &dummy_ck, CK_44XX),
3247 CLK(NULL, "gpt7_ick", &dummy_ck, CK_443X), 3247 CLK(NULL, "gpt7_ick", &dummy_ck, CK_44XX),
3248 CLK(NULL, "gpt8_ick", &dummy_ck, CK_443X), 3248 CLK(NULL, "gpt8_ick", &dummy_ck, CK_44XX),
3249 CLK(NULL, "gpt9_ick", &dummy_ck, CK_443X), 3249 CLK(NULL, "gpt9_ick", &dummy_ck, CK_44XX),
3250 CLK(NULL, "gpt10_ick", &dummy_ck, CK_443X), 3250 CLK(NULL, "gpt10_ick", &dummy_ck, CK_44XX),
3251 CLK(NULL, "gpt11_ick", &dummy_ck, CK_443X), 3251 CLK(NULL, "gpt11_ick", &dummy_ck, CK_44XX),
3252 CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X), 3252 CLK("omap_i2c.1", "ick", &dummy_ck, CK_44XX),
3253 CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X), 3253 CLK("omap_i2c.2", "ick", &dummy_ck, CK_44XX),
3254 CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X), 3254 CLK("omap_i2c.3", "ick", &dummy_ck, CK_44XX),
3255 CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X), 3255 CLK("omap_i2c.4", "ick", &dummy_ck, CK_44XX),
3256 CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X), 3256 CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_44XX),
3257 CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X), 3257 CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_44XX),
3258 CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X), 3258 CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_44XX),
3259 CLK("omap_hsmmc.3", "ick", &dummy_ck, CK_443X), 3259 CLK("omap_hsmmc.3", "ick", &dummy_ck, CK_44XX),
3260 CLK("omap_hsmmc.4", "ick", &dummy_ck, CK_443X), 3260 CLK("omap_hsmmc.4", "ick", &dummy_ck, CK_44XX),
3261 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X), 3261 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_44XX),
3262 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X), 3262 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_44XX),
3263 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X), 3263 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_44XX),
3264 CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X), 3264 CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_44XX),
3265 CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X), 3265 CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_44XX),
3266 CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X), 3266 CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_44XX),
3267 CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X), 3267 CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_44XX),
3268 CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X), 3268 CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_44XX),
3269 CLK(NULL, "uart1_ick", &dummy_ck, CK_443X), 3269 CLK(NULL, "uart1_ick", &dummy_ck, CK_44XX),
3270 CLK(NULL, "uart2_ick", &dummy_ck, CK_443X), 3270 CLK(NULL, "uart2_ick", &dummy_ck, CK_44XX),
3271 CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), 3271 CLK(NULL, "uart3_ick", &dummy_ck, CK_44XX),
3272 CLK(NULL, "uart4_ick", &dummy_ck, CK_443X), 3272 CLK(NULL, "uart4_ick", &dummy_ck, CK_44XX),
3273 CLK("omap_wdt", "ick", &dummy_ck, CK_443X), 3273 CLK("omap_wdt", "ick", &dummy_ck, CK_44XX),
3274 CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X), 3274 CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_44XX),
3275 CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X), 3275 CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_44XX),
3276 CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X), 3276 CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_44XX),
3277 CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X), 3277 CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_44XX),
3278 CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X), 3278 CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_44XX),
3279 CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X), 3279 CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_44XX),
3280 CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X), 3280 CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_44XX),
3281 CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X), 3281 CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_44XX),
3282 CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X), 3282 CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_44XX),
3283 CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X), 3283 CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_44XX),
3284 CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X), 3284 CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_44XX),
3285 CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X), 3285 CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_44XX),
3286}; 3286};
3287 3287
3288int __init omap4xxx_clk_init(void) 3288int __init omap4xxx_clk_init(void)
3289{ 3289{
3290 struct omap_clk *c; 3290 struct omap_clk *c;
3291 u32 cpu_clkflg; 3291 u32 cpu_clkflg = 0;
3292 3292
3293 if (cpu_is_omap44xx()) { 3293 if (cpu_is_omap443x()) {
3294 cpu_mask = RATE_IN_4430; 3294 cpu_mask = RATE_IN_4430;
3295 cpu_clkflg = CK_443X; 3295 cpu_clkflg = CK_443X;
3296 } else if (cpu_is_omap446x()) {
3297 cpu_mask = RATE_IN_446X;
3298 cpu_clkflg = CK_446X;
3296 } 3299 }
3297 3300
3298 clk_init(&omap2_clk_functions); 3301 clk_init(&omap2_clk_functions);
diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h
index f1899a3e417..324446bfd28 100644
--- a/arch/arm/plat-omap/include/plat/clkdev_omap.h
+++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h
@@ -39,11 +39,13 @@ struct omap_clk {
39#define CK_36XX (1 << 10) /* 36xx/37xx-specific clocks */ 39#define CK_36XX (1 << 10) /* 36xx/37xx-specific clocks */
40#define CK_443X (1 << 11) 40#define CK_443X (1 << 11)
41#define CK_TI816X (1 << 12) 41#define CK_TI816X (1 << 12)
42#define CK_446X (1 << 13)
42 43
43 44
44#define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS) 45#define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS)
45#define CK_AM35XX (CK_3505 | CK_3517) /* all Sitara AM35xx */ 46#define CK_AM35XX (CK_3505 | CK_3517) /* all Sitara AM35xx */
46#define CK_3XXX (CK_34XX | CK_AM35XX | CK_36XX) 47#define CK_3XXX (CK_34XX | CK_AM35XX | CK_36XX)
48#define CK_44XX (CK_443X | CK_446X)
47 49
48 50
49#endif 51#endif
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 006e599c661..973b7dc3e84 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -58,10 +58,12 @@ struct clkops {
58#define RATE_IN_36XX (1 << 4) 58#define RATE_IN_36XX (1 << 4)
59#define RATE_IN_4430 (1 << 5) 59#define RATE_IN_4430 (1 << 5)
60#define RATE_IN_TI816X (1 << 6) 60#define RATE_IN_TI816X (1 << 6)
61#define RATE_IN_446X (1 << 7)
61 62
62#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) 63#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
63#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS) 64#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
64#define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX) 65#define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX)
66#define RATE_IN_44XX (RATE_IN_4430 | RATE_IN_446X)
65 67
66/* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */ 68/* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
67#define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX) 69#define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX)
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-31 17:35:54 -0400