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authorHari Kanigeri <h-kanigeri2@ti.com>2010-09-15 01:35:03 -0400
committerPaolo Pisati <paolo.pisati@canonical.com>2012-08-17 04:19:17 -0400
commit13854bf25971da775dbec5545879c14ce66dd0a4 (patch)
tree9af5817e4d3701fc3934579dd9abb0d016c896eb /arch/arm
parentcd6629d28e31f626f305091c33a6add4c161111c (diff)
OMAP: SYSLINK: cacheflush
Revert "ARM: dma-mapping: remove dmac_clean_range and dmac_inv_range" This reverts commit 702b94bff3c50542a6e4ab9a4f4cef093262fe65 Signed-off-by: Hari Kanigeri <h-kanigeri2@ti.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/include/asm/cacheflush.h21
-rw-r--r--arch/arm/include/asm/glue-cache.h2
-rw-r--r--arch/arm/mm/cache-fa.S6
-rw-r--r--arch/arm/mm/cache-v3.S29
-rw-r--r--arch/arm/mm/cache-v4.S29
-rw-r--r--arch/arm/mm/cache-v4wb.S6
-rw-r--r--arch/arm/mm/cache-v4wt.S15
-rw-r--r--arch/arm/mm/cache-v6.S6
-rw-r--r--arch/arm/mm/cache-v7.S6
-rw-r--r--arch/arm/mm/proc-arm1020.S6
-rw-r--r--arch/arm/mm/proc-arm1020e.S6
-rw-r--r--arch/arm/mm/proc-arm1022.S6
-rw-r--r--arch/arm/mm/proc-arm1026.S6
-rw-r--r--arch/arm/mm/proc-arm920.S6
-rw-r--r--arch/arm/mm/proc-arm922.S6
-rw-r--r--arch/arm/mm/proc-arm925.S6
-rw-r--r--arch/arm/mm/proc-arm926.S6
-rw-r--r--arch/arm/mm/proc-arm940.S6
-rw-r--r--arch/arm/mm/proc-arm946.S6
-rw-r--r--arch/arm/mm/proc-feroceon.S12
-rw-r--r--arch/arm/mm/proc-mohawk.S6
-rw-r--r--arch/arm/mm/proc-xsc3.S6
-rw-r--r--arch/arm/mm/proc-xscale.S8
23 files changed, 171 insertions, 41 deletions
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 1252a2675ca..584fe0b6fcd 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -87,6 +87,21 @@
87 * DMA Cache Coherency 87 * DMA Cache Coherency
88 * =================== 88 * ===================
89 * 89 *
90 * dma_inv_range(start, end)
91 *
92 * Invalidate (discard) the specified virtual address range.
93 * May not write back any entries. If 'start' or 'end'
94 * are not cache line aligned, those lines must be written
95 * back.
96 * - start - virtual start address
97 * - end - virtual end address
98 *
99 * dma_clean_range(start, end)
100 *
101 * Clean (write back) the specified virtual address range.
102 * - start - virtual start address
103 * - end - virtual end address
104 *
90 * dma_flush_range(start, end) 105 * dma_flush_range(start, end)
91 * 106 *
92 * Clean and invalidate the specified virtual address range. 107 * Clean and invalidate the specified virtual address range.
@@ -107,6 +122,8 @@ struct cpu_cache_fns {
107 void (*dma_map_area)(const void *, size_t, int); 122 void (*dma_map_area)(const void *, size_t, int);
108 void (*dma_unmap_area)(const void *, size_t, int); 123 void (*dma_unmap_area)(const void *, size_t, int);
109 124
125 void (*dma_inv_range)(const void *, const void *);
126 void (*dma_clean_range)(const void *, const void *);
110 void (*dma_flush_range)(const void *, const void *); 127 void (*dma_flush_range)(const void *, const void *);
111}; 128};
112 129
@@ -133,6 +150,8 @@ extern struct cpu_cache_fns cpu_cache;
133 */ 150 */
134#define dmac_map_area cpu_cache.dma_map_area 151#define dmac_map_area cpu_cache.dma_map_area
135#define dmac_unmap_area cpu_cache.dma_unmap_area 152#define dmac_unmap_area cpu_cache.dma_unmap_area
153#define dmac_inv_range cpu_cache.dma_inv_range
154#define dmac_clean_range cpu_cache.dma_clean_range
136#define dmac_flush_range cpu_cache.dma_flush_range 155#define dmac_flush_range cpu_cache.dma_flush_range
137 156
138#else 157#else
@@ -153,6 +172,8 @@ extern void __cpuc_flush_dcache_area(void *, size_t);
153 */ 172 */
154extern void dmac_map_area(const void *, size_t, int); 173extern void dmac_map_area(const void *, size_t, int);
155extern void dmac_unmap_area(const void *, size_t, int); 174extern void dmac_unmap_area(const void *, size_t, int);
175extern void dmac_inv_range(const void *, const void *);
176extern void dmac_clean_range(const void *, const void *);
156extern void dmac_flush_range(const void *, const void *); 177extern void dmac_flush_range(const void *, const void *);
157 178
158#endif 179#endif
diff --git a/arch/arm/include/asm/glue-cache.h b/arch/arm/include/asm/glue-cache.h
index 7e30874377e..65de567cf7c 100644
--- a/arch/arm/include/asm/glue-cache.h
+++ b/arch/arm/include/asm/glue-cache.h
@@ -140,6 +140,8 @@
140 140
141#define dmac_map_area __glue(_CACHE,_dma_map_area) 141#define dmac_map_area __glue(_CACHE,_dma_map_area)
142#define dmac_unmap_area __glue(_CACHE,_dma_unmap_area) 142#define dmac_unmap_area __glue(_CACHE,_dma_unmap_area)
143#define dmac_inv_range __glue(_CACHE,_dma_inv_range)
144#define dmac_clean_range __glue(_CACHE,_dma_clean_range)
143#define dmac_flush_range __glue(_CACHE,_dma_flush_range) 145#define dmac_flush_range __glue(_CACHE,_dma_flush_range)
144#endif 146#endif
145 147
diff --git a/arch/arm/mm/cache-fa.S b/arch/arm/mm/cache-fa.S
index 1fa6f71470d..ad953fe4ef5 100644
--- a/arch/arm/mm/cache-fa.S
+++ b/arch/arm/mm/cache-fa.S
@@ -168,7 +168,7 @@ ENTRY(fa_flush_kern_dcache_area)
168 * - start - virtual start address 168 * - start - virtual start address
169 * - end - virtual end address 169 * - end - virtual end address
170 */ 170 */
171fa_dma_inv_range: 171ENTRY(fa_dma_inv_range)
172 tst r0, #CACHE_DLINESIZE - 1 172 tst r0, #CACHE_DLINESIZE - 1
173 bic r0, r0, #CACHE_DLINESIZE - 1 173 bic r0, r0, #CACHE_DLINESIZE - 1
174 mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry 174 mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry
@@ -191,7 +191,7 @@ fa_dma_inv_range:
191 * - start - virtual start address 191 * - start - virtual start address
192 * - end - virtual end address 192 * - end - virtual end address
193 */ 193 */
194fa_dma_clean_range: 194ENTRY(fa_dma_clean_range)
195 bic r0, r0, #CACHE_DLINESIZE - 1 195 bic r0, r0, #CACHE_DLINESIZE - 1
1961: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 1961: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
197 add r0, r0, #CACHE_DLINESIZE 197 add r0, r0, #CACHE_DLINESIZE
@@ -253,5 +253,7 @@ ENTRY(fa_cache_fns)
253 .long fa_flush_kern_dcache_area 253 .long fa_flush_kern_dcache_area
254 .long fa_dma_map_area 254 .long fa_dma_map_area
255 .long fa_dma_unmap_area 255 .long fa_dma_unmap_area
256 .long fa_dma_inv_range
257 .long fa_dma_clean_range
256 .long fa_dma_flush_range 258 .long fa_dma_flush_range
257 .size fa_cache_fns, . - fa_cache_fns 259 .size fa_cache_fns, . - fa_cache_fns
diff --git a/arch/arm/mm/cache-v3.S b/arch/arm/mm/cache-v3.S
index 2e2bc406a18..64f739eaa4c 100644
--- a/arch/arm/mm/cache-v3.S
+++ b/arch/arm/mm/cache-v3.S
@@ -93,6 +93,20 @@ ENTRY(v3_flush_kern_dcache_area)
93 /* FALLTHROUGH */ 93 /* FALLTHROUGH */
94 94
95/* 95/*
96 * dma_inv_range(start, end)
97 *
98 * Invalidate (discard) the specified virtual address range.
99 * May not write back any entries. If 'start' or 'end'
100 * are not cache line aligned, those lines must be written
101 * back.
102 *
103 * - start - virtual start address
104 * - end - virtual end address
105 */
106ENTRY(v3_dma_inv_range)
107 /* FALLTHROUGH */
108
109/*
96 * dma_flush_range(start, end) 110 * dma_flush_range(start, end)
97 * 111 *
98 * Clean and invalidate the specified virtual address range. 112 * Clean and invalidate the specified virtual address range.
@@ -103,6 +117,17 @@ ENTRY(v3_flush_kern_dcache_area)
103ENTRY(v3_dma_flush_range) 117ENTRY(v3_dma_flush_range)
104 mov r0, #0 118 mov r0, #0
105 mcr p15, 0, r0, c7, c0, 0 @ flush ID cache 119 mcr p15, 0, r0, c7, c0, 0 @ flush ID cache
120 /* FALLTHROUGH */
121
122/*
123 * dma_clean_range(start, end)
124 *
125 * Clean (write back) the specified virtual address range.
126 *
127 * - start - virtual start address
128 * - end - virtual end address
129 */
130ENTRY(v3_dma_clean_range)
106 mov pc, lr 131 mov pc, lr
107 132
108/* 133/*
@@ -113,7 +138,7 @@ ENTRY(v3_dma_flush_range)
113 */ 138 */
114ENTRY(v3_dma_unmap_area) 139ENTRY(v3_dma_unmap_area)
115 teq r2, #DMA_TO_DEVICE 140 teq r2, #DMA_TO_DEVICE
116 bne v3_dma_flush_range 141 bne v3_dma_inv_range
117 /* FALLTHROUGH */ 142 /* FALLTHROUGH */
118 143
119/* 144/*
@@ -140,5 +165,7 @@ ENTRY(v3_cache_fns)
140 .long v3_flush_kern_dcache_area 165 .long v3_flush_kern_dcache_area
141 .long v3_dma_map_area 166 .long v3_dma_map_area
142 .long v3_dma_unmap_area 167 .long v3_dma_unmap_area
168 .long v3_dma_inv_range
169 .long v3_dma_clean_range
143 .long v3_dma_flush_range 170 .long v3_dma_flush_range
144 .size v3_cache_fns, . - v3_cache_fns 171 .size v3_cache_fns, . - v3_cache_fns
diff --git a/arch/arm/mm/cache-v4.S b/arch/arm/mm/cache-v4.S
index a8fefb523f1..7824cf6e14a 100644
--- a/arch/arm/mm/cache-v4.S
+++ b/arch/arm/mm/cache-v4.S
@@ -103,6 +103,20 @@ ENTRY(v4_flush_kern_dcache_area)
103 /* FALLTHROUGH */ 103 /* FALLTHROUGH */
104 104
105/* 105/*
106 * dma_inv_range(start, end)
107 *
108 * Invalidate (discard) the specified virtual address range.
109 * May not write back any entries. If 'start' or 'end'
110 * are not cache line aligned, those lines must be written
111 * back.
112 *
113 * - start - virtual start address
114 * - end - virtual end address
115 */
116ENTRY(v4_dma_inv_range)
117 /* FALLTHROUGH */
118
119/*
106 * dma_flush_range(start, end) 120 * dma_flush_range(start, end)
107 * 121 *
108 * Clean and invalidate the specified virtual address range. 122 * Clean and invalidate the specified virtual address range.
@@ -115,6 +129,17 @@ ENTRY(v4_dma_flush_range)
115 mov r0, #0 129 mov r0, #0
116 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache 130 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
117#endif 131#endif
132 /* FALLTHROUGH */
133
134/*
135 * dma_clean_range(start, end)
136 *
137 * Clean (write back) the specified virtual address range.
138 *
139 * - start - virtual start address
140 * - end - virtual end address
141 */
142ENTRY(v4_dma_clean_range)
118 mov pc, lr 143 mov pc, lr
119 144
120/* 145/*
@@ -125,7 +150,7 @@ ENTRY(v4_dma_flush_range)
125 */ 150 */
126ENTRY(v4_dma_unmap_area) 151ENTRY(v4_dma_unmap_area)
127 teq r2, #DMA_TO_DEVICE 152 teq r2, #DMA_TO_DEVICE
128 bne v4_dma_flush_range 153 bne v4_dma_inv_range
129 /* FALLTHROUGH */ 154 /* FALLTHROUGH */
130 155
131/* 156/*
@@ -152,5 +177,7 @@ ENTRY(v4_cache_fns)
152 .long v4_flush_kern_dcache_area 177 .long v4_flush_kern_dcache_area
153 .long v4_dma_map_area 178 .long v4_dma_map_area
154 .long v4_dma_unmap_area 179 .long v4_dma_unmap_area
180 .long v4_dma_inv_range
181 .long v4_dma_clean_range
155 .long v4_dma_flush_range 182 .long v4_dma_flush_range
156 .size v4_cache_fns, . - v4_cache_fns 183 .size v4_cache_fns, . - v4_cache_fns
diff --git a/arch/arm/mm/cache-v4wb.S b/arch/arm/mm/cache-v4wb.S
index f40c69656d8..acbdaeb04e2 100644
--- a/arch/arm/mm/cache-v4wb.S
+++ b/arch/arm/mm/cache-v4wb.S
@@ -184,7 +184,7 @@ ENTRY(v4wb_coherent_user_range)
184 * - start - virtual start address 184 * - start - virtual start address
185 * - end - virtual end address 185 * - end - virtual end address
186 */ 186 */
187v4wb_dma_inv_range: 187ENTRY(v4wb_dma_inv_range)
188 tst r0, #CACHE_DLINESIZE - 1 188 tst r0, #CACHE_DLINESIZE - 1
189 bic r0, r0, #CACHE_DLINESIZE - 1 189 bic r0, r0, #CACHE_DLINESIZE - 1
190 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 190 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
@@ -205,7 +205,7 @@ v4wb_dma_inv_range:
205 * - start - virtual start address 205 * - start - virtual start address
206 * - end - virtual end address 206 * - end - virtual end address
207 */ 207 */
208v4wb_dma_clean_range: 208ENTRY(v4wb_dma_clean_range)
209 bic r0, r0, #CACHE_DLINESIZE - 1 209 bic r0, r0, #CACHE_DLINESIZE - 1
2101: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 2101: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
211 add r0, r0, #CACHE_DLINESIZE 211 add r0, r0, #CACHE_DLINESIZE
@@ -264,5 +264,7 @@ ENTRY(v4wb_cache_fns)
264 .long v4wb_flush_kern_dcache_area 264 .long v4wb_flush_kern_dcache_area
265 .long v4wb_dma_map_area 265 .long v4wb_dma_map_area
266 .long v4wb_dma_unmap_area 266 .long v4wb_dma_unmap_area
267 .long v4wb_dma_inv_range
268 .long v4wb_dma_clean_range
267 .long v4wb_dma_flush_range 269 .long v4wb_dma_flush_range
268 .size v4wb_cache_fns, . - v4wb_cache_fns 270 .size v4wb_cache_fns, . - v4wb_cache_fns
diff --git a/arch/arm/mm/cache-v4wt.S b/arch/arm/mm/cache-v4wt.S
index a7b276dbda1..5f60392c875 100644
--- a/arch/arm/mm/cache-v4wt.S
+++ b/arch/arm/mm/cache-v4wt.S
@@ -153,12 +153,23 @@ ENTRY(v4wt_flush_kern_dcache_area)
153 * - start - virtual start address 153 * - start - virtual start address
154 * - end - virtual end address 154 * - end - virtual end address
155 */ 155 */
156v4wt_dma_inv_range: 156ENTRY(v4wt_dma_inv_range)
157 bic r0, r0, #CACHE_DLINESIZE - 1 157 bic r0, r0, #CACHE_DLINESIZE - 1
1581: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 1581: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
159 add r0, r0, #CACHE_DLINESIZE 159 add r0, r0, #CACHE_DLINESIZE
160 cmp r0, r1 160 cmp r0, r1
161 blo 1b 161 blo 1b
162 /* FALLTHROUGH */
163
164/*
165 * dma_clean_range(start, end)
166 *
167 * Clean the specified virtual address range.
168 *
169 * - start - virtual start address
170 * - end - virtual end address
171 */
172ENTRY(v4wt_dma_clean_range)
162 mov pc, lr 173 mov pc, lr
163 174
164/* 175/*
@@ -208,5 +219,7 @@ ENTRY(v4wt_cache_fns)
208 .long v4wt_flush_kern_dcache_area 219 .long v4wt_flush_kern_dcache_area
209 .long v4wt_dma_map_area 220 .long v4wt_dma_map_area
210 .long v4wt_dma_unmap_area 221 .long v4wt_dma_unmap_area
222 .long v4wt_dma_inv_range
223 .long v4wt_dma_clean_range
211 .long v4wt_dma_flush_range 224 .long v4wt_dma_flush_range
212 .size v4wt_cache_fns, . - v4wt_cache_fns 225 .size v4wt_cache_fns, . - v4wt_cache_fns
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index 73b4a8b66a5..f8233d52e0c 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -203,7 +203,7 @@ ENTRY(v6_flush_kern_dcache_area)
203 * - start - virtual start address of region 203 * - start - virtual start address of region
204 * - end - virtual end address of region 204 * - end - virtual end address of region
205 */ 205 */
206v6_dma_inv_range: 206ENTRY(v6_dma_inv_range)
207#ifdef CONFIG_DMA_CACHE_RWFO 207#ifdef CONFIG_DMA_CACHE_RWFO
208 ldrb r2, [r0] @ read for ownership 208 ldrb r2, [r0] @ read for ownership
209 strb r2, [r0] @ write for ownership 209 strb r2, [r0] @ write for ownership
@@ -248,7 +248,7 @@ v6_dma_inv_range:
248 * - start - virtual start address of region 248 * - start - virtual start address of region
249 * - end - virtual end address of region 249 * - end - virtual end address of region
250 */ 250 */
251v6_dma_clean_range: 251ENTRY(v6_dma_clean_range)
252 bic r0, r0, #D_CACHE_LINE_SIZE - 1 252 bic r0, r0, #D_CACHE_LINE_SIZE - 1
2531: 2531:
254#ifdef CONFIG_DMA_CACHE_RWFO 254#ifdef CONFIG_DMA_CACHE_RWFO
@@ -341,5 +341,7 @@ ENTRY(v6_cache_fns)
341 .long v6_flush_kern_dcache_area 341 .long v6_flush_kern_dcache_area
342 .long v6_dma_map_area 342 .long v6_dma_map_area
343 .long v6_dma_unmap_area 343 .long v6_dma_unmap_area
344 .long v6_dma_inv_range
345 .long v6_dma_clean_range
344 .long v6_dma_flush_range 346 .long v6_dma_flush_range
345 .size v6_cache_fns, . - v6_cache_fns 347 .size v6_cache_fns, . - v6_cache_fns
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 1ed1fd36130..f74810951fd 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -256,7 +256,7 @@ ENDPROC(v7_flush_kern_dcache_area)
256 * - start - virtual start address of region 256 * - start - virtual start address of region
257 * - end - virtual end address of region 257 * - end - virtual end address of region
258 */ 258 */
259v7_dma_inv_range: 259ENTRY(v7_dma_inv_range)
260 dcache_line_size r2, r3 260 dcache_line_size r2, r3
261 sub r3, r2, #1 261 sub r3, r2, #1
262 tst r0, r3 262 tst r0, r3
@@ -284,7 +284,7 @@ ENDPROC(v7_dma_inv_range)
284 * - start - virtual start address of region 284 * - start - virtual start address of region
285 * - end - virtual end address of region 285 * - end - virtual end address of region
286 */ 286 */
287v7_dma_clean_range: 287ENTRY(v7_dma_clean_range)
288 dcache_line_size r2, r3 288 dcache_line_size r2, r3
289 sub r3, r2, #1 289 sub r3, r2, #1
290 bic r0, r0, r3 290 bic r0, r0, r3
@@ -362,5 +362,7 @@ ENTRY(v7_cache_fns)
362 .long v7_flush_kern_dcache_area 362 .long v7_flush_kern_dcache_area
363 .long v7_dma_map_area 363 .long v7_dma_map_area
364 .long v7_dma_unmap_area 364 .long v7_dma_unmap_area
365 .long v7_dma_inv_range
366 .long v7_dma_clean_range
365 .long v7_dma_flush_range 367 .long v7_dma_flush_range
366 .size v7_cache_fns, . - v7_cache_fns 368 .size v7_cache_fns, . - v7_cache_fns
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index 6c4e7fd6c8a..843b5c88ae5 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -275,7 +275,7 @@ ENTRY(arm1020_flush_kern_dcache_area)
275 * 275 *
276 * (same as v4wb) 276 * (same as v4wb)
277 */ 277 */
278arm1020_dma_inv_range: 278ENTRY(arm1020_dma_inv_range)
279 mov ip, #0 279 mov ip, #0
280#ifndef CONFIG_CPU_DCACHE_DISABLE 280#ifndef CONFIG_CPU_DCACHE_DISABLE
281 tst r0, #CACHE_DLINESIZE - 1 281 tst r0, #CACHE_DLINESIZE - 1
@@ -305,7 +305,7 @@ arm1020_dma_inv_range:
305 * 305 *
306 * (same as v4wb) 306 * (same as v4wb)
307 */ 307 */
308arm1020_dma_clean_range: 308ENTRY(arm1020_dma_clean_range)
309 mov ip, #0 309 mov ip, #0
310#ifndef CONFIG_CPU_DCACHE_DISABLE 310#ifndef CONFIG_CPU_DCACHE_DISABLE
311 bic r0, r0, #CACHE_DLINESIZE - 1 311 bic r0, r0, #CACHE_DLINESIZE - 1
@@ -374,6 +374,8 @@ ENTRY(arm1020_cache_fns)
374 .long arm1020_flush_kern_dcache_area 374 .long arm1020_flush_kern_dcache_area
375 .long arm1020_dma_map_area 375 .long arm1020_dma_map_area
376 .long arm1020_dma_unmap_area 376 .long arm1020_dma_unmap_area
377 .long arm1020_dma_inv_range
378 .long arm1020_dma_clean_range
377 .long arm1020_dma_flush_range 379 .long arm1020_dma_flush_range
378 380
379 .align 5 381 .align 5
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index 4ce947c1962..356b9c98f64 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -268,7 +268,7 @@ ENTRY(arm1020e_flush_kern_dcache_area)
268 * 268 *
269 * (same as v4wb) 269 * (same as v4wb)
270 */ 270 */
271arm1020e_dma_inv_range: 271ENTRY(arm1020e_dma_inv_range)
272 mov ip, #0 272 mov ip, #0
273#ifndef CONFIG_CPU_DCACHE_DISABLE 273#ifndef CONFIG_CPU_DCACHE_DISABLE
274 tst r0, #CACHE_DLINESIZE - 1 274 tst r0, #CACHE_DLINESIZE - 1
@@ -294,7 +294,7 @@ arm1020e_dma_inv_range:
294 * 294 *
295 * (same as v4wb) 295 * (same as v4wb)
296 */ 296 */
297arm1020e_dma_clean_range: 297ENTRY(arm1020e_dma_clean_range)
298 mov ip, #0 298 mov ip, #0
299#ifndef CONFIG_CPU_DCACHE_DISABLE 299#ifndef CONFIG_CPU_DCACHE_DISABLE
300 bic r0, r0, #CACHE_DLINESIZE - 1 300 bic r0, r0, #CACHE_DLINESIZE - 1
@@ -360,6 +360,8 @@ ENTRY(arm1020e_cache_fns)
360 .long arm1020e_flush_kern_dcache_area 360 .long arm1020e_flush_kern_dcache_area
361 .long arm1020e_dma_map_area 361 .long arm1020e_dma_map_area
362 .long arm1020e_dma_unmap_area 362 .long arm1020e_dma_unmap_area
363 .long arm1020e_dma_inv_range
364 .long arm1020e_dma_clean_range
363 .long arm1020e_dma_flush_range 365 .long arm1020e_dma_flush_range
364 366
365 .align 5 367 .align 5
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index c8884c5413a..b79de1148bc 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -257,7 +257,7 @@ ENTRY(arm1022_flush_kern_dcache_area)
257 * 257 *
258 * (same as v4wb) 258 * (same as v4wb)
259 */ 259 */
260arm1022_dma_inv_range: 260ENTRY(arm1022_dma_inv_range)
261 mov ip, #0 261 mov ip, #0
262#ifndef CONFIG_CPU_DCACHE_DISABLE 262#ifndef CONFIG_CPU_DCACHE_DISABLE
263 tst r0, #CACHE_DLINESIZE - 1 263 tst r0, #CACHE_DLINESIZE - 1
@@ -283,7 +283,7 @@ arm1022_dma_inv_range:
283 * 283 *
284 * (same as v4wb) 284 * (same as v4wb)
285 */ 285 */
286arm1022_dma_clean_range: 286ENTRY(arm1022_dma_clean_range)
287 mov ip, #0 287 mov ip, #0
288#ifndef CONFIG_CPU_DCACHE_DISABLE 288#ifndef CONFIG_CPU_DCACHE_DISABLE
289 bic r0, r0, #CACHE_DLINESIZE - 1 289 bic r0, r0, #CACHE_DLINESIZE - 1
@@ -349,6 +349,8 @@ ENTRY(arm1022_cache_fns)
349 .long arm1022_flush_kern_dcache_area 349 .long arm1022_flush_kern_dcache_area
350 .long arm1022_dma_map_area 350 .long arm1022_dma_map_area
351 .long arm1022_dma_unmap_area 351 .long arm1022_dma_unmap_area
352 .long arm1022_dma_inv_range
353 .long arm1022_dma_clean_range
352 .long arm1022_dma_flush_range 354 .long arm1022_dma_flush_range
353 355
354 .align 5 356 .align 5
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 413684660aa..dfeb57f33af 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -251,7 +251,7 @@ ENTRY(arm1026_flush_kern_dcache_area)
251 * 251 *
252 * (same as v4wb) 252 * (same as v4wb)
253 */ 253 */
254arm1026_dma_inv_range: 254ENTRY(arm1026_dma_inv_range)
255 mov ip, #0 255 mov ip, #0
256#ifndef CONFIG_CPU_DCACHE_DISABLE 256#ifndef CONFIG_CPU_DCACHE_DISABLE
257 tst r0, #CACHE_DLINESIZE - 1 257 tst r0, #CACHE_DLINESIZE - 1
@@ -277,7 +277,7 @@ arm1026_dma_inv_range:
277 * 277 *
278 * (same as v4wb) 278 * (same as v4wb)
279 */ 279 */
280arm1026_dma_clean_range: 280ENTRY(arm1026_dma_clean_range)
281 mov ip, #0 281 mov ip, #0
282#ifndef CONFIG_CPU_DCACHE_DISABLE 282#ifndef CONFIG_CPU_DCACHE_DISABLE
283 bic r0, r0, #CACHE_DLINESIZE - 1 283 bic r0, r0, #CACHE_DLINESIZE - 1
@@ -343,6 +343,8 @@ ENTRY(arm1026_cache_fns)
343 .long arm1026_flush_kern_dcache_area 343 .long arm1026_flush_kern_dcache_area
344 .long arm1026_dma_map_area 344 .long arm1026_dma_map_area
345 .long arm1026_dma_unmap_area 345 .long arm1026_dma_unmap_area
346 .long arm1026_dma_inv_range
347 .long arm1026_dma_clean_range
346 .long arm1026_dma_flush_range 348 .long arm1026_dma_flush_range
347 349
348 .align 5 350 .align 5
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index bf8a1d1cccb..8467b20d05d 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -242,7 +242,7 @@ ENTRY(arm920_flush_kern_dcache_area)
242 * 242 *
243 * (same as v4wb) 243 * (same as v4wb)
244 */ 244 */
245arm920_dma_inv_range: 245ENTRY(arm920_dma_inv_range)
246 tst r0, #CACHE_DLINESIZE - 1 246 tst r0, #CACHE_DLINESIZE - 1
247 bic r0, r0, #CACHE_DLINESIZE - 1 247 bic r0, r0, #CACHE_DLINESIZE - 1
248 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 248 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
@@ -265,7 +265,7 @@ arm920_dma_inv_range:
265 * 265 *
266 * (same as v4wb) 266 * (same as v4wb)
267 */ 267 */
268arm920_dma_clean_range: 268ENTRY(arm920_dma_clean_range)
269 bic r0, r0, #CACHE_DLINESIZE - 1 269 bic r0, r0, #CACHE_DLINESIZE - 1
2701: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 2701: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
271 add r0, r0, #CACHE_DLINESIZE 271 add r0, r0, #CACHE_DLINESIZE
@@ -325,6 +325,8 @@ ENTRY(arm920_cache_fns)
325 .long arm920_flush_kern_dcache_area 325 .long arm920_flush_kern_dcache_area
326 .long arm920_dma_map_area 326 .long arm920_dma_map_area
327 .long arm920_dma_unmap_area 327 .long arm920_dma_unmap_area
328 .long arm920_dma_inv_range
329 .long arm920_dma_clean_range
328 .long arm920_dma_flush_range 330 .long arm920_dma_flush_range
329 331
330#endif 332#endif
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index 95ba1fc56e4..a7d9f56d483 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -244,7 +244,7 @@ ENTRY(arm922_flush_kern_dcache_area)
244 * 244 *
245 * (same as v4wb) 245 * (same as v4wb)
246 */ 246 */
247arm922_dma_inv_range: 247ENTRY(arm922_dma_inv_range)
248 tst r0, #CACHE_DLINESIZE - 1 248 tst r0, #CACHE_DLINESIZE - 1
249 bic r0, r0, #CACHE_DLINESIZE - 1 249 bic r0, r0, #CACHE_DLINESIZE - 1
250 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 250 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
@@ -267,7 +267,7 @@ arm922_dma_inv_range:
267 * 267 *
268 * (same as v4wb) 268 * (same as v4wb)
269 */ 269 */
270arm922_dma_clean_range: 270ENTRY(arm922_dma_clean_range)
271 bic r0, r0, #CACHE_DLINESIZE - 1 271 bic r0, r0, #CACHE_DLINESIZE - 1
2721: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 2721: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
273 add r0, r0, #CACHE_DLINESIZE 273 add r0, r0, #CACHE_DLINESIZE
@@ -327,6 +327,8 @@ ENTRY(arm922_cache_fns)
327 .long arm922_flush_kern_dcache_area 327 .long arm922_flush_kern_dcache_area
328 .long arm922_dma_map_area 328 .long arm922_dma_map_area
329 .long arm922_dma_unmap_area 329 .long arm922_dma_unmap_area
330 .long arm922_dma_inv_range
331 .long arm922_dma_clean_range
330 .long arm922_dma_flush_range 332 .long arm922_dma_flush_range
331 333
332#endif 334#endif
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 541e4774eea..11c29f0b5af 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -290,7 +290,7 @@ ENTRY(arm925_flush_kern_dcache_area)
290 * 290 *
291 * (same as v4wb) 291 * (same as v4wb)
292 */ 292 */
293arm925_dma_inv_range: 293ENTRY(arm925_dma_inv_range)
294#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 294#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
295 tst r0, #CACHE_DLINESIZE - 1 295 tst r0, #CACHE_DLINESIZE - 1
296 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 296 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
@@ -315,7 +315,7 @@ arm925_dma_inv_range:
315 * 315 *
316 * (same as v4wb) 316 * (same as v4wb)
317 */ 317 */
318arm925_dma_clean_range: 318ENTRY(arm925_dma_clean_range)
319#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 319#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
320 bic r0, r0, #CACHE_DLINESIZE - 1 320 bic r0, r0, #CACHE_DLINESIZE - 1
3211: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 3211: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
@@ -382,6 +382,8 @@ ENTRY(arm925_cache_fns)
382 .long arm925_flush_kern_dcache_area 382 .long arm925_flush_kern_dcache_area
383 .long arm925_dma_map_area 383 .long arm925_dma_map_area
384 .long arm925_dma_unmap_area 384 .long arm925_dma_unmap_area
385 .long arm925_dma_inv_range
386 .long arm925_dma_clean_range
385 .long arm925_dma_flush_range 387 .long arm925_dma_flush_range
386 388
387ENTRY(cpu_arm925_dcache_clean_area) 389ENTRY(cpu_arm925_dcache_clean_area)
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 0ed85d930c0..4a6724e3f6f 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -253,7 +253,7 @@ ENTRY(arm926_flush_kern_dcache_area)
253 * 253 *
254 * (same as v4wb) 254 * (same as v4wb)
255 */ 255 */
256arm926_dma_inv_range: 256ENTRY(arm926_dma_inv_range)
257#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 257#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
258 tst r0, #CACHE_DLINESIZE - 1 258 tst r0, #CACHE_DLINESIZE - 1
259 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 259 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
@@ -278,7 +278,7 @@ arm926_dma_inv_range:
278 * 278 *
279 * (same as v4wb) 279 * (same as v4wb)
280 */ 280 */
281arm926_dma_clean_range: 281ENTRY(arm926_dma_clean_range)
282#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 282#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
283 bic r0, r0, #CACHE_DLINESIZE - 1 283 bic r0, r0, #CACHE_DLINESIZE - 1
2841: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 2841: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
@@ -345,6 +345,8 @@ ENTRY(arm926_cache_fns)
345 .long arm926_flush_kern_dcache_area 345 .long arm926_flush_kern_dcache_area
346 .long arm926_dma_map_area 346 .long arm926_dma_map_area
347 .long arm926_dma_unmap_area 347 .long arm926_dma_unmap_area
348 .long arm926_dma_inv_range
349 .long arm926_dma_clean_range
348 .long arm926_dma_flush_range 350 .long arm926_dma_flush_range
349 351
350ENTRY(cpu_arm926_dcache_clean_area) 352ENTRY(cpu_arm926_dcache_clean_area)
diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
index 26aea3f71c2..9009b55190d 100644
--- a/arch/arm/mm/proc-arm940.S
+++ b/arch/arm/mm/proc-arm940.S
@@ -178,7 +178,7 @@ ENTRY(arm940_flush_kern_dcache_area)
178 * - start - virtual start address 178 * - start - virtual start address
179 * - end - virtual end address 179 * - end - virtual end address
180 */ 180 */
181arm940_dma_inv_range: 181ENTRY(arm940_dma_inv_range)
182 mov ip, #0 182 mov ip, #0
183 mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments 183 mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
1841: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries 1841: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
@@ -199,7 +199,7 @@ arm940_dma_inv_range:
199 * - start - virtual start address 199 * - start - virtual start address
200 * - end - virtual end address 200 * - end - virtual end address
201 */ 201 */
202arm940_dma_clean_range: 202ENTRY(arm940_dma_clean_range)
203ENTRY(cpu_arm940_dcache_clean_area) 203ENTRY(cpu_arm940_dcache_clean_area)
204 mov ip, #0 204 mov ip, #0
205#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 205#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
@@ -274,6 +274,8 @@ ENTRY(arm940_cache_fns)
274 .long arm940_flush_kern_dcache_area 274 .long arm940_flush_kern_dcache_area
275 .long arm940_dma_map_area 275 .long arm940_dma_map_area
276 .long arm940_dma_unmap_area 276 .long arm940_dma_unmap_area
277 .long arm940_dma_inv_range
278 .long arm940_dma_clean_range
277 .long arm940_dma_flush_range 279 .long arm940_dma_flush_range
278 280
279 __CPUINIT 281 __CPUINIT
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
index 8063345406f..ed2234aa88a 100644
--- a/arch/arm/mm/proc-arm946.S
+++ b/arch/arm/mm/proc-arm946.S
@@ -222,7 +222,7 @@ ENTRY(arm946_flush_kern_dcache_area)
222 * - end - virtual end address 222 * - end - virtual end address
223 * (same as arm926) 223 * (same as arm926)
224 */ 224 */
225arm946_dma_inv_range: 225ENTRY(arm946_dma_inv_range)
226#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 226#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
227 tst r0, #CACHE_DLINESIZE - 1 227 tst r0, #CACHE_DLINESIZE - 1
228 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 228 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
@@ -247,7 +247,7 @@ arm946_dma_inv_range:
247 * 247 *
248 * (same as arm926) 248 * (same as arm926)
249 */ 249 */
250arm946_dma_clean_range: 250ENTRY(arm946_dma_clean_range)
251#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 251#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
252 bic r0, r0, #CACHE_DLINESIZE - 1 252 bic r0, r0, #CACHE_DLINESIZE - 1
2531: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 2531: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
@@ -316,6 +316,8 @@ ENTRY(arm946_cache_fns)
316 .long arm946_flush_kern_dcache_area 316 .long arm946_flush_kern_dcache_area
317 .long arm946_dma_map_area 317 .long arm946_dma_map_area
318 .long arm946_dma_unmap_area 318 .long arm946_dma_unmap_area
319 .long arm946_dma_inv_range
320 .long arm946_dma_clean_range
319 .long arm946_dma_flush_range 321 .long arm946_dma_flush_range
320 322
321 323
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index d3883eed7a4..1ef5673266a 100644
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -280,7 +280,7 @@ ENTRY(feroceon_range_flush_kern_dcache_area)
280 * (same as v4wb) 280 * (same as v4wb)
281 */ 281 */
282 .align 5 282 .align 5
283feroceon_dma_inv_range: 283ENTRY(feroceon_dma_inv_range)
284 tst r0, #CACHE_DLINESIZE - 1 284 tst r0, #CACHE_DLINESIZE - 1
285 bic r0, r0, #CACHE_DLINESIZE - 1 285 bic r0, r0, #CACHE_DLINESIZE - 1
286 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 286 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
@@ -294,7 +294,7 @@ feroceon_dma_inv_range:
294 mov pc, lr 294 mov pc, lr
295 295
296 .align 5 296 .align 5
297feroceon_range_dma_inv_range: 297ENTRY(feroceon_range_dma_inv_range)
298 mrs r2, cpsr 298 mrs r2, cpsr
299 tst r0, #CACHE_DLINESIZE - 1 299 tst r0, #CACHE_DLINESIZE - 1
300 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 300 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
@@ -320,7 +320,7 @@ feroceon_range_dma_inv_range:
320 * (same as v4wb) 320 * (same as v4wb)
321 */ 321 */
322 .align 5 322 .align 5
323feroceon_dma_clean_range: 323ENTRY(feroceon_dma_clean_range)
324 bic r0, r0, #CACHE_DLINESIZE - 1 324 bic r0, r0, #CACHE_DLINESIZE - 1
3251: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 3251: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
326 add r0, r0, #CACHE_DLINESIZE 326 add r0, r0, #CACHE_DLINESIZE
@@ -330,7 +330,7 @@ feroceon_dma_clean_range:
330 mov pc, lr 330 mov pc, lr
331 331
332 .align 5 332 .align 5
333feroceon_range_dma_clean_range: 333ENTRY(feroceon_range_dma_clean_range)
334 mrs r2, cpsr 334 mrs r2, cpsr
335 cmp r1, r0 335 cmp r1, r0
336 subne r1, r1, #1 @ top address is inclusive 336 subne r1, r1, #1 @ top address is inclusive
@@ -421,6 +421,8 @@ ENTRY(feroceon_cache_fns)
421 .long feroceon_flush_kern_dcache_area 421 .long feroceon_flush_kern_dcache_area
422 .long feroceon_dma_map_area 422 .long feroceon_dma_map_area
423 .long feroceon_dma_unmap_area 423 .long feroceon_dma_unmap_area
424 .long feroceon_dma_inv_range
425 .long feroceon_dma_clean_range
424 .long feroceon_dma_flush_range 426 .long feroceon_dma_flush_range
425 427
426ENTRY(feroceon_range_cache_fns) 428ENTRY(feroceon_range_cache_fns)
@@ -433,6 +435,8 @@ ENTRY(feroceon_range_cache_fns)
433 .long feroceon_range_flush_kern_dcache_area 435 .long feroceon_range_flush_kern_dcache_area
434 .long feroceon_range_dma_map_area 436 .long feroceon_range_dma_map_area
435 .long feroceon_dma_unmap_area 437 .long feroceon_dma_unmap_area
438 .long feroceon_range_dma_inv_range
439 .long feroceon_range_dma_clean_range
436 .long feroceon_range_dma_flush_range 440 .long feroceon_range_dma_flush_range
437 441
438 .align 5 442 .align 5
diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S
index 9d4f2ae6337..7702f939a65 100644
--- a/arch/arm/mm/proc-mohawk.S
+++ b/arch/arm/mm/proc-mohawk.S
@@ -214,7 +214,7 @@ ENTRY(mohawk_flush_kern_dcache_area)
214 * 214 *
215 * (same as v4wb) 215 * (same as v4wb)
216 */ 216 */
217mohawk_dma_inv_range: 217ENTRY(mohawk_dma_inv_range)
218 tst r0, #CACHE_DLINESIZE - 1 218 tst r0, #CACHE_DLINESIZE - 1
219 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 219 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
220 tst r1, #CACHE_DLINESIZE - 1 220 tst r1, #CACHE_DLINESIZE - 1
@@ -237,7 +237,7 @@ mohawk_dma_inv_range:
237 * 237 *
238 * (same as v4wb) 238 * (same as v4wb)
239 */ 239 */
240mohawk_dma_clean_range: 240ENTRY(mohawk_dma_clean_range)
241 bic r0, r0, #CACHE_DLINESIZE - 1 241 bic r0, r0, #CACHE_DLINESIZE - 1
2421: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 2421: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
243 add r0, r0, #CACHE_DLINESIZE 243 add r0, r0, #CACHE_DLINESIZE
@@ -297,6 +297,8 @@ ENTRY(mohawk_cache_fns)
297 .long mohawk_flush_kern_dcache_area 297 .long mohawk_flush_kern_dcache_area
298 .long mohawk_dma_map_area 298 .long mohawk_dma_map_area
299 .long mohawk_dma_unmap_area 299 .long mohawk_dma_unmap_area
300 .long mohawk_dma_inv_range
301 .long mohawk_dma_clean_range
300 .long mohawk_dma_flush_range 302 .long mohawk_dma_flush_range
301 303
302ENTRY(cpu_mohawk_dcache_clean_area) 304ENTRY(cpu_mohawk_dcache_clean_area)
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 596213699f3..5c2dc7d68e4 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -264,7 +264,7 @@ ENTRY(xsc3_flush_kern_dcache_area)
264 * - start - virtual start address 264 * - start - virtual start address
265 * - end - virtual end address 265 * - end - virtual end address
266 */ 266 */
267xsc3_dma_inv_range: 267ENTRY(xsc3_dma_inv_range)
268 tst r0, #CACHELINESIZE - 1 268 tst r0, #CACHELINESIZE - 1
269 bic r0, r0, #CACHELINESIZE - 1 269 bic r0, r0, #CACHELINESIZE - 1
270 mcrne p15, 0, r0, c7, c10, 1 @ clean L1 D line 270 mcrne p15, 0, r0, c7, c10, 1 @ clean L1 D line
@@ -285,7 +285,7 @@ xsc3_dma_inv_range:
285 * - start - virtual start address 285 * - start - virtual start address
286 * - end - virtual end address 286 * - end - virtual end address
287 */ 287 */
288xsc3_dma_clean_range: 288ENTRY(xsc3_dma_clean_range)
289 bic r0, r0, #CACHELINESIZE - 1 289 bic r0, r0, #CACHELINESIZE - 1
2901: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line 2901: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
291 add r0, r0, #CACHELINESIZE 291 add r0, r0, #CACHELINESIZE
@@ -345,6 +345,8 @@ ENTRY(xsc3_cache_fns)
345 .long xsc3_flush_kern_dcache_area 345 .long xsc3_flush_kern_dcache_area
346 .long xsc3_dma_map_area 346 .long xsc3_dma_map_area
347 .long xsc3_dma_unmap_area 347 .long xsc3_dma_unmap_area
348 .long xsc3_dma_inv_range
349 .long xsc3_dma_clean_range
348 .long xsc3_dma_flush_range 350 .long xsc3_dma_flush_range
349 351
350ENTRY(cpu_xsc3_dcache_clean_area) 352ENTRY(cpu_xsc3_dcache_clean_area)
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 42af97664c9..6e804fb65b2 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -322,7 +322,7 @@ ENTRY(xscale_flush_kern_dcache_area)
322 * - start - virtual start address 322 * - start - virtual start address
323 * - end - virtual end address 323 * - end - virtual end address
324 */ 324 */
325xscale_dma_inv_range: 325ENTRY(xscale_dma_inv_range)
326 tst r0, #CACHELINESIZE - 1 326 tst r0, #CACHELINESIZE - 1
327 bic r0, r0, #CACHELINESIZE - 1 327 bic r0, r0, #CACHELINESIZE - 1
328 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 328 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
@@ -343,7 +343,7 @@ xscale_dma_inv_range:
343 * - start - virtual start address 343 * - start - virtual start address
344 * - end - virtual end address 344 * - end - virtual end address
345 */ 345 */
346xscale_dma_clean_range: 346ENTRY(xscale_dma_clean_range)
347 bic r0, r0, #CACHELINESIZE - 1 347 bic r0, r0, #CACHELINESIZE - 1
3481: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 3481: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
349 add r0, r0, #CACHELINESIZE 349 add r0, r0, #CACHELINESIZE
@@ -417,6 +417,8 @@ ENTRY(xscale_cache_fns)
417 .long xscale_flush_kern_dcache_area 417 .long xscale_flush_kern_dcache_area
418 .long xscale_dma_map_area 418 .long xscale_dma_map_area
419 .long xscale_dma_unmap_area 419 .long xscale_dma_unmap_area
420 .long xscale_dma_inv_range
421 .long xscale_dma_clean_range
420 .long xscale_dma_flush_range 422 .long xscale_dma_flush_range
421 423
422/* 424/*
@@ -442,6 +444,8 @@ ENTRY(xscale_80200_A0_A1_cache_fns)
442 .long xscale_dma_a0_map_area 444 .long xscale_dma_a0_map_area
443 .long xscale_dma_unmap_area 445 .long xscale_dma_unmap_area
444 .long xscale_dma_flush_range 446 .long xscale_dma_flush_range
447 .long xscale_dma_clean_range
448 .long xscale_dma_flush_range
445 449
446ENTRY(cpu_xscale_dcache_clean_area) 450ENTRY(cpu_xscale_dcache_clean_area)
4471: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 4511: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-31 19:39:59 -0400