Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm

* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (28 commits)
  ARM: OMAP: Fix GCC-reported compile time bug
  ARM: OMAP: restore CONFIG_GENERIC_TIME
  ARM: OMAP: partial LED fixes
  ARM: OMAP: add SoSSI clock (call propagate_rate for childrens)
  ARM: OMAP: FB sync with N800 tree (support for dynamic SRAM allocations)
  ARM: OMAP: Sync framebuffer headers with N800 tree
  ARM: OMAP: Mostly cosmetic to sync up with linux-omap tree
  ARM: OMAP: Fix gpmc header
  ARM: OMAP: Add mailbox support for IVA
  [ARM] armv7: add Makefile and Kconfig entries
  [ARM] armv7: add support for asid-tagged VIVT I-cache
  [ARM] armv7: add dedicated ARMv7 barrier instructions
  [ARM] armv7: Add ARMv7 cacheid macros
  [ARM] armv7: add support for ARMv7 cores.
  [ARM] Fix ARM branch relocation range
  [ARM] 4363/1: AT91: Remove legacy PIO definitions
  [ARM] 4361/1: AT91: Build error
  ARM: OMAP: Sync core code with linux-omap
  ARM: OMAP: Sync headers with linux-omap
  ARM: OMAP: h4 must have blinky leds!!
  ...

1 files changed, 14 insertions, 3 deletions

diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index 9da43a0fdcd..fc84fcc7438 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -14,7 +14,8 @@
 #include <asm/mmu_context.h>
 #include <asm/tlbflush.h>
 
-unsigned int cpu_last_asid = { 1 << ASID_BITS };
+static DEFINE_SPINLOCK(cpu_asid_lock);
+unsigned int cpu_last_asid = ASID_FIRST_VERSION;
 
 /*
  * We fork()ed a process, and we need a new context for the child
@@ -31,15 +32,16 @@ void __new_context(struct mm_struct *mm)
 {
         unsigned int asid;
 
+        spin_lock(&cpu_asid_lock);
         asid = ++cpu_last_asid;
         if (asid == 0)
-                asid = cpu_last_asid = 1 << ASID_BITS;
+                asid = cpu_last_asid = ASID_FIRST_VERSION;
 
         /*
          * If we've used up all our ASIDs, we need
          * to start a new version and flush the TLB.
          */
-        if ((asid & ~ASID_MASK) == 0) {
+        if (unlikely((asid & ~ASID_MASK) == 0)) {
                 asid = ++cpu_last_asid;
                 /* set the reserved ASID before flushing the TLB */
                 asm("mcr        p15, 0, %0, c13, c0, 1  @ set reserved context ID\n"
@@ -47,7 +49,16 @@ void __new_context(struct mm_struct *mm)
                     : "r" (0));
                 isb();
                 flush_tlb_all();
+                if (icache_is_vivt_asid_tagged()) {
+                        asm("mcr        p15, 0, %0, c7, c5, 0   @ invalidate I-cache\n"
+                            "mcr        p15, 0, %0, c7, c5, 6   @ flush BTAC/BTB\n"
+                            :
+                            : "r" (0));
+                        dsb();
+                }
         }
+        spin_unlock(&cpu_asid_lock);
 
+        mm->cpu_vm_mask = cpumask_of_cpu(smp_processor_id());
         mm->context.id = asid;
 }