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authorJens Axboe <jens.axboe@oracle.com>2010-02-22 07:48:51 -0500
committerJens Axboe <jens.axboe@oracle.com>2010-02-22 07:48:51 -0500
commitf11cbd74c5ff3614f6390b4de67a6ffdc614c378 (patch)
tree6a30920ade9eeaac5bf6d6263b5d09712e882eb0 /arch/arm/mm/cache-xsc3l2.c
parent429c42c9d246f5bda868495c09974312a0177328 (diff)
parentaea187c46f7d03ce985e55eb1398d0776a15b928 (diff)
Merge branch 'master' into for-2.6.34
Diffstat (limited to 'arch/arm/mm/cache-xsc3l2.c')
-rw-r--r--arch/arm/mm/cache-xsc3l2.c11
1 files changed, 5 insertions, 6 deletions
diff --git a/arch/arm/mm/cache-xsc3l2.c b/arch/arm/mm/cache-xsc3l2.c
index 5d180cb0bd9..c3154928bcc 100644
--- a/arch/arm/mm/cache-xsc3l2.c
+++ b/arch/arm/mm/cache-xsc3l2.c
@@ -221,15 +221,14 @@ static int __init xsc3_l2_init(void)
221 if (!cpu_is_xsc3() || !xsc3_l2_present()) 221 if (!cpu_is_xsc3() || !xsc3_l2_present())
222 return 0; 222 return 0;
223 223
224 if (!(get_cr() & CR_L2)) { 224 if (get_cr() & CR_L2) {
225 pr_info("XScale3 L2 cache enabled.\n"); 225 pr_info("XScale3 L2 cache enabled.\n");
226 adjust_cr(CR_L2, CR_L2);
227 xsc3_l2_inv_all(); 226 xsc3_l2_inv_all();
228 }
229 227
230 outer_cache.inv_range = xsc3_l2_inv_range; 228 outer_cache.inv_range = xsc3_l2_inv_range;
231 outer_cache.clean_range = xsc3_l2_clean_range; 229 outer_cache.clean_range = xsc3_l2_clean_range;
232 outer_cache.flush_range = xsc3_l2_flush_range; 230 outer_cache.flush_range = xsc3_l2_flush_range;
231 }
233 232
234 return 0; 233 return 0;
235} 234}