Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm

* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (422 commits)
  [ARM] 5435/1: fix compile warning in sanity_check_meminfo()
  [ARM] 5434/1: ARM: OMAP: Fix mailbox compile for 24xx
  [ARM] pxa: fix the bad assumption that PCMCIA sockets always start with 0
  [ARM] pxa: fix Colibri PXA300 and PXA320 LCD backlight pins
  imxfb: Fix TFT mode
  i.MX21/27: remove ifdef CONFIG_FB_IMX
  imxfb: add clock support
  mxc: add arch_reset() function
  clkdev: add possibility to get a clock based on the device name
  i.MX1: remove fb support from mach-imx
  [ARM] pxa: build arch/arm/plat-pxa/mfp.c only when PXA3xx or ARCH_MMP defined
  Gemini: Add support for Teltonika RUT100
  Gemini: gpiolib based GPIO support v2
  MAINTAINERS: add myself as Gemini architecture maintainer
  ARM: Add Gemini architecture v3
  [ARM] OMAP: Fix compile for omap2_init_common_hw()
  MAINTAINERS: Add myself as Faraday ARM core variant maintainer
  ARM: Add support for FA526 v2
  [ARM] acorn,ebsa110,footbridge,integrator,sa1100: Convert asm/io.h to linux/io.h
  [ARM] collie: fix two minor formatting nits
  ...

3 files changed, 64 insertions, 0 deletions

diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 77d614232d8..b371fba1b95 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -27,6 +27,12 @@
                 .macro  writeb, ch, rb
                 mcr     p14, 0, \ch, c0, c5, 0
                 .endm
+#elif defined(CONFIG_CPU_XSCALE)
+                .macro  loadsp, rb
+                .endm
+                .macro  writeb, ch, rb
+                mcr     p14, 0, \ch, c8, c0, 0
+                .endm
 #else
                 .macro  loadsp, rb
                 .endm
@@ -459,6 +465,20 @@ __armv7_mmu_cache_on:
                 mcr     p15, 0, r0, c7, c5, 4   @ ISB
                 mov     pc, r12
 
+__fa526_cache_on:
+                mov     r12, lr
+                bl      __setup_mmu
+                mov     r0, #0
+                mcr     p15, 0, r0, c7, c7, 0   @ Invalidate whole cache
+                mcr     p15, 0, r0, c7, c10, 4  @ drain write buffer
+                mcr     p15, 0, r0, c8, c7, 0   @ flush UTLB
+                mrc     p15, 0, r0, c1, c0, 0   @ read control reg
+                orr     r0, r0, #0x1000         @ I-cache enable
+                bl      __common_mmu_cache_on
+                mov     r0, #0
+                mcr     p15, 0, r0, c8, c7, 0   @ flush UTLB
+                mov     pc, r12
+
 __arm6_mmu_cache_on:
                 mov     r12, lr
                 bl      __setup_mmu
@@ -630,12 +650,30 @@ proc_types:
                 b       __armv4_mmu_cache_off
                 b       __armv4_mmu_cache_flush
 
+                .word   0x56158000              @ PXA168
+                .word   0xfffff000
+                b __armv4_mmu_cache_on
+                b __armv4_mmu_cache_off
+                b __armv5tej_mmu_cache_flush
+
+                .word   0x56056930
+                .word   0xff0ffff0              @ PXA935
+                b       __armv4_mmu_cache_on
+                b       __armv4_mmu_cache_off
+                b       __armv4_mmu_cache_flush
+
                 .word   0x56050000              @ Feroceon
                 .word   0xff0f0000
                 b       __armv4_mmu_cache_on
                 b       __armv4_mmu_cache_off
                 b       __armv5tej_mmu_cache_flush
 
+                .word   0x66015261              @ FA526
+                .word   0xff01fff1
+                b       __fa526_cache_on
+                b       __armv4_mmu_cache_off
+                b       __fa526_cache_flush
+
                 @ These match on the architecture ID
 
                 .word   0x00020000              @ ARMv4T
@@ -775,6 +813,12 @@ __armv4_mpu_cache_flush:
                 mcr     p15, 0, ip, c7, c10, 4  @ drain WB
                 mov     pc, lr
                 
+__fa526_cache_flush:
+                mov     r1, #0
+                mcr     p15, 0, r1, c7, c14, 0  @ clean and invalidate D cache
+                mcr     p15, 0, r1, c7, c5, 0   @ flush I cache
+                mcr     p15, 0, r1, c7, c10, 4  @ drain WB
+                mov     pc, lr
 
 __armv6_mmu_cache_flush:
                 mov     r1, #0
diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
index 3fc08413fff..393c8164131 100644
--- a/arch/arm/boot/compressed/misc.c
+++ b/arch/arm/boot/compressed/misc.c
@@ -46,6 +46,21 @@ static void icedcc_putc(int ch)
 
         asm("mcr p14, 0, %0, c0, c5, 0" : : "r" (ch));
 }
+#elif defined(CONFIG_CPU_XSCALE)
+
+static void icedcc_putc(int ch)
+{
+        int status, i = 0x4000000;
+
+        do {
+                if (--i < 0)
+                        return;
+
+                asm volatile ("mrc p14, 0, %0, c14, c0, 0" : "=r" (status));
+        } while (status & (1 << 28));
+
+        asm("mcr p14, 0, %0, c8, c0, 0" : : "r" (ch));
+}
 
 #else
 
diff --git a/arch/arm/boot/compressed/vmlinux.lds.in b/arch/arm/boot/compressed/vmlinux.lds.in
index 153a07e7222..a5924b9b88b 100644
--- a/arch/arm/boot/compressed/vmlinux.lds.in
+++ b/arch/arm/boot/compressed/vmlinux.lds.in
@@ -11,6 +11,11 @@ OUTPUT_ARCH(arm)
 ENTRY(_start)
 SECTIONS
 {
+  /DISCARD/ : {
+    *(.ARM.exidx*)
+    *(.ARM.extab*)
+  }
+
   . = TEXT_START;
   _text = .;