drm/radeon/kms: add bo blit support for NI

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

1 files changed, 67 insertions, 2 deletions

diff --git a/drivers/gpu/drm/radeon/evergreen_blit_kms.c b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
index 2ccd1f0545f..b758dc7f2f2 100644
--- a/drivers/gpu/drm/radeon/evergreen_blit_kms.c
+++ b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
@@ -148,7 +148,8 @@ set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
         radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30);
 
         if ((rdev->family == CHIP_CEDAR) ||
-            (rdev->family == CHIP_PALM))
+            (rdev->family == CHIP_PALM) ||
+            (rdev->family == CHIP_CAICOS))
                 cp_set_surface_sync(rdev,
                                     PACKET3_TC_ACTION_ENA, 48, gpu_addr);
         else
@@ -353,10 +354,74 @@ set_default_state(struct radeon_device *rdev)
                 num_hs_stack_entries = 42;
                 num_ls_stack_entries = 42;
                 break;
+        case CHIP_BARTS:
+                num_ps_gprs = 93;
+                num_vs_gprs = 46;
+                num_temp_gprs = 4;
+                num_gs_gprs = 31;
+                num_es_gprs = 31;
+                num_hs_gprs = 23;
+                num_ls_gprs = 23;
+                num_ps_threads = 128;
+                num_vs_threads = 20;
+                num_gs_threads = 20;
+                num_es_threads = 20;
+                num_hs_threads = 20;
+                num_ls_threads = 20;
+                num_ps_stack_entries = 85;
+                num_vs_stack_entries = 85;
+                num_gs_stack_entries = 85;
+                num_es_stack_entries = 85;
+                num_hs_stack_entries = 85;
+                num_ls_stack_entries = 85;
+                break;
+        case CHIP_TURKS:
+                num_ps_gprs = 93;
+                num_vs_gprs = 46;
+                num_temp_gprs = 4;
+                num_gs_gprs = 31;
+                num_es_gprs = 31;
+                num_hs_gprs = 23;
+                num_ls_gprs = 23;
+                num_ps_threads = 128;
+                num_vs_threads = 20;
+                num_gs_threads = 20;
+                num_es_threads = 20;
+                num_hs_threads = 20;
+                num_ls_threads = 20;
+                num_ps_stack_entries = 42;
+                num_vs_stack_entries = 42;
+                num_gs_stack_entries = 42;
+                num_es_stack_entries = 42;
+                num_hs_stack_entries = 42;
+                num_ls_stack_entries = 42;
+                break;
+        case CHIP_CAICOS:
+                num_ps_gprs = 93;
+                num_vs_gprs = 46;
+                num_temp_gprs = 4;
+                num_gs_gprs = 31;
+                num_es_gprs = 31;
+                num_hs_gprs = 23;
+                num_ls_gprs = 23;
+                num_ps_threads = 128;
+                num_vs_threads = 10;
+                num_gs_threads = 10;
+                num_es_threads = 10;
+                num_hs_threads = 10;
+                num_ls_threads = 10;
+                num_ps_stack_entries = 42;
+                num_vs_stack_entries = 42;
+                num_gs_stack_entries = 42;
+                num_es_stack_entries = 42;
+                num_hs_stack_entries = 42;
+                num_ls_stack_entries = 42;
+                break;
         }
 
         if ((rdev->family == CHIP_CEDAR) ||
-            (rdev->family == CHIP_PALM))
+            (rdev->family == CHIP_PALM) ||
+            (rdev->family == CHIP_CAICOS))
                 sq_config = 0;
         else
                 sq_config = VC_ENABLE;