diff options
author | Liam Girdwood <lrg@ti.com> | 2011-07-24 15:59:39 -0400 |
---|---|---|
committer | Paolo Pisati <paolo.pisati@canonical.com> | 2012-08-17 04:18:23 -0400 |
commit | fad1d53913cb6eefebba505a2f76143b493a8639 (patch) | |
tree | 179f3e87ede284ff112c6bc029667e2c45326e32 | |
parent | d06190da37c76a1bb7f85c5c17d4705b3a395ffd (diff) |
Subject: [PATCH 060/104] OMAP4: DMIC - Add OMAP4 digital Mic controller.
Add register bit and offset definitions for OMAP4 DMICs.
Signed-off-by: Liam Girdwood <lrg@ti.com>
-rw-r--r-- | arch/arm/plat-omap/include/plat/dmic.h | 79 |
1 files changed, 79 insertions, 0 deletions
diff --git a/arch/arm/plat-omap/include/plat/dmic.h b/arch/arm/plat-omap/include/plat/dmic.h new file mode 100644 index 00000000000..1b0e49e7786 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/dmic.h | |||
@@ -0,0 +1,79 @@ | |||
1 | /* | ||
2 | * dmic.h -- OMAP Digital Microphone Controller | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License version 2 as | ||
6 | * published by the Free Software Foundation. | ||
7 | */ | ||
8 | |||
9 | #ifndef __ASM_ARCH_OMAP_DMIC_H | ||
10 | #define __ASM_ARCH_OMAP_DMIC_H | ||
11 | |||
12 | #define OMAP44XX_DMIC_L3_BASE 0x4902e000 | ||
13 | |||
14 | #define OMAP_DMIC_REVISION 0x00 | ||
15 | #define OMAP_DMIC_SYSCONFIG 0x10 | ||
16 | #define OMAP_DMIC_IRQSTATUS_RAW 0x24 | ||
17 | #define OMAP_DMIC_IRQSTATUS 0x28 | ||
18 | #define OMAP_DMIC_IRQENABLE_SET 0x2C | ||
19 | #define OMAP_DMIC_IRQENABLE_CLR 0x30 | ||
20 | #define OMAP_DMIC_IRQWAKE_EN 0x34 | ||
21 | #define OMAP_DMIC_DMAENABLE_SET 0x38 | ||
22 | #define OMAP_DMIC_DMAENABLE_CLR 0x3C | ||
23 | #define OMAP_DMIC_DMAWAKEEN 0x40 | ||
24 | #define OMAP_DMIC_CTRL 0x44 | ||
25 | #define OMAP_DMIC_DATA 0x48 | ||
26 | #define OMAP_DMIC_FIFO_CTRL 0x4C | ||
27 | #define OMAP_DMIC_FIFO_DMIC1R_DATA 0x50 | ||
28 | #define OMAP_DMIC_FIFO_DMIC1L_DATA 0x54 | ||
29 | #define OMAP_DMIC_FIFO_DMIC2R_DATA 0x58 | ||
30 | #define OMAP_DMIC_FIFO_DMIC2L_DATA 0x5C | ||
31 | #define OMAP_DMIC_FIFO_DMIC3R_DATA 0x60 | ||
32 | #define OMAP_DMIC_FIFO_DMIC3L_DATA 0x64 | ||
33 | |||
34 | /* | ||
35 | * DMIC_IRQ bit fields | ||
36 | * IRQSTATUS_RAW, IRQSTATUS, IRQENABLE_SET, IRQENABLE_CLR | ||
37 | */ | ||
38 | |||
39 | #define OMAP_DMIC_IRQ (1 << 0) | ||
40 | #define OMAP_DMIC_IRQ_FULL (1 << 1) | ||
41 | #define OMAP_DMIC_IRQ_ALMST_EMPTY (1 << 2) | ||
42 | #define OMAP_DMIC_IRQ_EMPTY (1 << 3) | ||
43 | #define OMAP_DMIC_IRQ_MASK 0x07 | ||
44 | |||
45 | /* | ||
46 | * DMIC_DMAENABLE bit fields | ||
47 | */ | ||
48 | |||
49 | #define OMAP_DMIC_DMA_ENABLE 0x1 | ||
50 | |||
51 | /* | ||
52 | * DMIC_CTRL bit fields | ||
53 | */ | ||
54 | |||
55 | #define OMAP_DMIC_UP1_ENABLE 0x0001 | ||
56 | #define OMAP_DMIC_UP2_ENABLE 0x0002 | ||
57 | #define OMAP_DMIC_UP3_ENABLE 0x0004 | ||
58 | #define OMAP_DMIC_UP_ENABLE_MASK 0x0007 | ||
59 | #define OMAP_DMIC_FORMAT 0x0008 | ||
60 | #define OMAP_DMIC_POLAR1 0x0010 | ||
61 | #define OMAP_DMIC_POLAR2 0x0020 | ||
62 | #define OMAP_DMIC_POLAR3 0x0040 | ||
63 | #define OMAP_DMIC_POLAR_MASK 0x0070 | ||
64 | #define OMAP_DMIC_CLK_DIV_SHIFT 7 | ||
65 | #define OMAP_DMIC_CLK_DIV_MASK 0x0380 | ||
66 | #define OMAP_DMIC_RESET 0x0400 | ||
67 | |||
68 | #define OMAP_DMIC_ENABLE_MASK 0x007 | ||
69 | |||
70 | #define OMAP_DMICOUTFORMAT_LJUST (0 << 3) | ||
71 | #define OMAP_DMICOUTFORMAT_RJUST (1 << 3) | ||
72 | |||
73 | /* | ||
74 | * DMIC_FIFO_CTRL bit fields | ||
75 | */ | ||
76 | |||
77 | #define OMAP_DMIC_THRES_MAX 0xF | ||
78 | |||
79 | #endif | ||