diff options
author | Subramaniam C.A <subramaniam.ca@ti.com> | 2011-02-14 19:59:32 -0500 |
---|---|---|
committer | Paolo Pisati <paolo.pisati@canonical.com> | 2012-08-17 04:19:16 -0400 |
commit | cd6629d28e31f626f305091c33a6add4c161111c (patch) | |
tree | 738e8da136b49e05f541ab619e29c4ae917fb292 | |
parent | a5f51bee0e31ddc2cdfe2cf3c62b2f22e910c703 (diff) |
SYSLINK: ipu-pm ported changes specific for 2.6.38 vanilla l-o kernel.
This patch adds vanilla l-o 2.6.38 specific changes. The patch might get
redundant once the OMAP_PM specific changes/ baseport changes go in.
Check the return value of kfifo_out ti avoid a warning
Do not use any constraint req/rel since the fwk is not
ready yet.
Signed-off-by: Miguel Vadillo <vadillo@ti.com>
Signed-off-by: Subramaniam C.A <subramaniam.ca@ti.com>
Signed-off-by: Cris Jansson <cjansson@ti.com>
-rw-r--r-- | arch/arm/mach-omap2/ipu_dev.c | 6 | ||||
-rw-r--r-- | drivers/dsp/syslink/Kconfig | 2 | ||||
-rw-r--r-- | drivers/dsp/syslink/ipu_pm/ipu_pm.c | 45 |
3 files changed, 29 insertions, 24 deletions
diff --git a/arch/arm/mach-omap2/ipu_dev.c b/arch/arm/mach-omap2/ipu_dev.c index a24ca10d367..8ffbfc40907 100644 --- a/arch/arm/mach-omap2/ipu_dev.c +++ b/arch/arm/mach-omap2/ipu_dev.c | |||
@@ -17,6 +17,7 @@ | |||
17 | 17 | ||
18 | #include <mach/irqs.h> | 18 | #include <mach/irqs.h> |
19 | #include <plat/omap_hwmod.h> | 19 | #include <plat/omap_hwmod.h> |
20 | #include <plat/common.h> | ||
20 | #include <plat/omap_device.h> | 21 | #include <plat/omap_device.h> |
21 | #include <plat/omap-pm.h> | 22 | #include <plat/omap-pm.h> |
22 | #include <linux/platform_device.h> | 23 | #include <linux/platform_device.h> |
@@ -89,7 +90,7 @@ inline int ipu_pm_module_set_rate(unsigned rsrc, | |||
89 | unsigned target_rsrc, | 90 | unsigned target_rsrc, |
90 | unsigned rate) | 91 | unsigned rate) |
91 | { | 92 | { |
92 | int ret; | 93 | int ret = 0; |
93 | unsigned target; | 94 | unsigned target; |
94 | struct device *dp; | 95 | struct device *dp; |
95 | struct omap_ipupm_mod_platform_data *pd; | 96 | struct omap_ipupm_mod_platform_data *pd; |
@@ -114,8 +115,9 @@ inline int ipu_pm_module_set_rate(unsigned rsrc, | |||
114 | } else | 115 | } else |
115 | dp = pd[target].dev; | 116 | dp = pd[target].dev; |
116 | } | 117 | } |
117 | 118 | #ifdef CONFIG_OMAP_PM | |
118 | ret = omap_device_set_rate(pd[rsrc].dev, dp, rate); | 119 | ret = omap_device_set_rate(pd[rsrc].dev, dp, rate); |
120 | #endif | ||
119 | if (ret) | 121 | if (ret) |
120 | pr_err("device set rate failed %s", pd[target_rsrc].oh_name); | 122 | pr_err("device set rate failed %s", pd[target_rsrc].oh_name); |
121 | err_ret: | 123 | err_ret: |
diff --git a/drivers/dsp/syslink/Kconfig b/drivers/dsp/syslink/Kconfig index 8296d7361b3..c744be6ddc8 100644 --- a/drivers/dsp/syslink/Kconfig +++ b/drivers/dsp/syslink/Kconfig | |||
@@ -38,7 +38,7 @@ config SYSLINK_DUCATI_PM | |||
38 | config SYSLINK_IPU_SELF_HIBERNATION | 38 | config SYSLINK_IPU_SELF_HIBERNATION |
39 | bool "Enable IPU Self hibernation" | 39 | bool "Enable IPU Self hibernation" |
40 | depends on SYSLINK_DUCATI_PM | 40 | depends on SYSLINK_DUCATI_PM |
41 | default y | 41 | default n |
42 | help | 42 | help |
43 | IPU will hibernate by it self after a configurable time, this | 43 | IPU will hibernate by it self after a configurable time, this |
44 | controls the self hibernation, IPU will hibernate when a system | 44 | controls the self hibernation, IPU will hibernate when a system |
diff --git a/drivers/dsp/syslink/ipu_pm/ipu_pm.c b/drivers/dsp/syslink/ipu_pm/ipu_pm.c index b19522a2c43..ff6ad2041c2 100644 --- a/drivers/dsp/syslink/ipu_pm/ipu_pm.c +++ b/drivers/dsp/syslink/ipu_pm/ipu_pm.c | |||
@@ -355,8 +355,8 @@ static char *aux_clk_name[NUM_AUX_CLK] = { | |||
355 | 355 | ||
356 | static char *aux_clk_source_name[] = { | 356 | static char *aux_clk_source_name[] = { |
357 | "sys_clkin_ck", | 357 | "sys_clkin_ck", |
358 | "dpll_core_m3_ck", | 358 | "dpll_core_m3x2_ck", |
359 | "dpll_per_m3_ck", | 359 | "dpll_per_m3x2_ck", |
360 | NULL | 360 | NULL |
361 | } ; | 361 | } ; |
362 | 362 | ||
@@ -627,9 +627,12 @@ static void ipu_pm_work(struct work_struct *work) | |||
627 | /* set retval for each iteration asumming error */ | 627 | /* set retval for each iteration asumming error */ |
628 | retval = PM_UNSUPPORTED; | 628 | retval = PM_UNSUPPORTED; |
629 | spin_lock_irq(&handle->lock); | 629 | spin_lock_irq(&handle->lock); |
630 | kfifo_out(&handle->fifo, &im, sizeof(im)); | 630 | retval = kfifo_out(&handle->fifo, &im, sizeof(im)); |
631 | spin_unlock_irq(&handle->lock); | 631 | spin_unlock_irq(&handle->lock); |
632 | 632 | ||
633 | if (retval == 0) | ||
634 | break; | ||
635 | |||
633 | /* Get the payload */ | 636 | /* Get the payload */ |
634 | pm_msg.whole = im.pm_msg; | 637 | pm_msg.whole = im.pm_msg; |
635 | /* Get the rcb_num */ | 638 | /* Get the rcb_num */ |
@@ -1425,9 +1428,9 @@ static inline int ipu_pm_get_iss(struct ipu_pm_object *handle, | |||
1425 | * independent control this also duplicates the | 1428 | * independent control this also duplicates the |
1426 | * above call to avoid read modify write locking. | 1429 | * above call to avoid read modify write locking. |
1427 | */ | 1430 | */ |
1428 | cm_write_mod_reg((OPTFCLKEN | CAM_ENABLED), | 1431 | /*cm_write_mod_reg((OPTFCLKEN | CAM_ENABLED), |
1429 | OMAP4430_CM2_CAM_MOD, | 1432 | OMAP4430_CM2_CAM_MOD, |
1430 | OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET); | 1433 | OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET);*/ |
1431 | 1434 | ||
1432 | #ifdef CONFIG_OMAP_PM | 1435 | #ifdef CONFIG_OMAP_PM |
1433 | pr_debug("Request MPU wakeup latency\n"); | 1436 | pr_debug("Request MPU wakeup latency\n"); |
@@ -1728,11 +1731,11 @@ static inline int ipu_pm_rel_fdif(struct ipu_pm_object *handle, | |||
1728 | 1731 | ||
1729 | #ifdef SR_WA | 1732 | #ifdef SR_WA |
1730 | /* Make sure the clock domain is in idle if not softreset */ | 1733 | /* Make sure the clock domain is in idle if not softreset */ |
1731 | if ((cm_read_mod_reg(OMAP4430_CM2_CAM_MOD, | 1734 | /*if ((cm_read_mod_reg(OMAP4430_CM2_CAM_MOD, |
1732 | OMAP4_CM_CAM_CLKSTCTRL_OFFSET)) & 0x400) { | 1735 | OMAP4_CM_CAM_CLKSTCTRL_OFFSET)) & 0x400) { |
1733 | __raw_writel(__raw_readl(fdifHandle + 0x10) | 0x1, | 1736 | __raw_writel(__raw_readl(fdifHandle + 0x10) | 0x1, |
1734 | fdifHandle + 0x10); | 1737 | fdifHandle + 0x10); |
1735 | } | 1738 | }*/ |
1736 | #endif | 1739 | #endif |
1737 | 1740 | ||
1738 | params->pm_fdif_counter--; | 1741 | params->pm_fdif_counter--; |
@@ -1922,11 +1925,11 @@ static inline int ipu_pm_rel_iss(struct ipu_pm_object *handle, | |||
1922 | 1925 | ||
1923 | #ifdef SR_WA | 1926 | #ifdef SR_WA |
1924 | /* Make sure the clock domain is in idle if not softreset */ | 1927 | /* Make sure the clock domain is in idle if not softreset */ |
1925 | if ((cm_read_mod_reg(OMAP4430_CM2_CAM_MOD, | 1928 | /*if ((cm_read_mod_reg(OMAP4430_CM2_CAM_MOD, |
1926 | OMAP4_CM_CAM_CLKSTCTRL_OFFSET)) & 0x100) { | 1929 | OMAP4_CM_CAM_CLKSTCTRL_OFFSET)) & 0x100) { |
1927 | __raw_writel(__raw_readl(issHandle + 0x10) | 0x1, | 1930 | __raw_writel(__raw_readl(issHandle + 0x10) | 0x1, |
1928 | issHandle + 0x10); | 1931 | issHandle + 0x10); |
1929 | } | 1932 | }*/ |
1930 | #endif | 1933 | #endif |
1931 | 1934 | ||
1932 | /* FIXME: | 1935 | /* FIXME: |
@@ -1935,9 +1938,9 @@ static inline int ipu_pm_rel_iss(struct ipu_pm_object *handle, | |||
1935 | * independent control this also duplicates the | 1938 | * independent control this also duplicates the |
1936 | * above call to avoid read modify write locking | 1939 | * above call to avoid read modify write locking |
1937 | */ | 1940 | */ |
1938 | cm_write_mod_reg(CAM_DISABLED, | 1941 | /*cm_write_mod_reg(CAM_DISABLED, |
1939 | OMAP4430_CM2_CAM_MOD, | 1942 | OMAP4430_CM2_CAM_MOD, |
1940 | OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET); | 1943 | OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET);*/ |
1941 | params->pm_iss_counter--; | 1944 | params->pm_iss_counter--; |
1942 | pr_debug("Release ISS\n"); | 1945 | pr_debug("Release ISS\n"); |
1943 | 1946 | ||
@@ -2481,18 +2484,18 @@ int ipu_pm_save_ctx(int proc_id) | |||
2481 | if (app_loaded) { | 2484 | if (app_loaded) { |
2482 | pr_info("Sleep APPM3\n"); | 2485 | pr_info("Sleep APPM3\n"); |
2483 | retval = rproc_sleep(app_rproc); | 2486 | retval = rproc_sleep(app_rproc); |
2484 | cm_write_mod_reg(HW_AUTO, | 2487 | /*cm_write_mod_reg(HW_AUTO, |
2485 | OMAP4430_CM2_CORE_MOD, | 2488 | OMAP4430_CM2_CORE_MOD, |
2486 | OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET); | 2489 | OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET);*/ |
2487 | if (retval) | 2490 | if (retval) |
2488 | goto error; | 2491 | goto error; |
2489 | handle->rcb_table->state_flag |= APP_PROC_DOWN; | 2492 | handle->rcb_table->state_flag |= APP_PROC_DOWN; |
2490 | } | 2493 | } |
2491 | pr_info("Sleep SYSM3\n"); | 2494 | pr_info("Sleep SYSM3\n"); |
2492 | retval = rproc_sleep(sys_rproc); | 2495 | retval = rproc_sleep(sys_rproc); |
2493 | cm_write_mod_reg(HW_AUTO, | 2496 | /*cm_write_mod_reg(HW_AUTO, |
2494 | OMAP4430_CM2_CORE_MOD, | 2497 | OMAP4430_CM2_CORE_MOD, |
2495 | OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET); | 2498 | OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET);*/ |
2496 | if (retval) | 2499 | if (retval) |
2497 | goto error; | 2500 | goto error; |
2498 | handle->rcb_table->state_flag |= SYS_PROC_DOWN; | 2501 | handle->rcb_table->state_flag |= SYS_PROC_DOWN; |
@@ -2558,9 +2561,9 @@ int ipu_pm_restore_ctx(int proc_id) | |||
2558 | pr_debug("hibernateAllowed=%d\n", | 2561 | pr_debug("hibernateAllowed=%d\n", |
2559 | handle->rcb_table->pm_flags.hibernateAllowed); | 2562 | handle->rcb_table->pm_flags.hibernateAllowed); |
2560 | first_time = 0; | 2563 | first_time = 0; |
2561 | cm_write_mod_reg(HW_AUTO, | 2564 | /*cm_write_mod_reg(HW_AUTO, |
2562 | OMAP4430_CM2_CORE_MOD, | 2565 | OMAP4430_CM2_CORE_MOD, |
2563 | OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET); | 2566 | OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET);*/ |
2564 | #ifdef CONFIG_OMAP_PM | 2567 | #ifdef CONFIG_OMAP_PM |
2565 | retval = omap_pm_set_max_sdma_lat(&pm_qos_handle_2, | 2568 | retval = omap_pm_set_max_sdma_lat(&pm_qos_handle_2, |
2566 | IPU_PM_MM_MPU_LAT_CONSTRAINT); | 2569 | IPU_PM_MM_MPU_LAT_CONSTRAINT); |
@@ -2596,18 +2599,18 @@ int ipu_pm_restore_ctx(int proc_id) | |||
2596 | 2599 | ||
2597 | pr_info("Wakeup SYSM3\n"); | 2600 | pr_info("Wakeup SYSM3\n"); |
2598 | retval = rproc_wakeup(sys_rproc); | 2601 | retval = rproc_wakeup(sys_rproc); |
2599 | cm_write_mod_reg(HW_AUTO, | 2602 | /*cm_write_mod_reg(HW_AUTO, |
2600 | OMAP4430_CM2_CORE_MOD, | 2603 | OMAP4430_CM2_CORE_MOD, |
2601 | OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET); | 2604 | OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET);*/ |
2602 | if (retval) | 2605 | if (retval) |
2603 | goto error; | 2606 | goto error; |
2604 | handle->rcb_table->state_flag &= ~SYS_PROC_DOWN; | 2607 | handle->rcb_table->state_flag &= ~SYS_PROC_DOWN; |
2605 | if (ipu_pm_get_state(proc_id) & APP_PROC_LOADED) { | 2608 | if (ipu_pm_get_state(proc_id) & APP_PROC_LOADED) { |
2606 | pr_info("Wakeup APPM3\n"); | 2609 | pr_info("Wakeup APPM3\n"); |
2607 | retval = rproc_wakeup(app_rproc); | 2610 | retval = rproc_wakeup(app_rproc); |
2608 | cm_write_mod_reg(HW_AUTO, | 2611 | /*cm_write_mod_reg(HW_AUTO, |
2609 | OMAP4430_CM2_CORE_MOD, | 2612 | OMAP4430_CM2_CORE_MOD, |
2610 | OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET); | 2613 | OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET);*/ |
2611 | if (retval) | 2614 | if (retval) |
2612 | goto error; | 2615 | goto error; |
2613 | handle->rcb_table->state_flag &= ~APP_PROC_DOWN; | 2616 | handle->rcb_table->state_flag &= ~APP_PROC_DOWN; |