[XTENSA] Add support for configurable registers and coprocessors

The Xtensa architecture allows to define custom instructions and
registers. Registers that are bound to a coprocessor are only
accessible if the corresponding enable bit is set, which allows
to implement a 'lazy' context switch mechanism. Other registers
needs to be saved and restore at the time of the context switch
or during interrupt handling.

This patch adds support for these additional states:

- save and restore registers that are used by the compiler upon
  interrupt entry and exit.
- context switch additional registers unbound to any coprocessor
- 'lazy' context switch of registers bound to a coprocessor
- ptrace interface to provide access to additional registers
- update configuration files in include/asm-xtensa/variant-fsf

Signed-off-by: Chris Zankel <chris@zankel.net>

17 files changed, 1065 insertions, 874 deletions

diff --git a/arch/xtensa/kernel/asm-offsets.c b/arch/xtensa/kernel/asm-offsets.c
index 5d9ef515ca1..ef63adadf7f 100644
--- a/arch/xtensa/kernel/asm-offsets.c
+++ b/arch/xtensa/kernel/asm-offsets.c
@@ -63,6 +63,8 @@ int main(void)
         DEFINE(PT_SIZE, sizeof(struct pt_regs));
         DEFINE(PT_AREG_END, offsetof (struct pt_regs, areg[XCHAL_NUM_AREGS]));
         DEFINE(PT_USER_SIZE, offsetof(struct pt_regs, areg[XCHAL_NUM_AREGS]));
+        DEFINE(PT_XTREGS_OPT, offsetof(struct pt_regs, xtregs_opt));
+        DEFINE(XTREGS_OPT_SIZE, sizeof(xtregs_opt_t));
 
         /* struct task_struct */
         DEFINE(TASK_PTRACE, offsetof (struct task_struct, ptrace));
@@ -76,7 +78,19 @@ int main(void)
         /* struct thread_info (offset from start_struct) */
         DEFINE(THREAD_RA, offsetof (struct task_struct, thread.ra));
         DEFINE(THREAD_SP, offsetof (struct task_struct, thread.sp));
-        DEFINE(THREAD_CP_SAVE, offsetof (struct task_struct, thread.cp_save));
+        DEFINE(THREAD_CPENABLE, offsetof (struct thread_info, cpenable));
+#if XTENSA_HAVE_COPROCESSORS
+        DEFINE(THREAD_XTREGS_CP0, offsetof (struct thread_info, xtregs_cp));
+        DEFINE(THREAD_XTREGS_CP1, offsetof (struct thread_info, xtregs_cp));
+        DEFINE(THREAD_XTREGS_CP2, offsetof (struct thread_info, xtregs_cp));
+        DEFINE(THREAD_XTREGS_CP3, offsetof (struct thread_info, xtregs_cp));
+        DEFINE(THREAD_XTREGS_CP4, offsetof (struct thread_info, xtregs_cp));
+        DEFINE(THREAD_XTREGS_CP5, offsetof (struct thread_info, xtregs_cp));
+        DEFINE(THREAD_XTREGS_CP6, offsetof (struct thread_info, xtregs_cp));
+        DEFINE(THREAD_XTREGS_CP7, offsetof (struct thread_info, xtregs_cp));
+#endif
+        DEFINE(THREAD_XTREGS_USER, offsetof (struct thread_info, xtregs_user));
+        DEFINE(XTREGS_USER_SIZE, sizeof(xtregs_user_t));
         DEFINE(THREAD_CURRENT_DS, offsetof (struct task_struct, thread.current_ds));
 
         /* struct mm_struct */
diff --git a/arch/xtensa/kernel/coprocessor.S b/arch/xtensa/kernel/coprocessor.S
index 01bcb9fcfcb..2bc1e145c0a 100644
--- a/arch/xtensa/kernel/coprocessor.S
+++ b/arch/xtensa/kernel/coprocessor.S
@@ -8,193 +8,328 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2003 - 2005 Tensilica Inc.
- *
- * Marc Gauthier <marc@tensilica.com> <marc@alumni.uwaterloo.ca>
+ * Copyright (C) 2003 - 2007 Tensilica Inc.
  */
 
-/*
- * This module contains a table that describes the layout of the various
- * custom registers and states associated with each coprocessor, as well
- * as those not associated with any coprocessor ("extra state").
- * This table is included with core dumps and is available via the ptrace
- * interface, allowing the layout of such register/state information to
- * be modified in the kernel without affecting the debugger.  Each
- * register or state is identified using a 32-bit "libdb target number"
- * assigned when the Xtensa processor is generated.
- */
 
 #include <linux/linkage.h>
+#include <asm/asm-offsets.h>
 #include <asm/processor.h>
+#include <asm/coprocessor.h>
+#include <asm/thread_info.h>
+#include <asm/uaccess.h>
+#include <asm/unistd.h>
+#include <asm/ptrace.h>
+#include <asm/current.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/signal.h>
+#include <asm/tlbflush.h>
 
-#if XCHAL_HAVE_CP
+/*
+ * Entry condition:
+ *
+ *   a0:        trashed, original value saved on stack (PT_AREG0)
+ *   a1:        a1
+ *   a2:        new stack pointer, original in DEPC
+ *   a3:        dispatch table
+ *   depc:      a2, original value saved on stack (PT_DEPC)
+ *   excsave_1: a3
+ *
+ *   PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
+ *           <  VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
+ */
 
-#define CP_LAST ((XCHAL_CP_MAX - 1) * COPROCESSOR_INFO_SIZE)
+/* IO protection is currently unsupported. */
 
-ENTRY(release_coprocessors)
+ENTRY(fast_io_protect)
+        wsr     a0, EXCSAVE_1
+        movi    a0, unrecoverable_exception
+        callx0  a0
 
-        entry   a1, 16
-                                                # a2: task
-        movi    a3, 1 << XCHAL_CP_MAX           # a3: coprocessor-bit
-        movi    a4, coprocessor_info+CP_LAST    # a4: owner-table
-                                                # a5: tmp
-        movi    a6, 0                           # a6: 0
-        rsil    a7, LOCKLEVEL                   # a7: PS
+#if XTENSA_HAVE_COPROCESSORS
 
-1:      /* Check if task is coprocessor owner of coprocessor[i]. */
+/*
+ * Macros for lazy context switch. 
+ */
 
-        l32i    a5, a4, COPROCESSOR_INFO_OWNER
-        srli    a3, a3, 1
-        beqz    a3, 1f
-        addi    a4, a4, -8
-        beq     a2, a5, 1b
+#define SAVE_CP_REGS(x)                                                 \
+        .align 4;                                                       \
+        .Lsave_cp_regs_cp##x:                                           \
+        .if XTENSA_HAVE_COPROCESSOR(x);                                 \
+                xchal_cp##x##_store a2 a4 a5 a6 a7;                     \
+        .endif;                                                         \
+        jx      a0
 
-        /* Found an entry: Clear entry CPENABLE bit to disable CP. */
+#define SAVE_CP_REGS_TAB(x)                                             \
+        .if XTENSA_HAVE_COPROCESSOR(x);                                 \
+                .long .Lsave_cp_regs_cp##x - .Lsave_cp_regs_jump_table; \
+        .else;                                                          \
+                .long 0;                                                \
+        .endif;                                                         \
+        .long THREAD_XTREGS_CP##x
 
-        rsr     a5, CPENABLE
-        s32i    a6, a4, COPROCESSOR_INFO_OWNER
-        xor     a5, a3, a5
-        wsr     a5, CPENABLE
 
-        bnez    a3, 1b
+#define LOAD_CP_REGS(x)                                                 \
+        .align 4;                                                       \
+        .Lload_cp_regs_cp##x:                                           \
+        .if XTENSA_HAVE_COPROCESSOR(x);                                 \
+                xchal_cp##x##_load a2 a4 a5 a6 a7;                      \
+        .endif;                                                         \
+        jx      a0
 
-1:      wsr     a7, PS
-        rsync
-        retw
+#define LOAD_CP_REGS_TAB(x)                                             \
+        .if XTENSA_HAVE_COPROCESSOR(x);                                 \
+                .long .Lload_cp_regs_cp##x - .Lload_cp_regs_jump_table; \
+        .else;                                                          \
+                .long 0;                                                \
+        .endif;                                                         \
+        .long THREAD_XTREGS_CP##x
 
+        SAVE_CP_REGS(0)
+        SAVE_CP_REGS(1)
+        SAVE_CP_REGS(2)
+        SAVE_CP_REGS(3)
+        SAVE_CP_REGS(4)
+        SAVE_CP_REGS(5)
+        SAVE_CP_REGS(6)
+        SAVE_CP_REGS(7)