gpio: driver for 42 AB8500 GPIO pins

To get rid of port expanders, the free GPIOs of ab8500
can be used. There are 42 GPIO pins. Out of which 16
are interrupt capable.This patch implements 16 virtual
IRQ mapped to 16 interrupt capable AB8500 GPIOs.

Signed-off-by: Bibek Basu <bibek.basu@stericsson.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
[Renamed header file as per MFD structure]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

7 files changed, 605 insertions, 1 deletions

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index d8d0cda2641..d3743204a7e 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -414,4 +414,9 @@ config GPIO_JANZ_TTL
           This driver provides support for driving the pins in output
           mode only. Input mode is not supported.
 
+config AB8500_GPIO
+        bool "ST-Ericsson AB8500 Mixed Signal Circuit gpio functions"
+        depends on AB8500_CORE
+        help
+          Select this to enable the AB8500 IC GPIO driver
 endif
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 3351cf87b0e..becef595435 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -42,3 +42,4 @@ obj-$(CONFIG_GPIO_JANZ_TTL)	+= janz-ttl.o
 obj-$(CONFIG_GPIO_SX150X)       += sx150x.o
 obj-$(CONFIG_GPIO_VX855)        += vx855_gpio.o
 obj-$(CONFIG_GPIO_ML_IOH)       += ml_ioh_gpio.o
+obj-$(CONFIG_AB8500_GPIO)       += ab8500-gpio.o
diff --git a/drivers/gpio/ab8500-gpio.c b/drivers/gpio/ab8500-gpio.c
new file mode 100644
index 00000000000..e7b834d054b
--- /dev/null
+++ b/drivers/gpio/ab8500-gpio.c
@@ -0,0 +1,522 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2011
+ *
+ * Author: BIBEK BASU <bibek.basu@stericsson.com>
+ * License terms: GNU General Public License (GPL) version 2
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/mfd/ab8500.h>
+#include <linux/mfd/abx500.h>
+#include <linux/mfd/ab8500/gpio.h>
+
+/*
+ * GPIO registers offset
+ * Bank: 0x10
+ */
+#define AB8500_GPIO_SEL1_REG    0x00
+#define AB8500_GPIO_SEL2_REG    0x01
+#define AB8500_GPIO_SEL3_REG    0x02
+#define AB8500_GPIO_SEL4_REG    0x03
+#define AB8500_GPIO_SEL5_REG    0x04
+#define AB8500_GPIO_SEL6_REG    0x05
+
+#define AB8500_GPIO_DIR1_REG    0x10
+#define AB8500_GPIO_DIR2_REG    0x11
+#define AB8500_GPIO_DIR3_REG    0x12
+#define AB8500_GPIO_DIR4_REG    0x13
+#define AB8500_GPIO_DIR5_REG    0x14
+#define AB8500_GPIO_DIR6_REG    0x15
+
+#define AB8500_GPIO_OUT1_REG    0x20
+#define AB8500_GPIO_OUT2_REG    0x21
+#define AB8500_GPIO_OUT3_REG    0x22
+#define AB8500_GPIO_OUT4_REG    0x23
+#define AB8500_GPIO_OUT5_REG    0x24
+#define AB8500_GPIO_OUT6_REG    0x25
+
+#define AB8500_GPIO_PUD1_REG    0x30
+#define AB8500_GPIO_PUD2_REG    0x31
+#define AB8500_GPIO_PUD3_REG    0x32
+#define AB8500_GPIO_PUD4_REG    0x33
+#define AB8500_GPIO_PUD5_REG    0x34
+#define AB8500_GPIO_PUD6_REG    0x35
+
+#define AB8500_GPIO_IN1_REG     0x40
+#define AB8500_GPIO_IN2_REG     0x41
+#define AB8500_GPIO_IN3_REG     0x42
+#define AB8500_GPIO_IN4_REG     0x43
+#define AB8500_GPIO_IN5_REG     0x44
+#define AB8500_GPIO_IN6_REG     0x45
+#define AB8500_GPIO_ALTFUN_REG  0x45
+#define ALTFUN_REG_INDEX        6
+#define AB8500_NUM_GPIO         42
+#define AB8500_NUM_VIR_GPIO_IRQ 16
+
+enum ab8500_gpio_action {
+        NONE,
+        STARTUP,
+        SHUTDOWN,
+        MASK,
+        UNMASK
+};
+
+struct ab8500_gpio {
+        struct gpio_chip chip;
+        struct ab8500 *parent;
+        struct device *dev;
+        struct mutex lock;
+        u32 irq_base;
+        enum ab8500_gpio_action irq_action;
+        u16 rising;
+        u16 falling;
+};
+/**
+ * to_ab8500_gpio() - get the pointer to ab8500_gpio
+ * @chip:       Member of the structure ab8500_gpio
+ */
+static inline struct ab8500_gpio *to_ab8500_gpio(struct gpio_chip *chip)
+{
+        return container_of(chip, struct ab8500_gpio, chip);
+}
+
+static int ab8500_gpio_set_bits(struct gpio_chip *chip, u8 reg,
+                                        unsigned offset, int val)
+{
+        struct ab8500_gpio *ab8500_gpio = to_ab8500_gpio(chip);
+        u8 pos = offset % 8;
+        int ret;
+
+        reg = reg + (offset / 8);
+        ret = abx500_mask_and_set_register_interruptible(ab8500_gpio->dev,
+                                AB8500_MISC, reg, 1 << pos, val << pos);
+        if (ret < 0)
+                dev_err(ab8500_gpio->dev, "%s write failed\n", __func__);
+        return ret;
+}
+/**
+ * ab8500_gpio_get() - Get the particular GPIO value
+ * @chip: Gpio device
+ * @offset: GPIO number to read
+ */
+static int ab8500_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+        struct ab8500_gpio *ab8500_gpio = to_ab8500_gpio(chip);
+        u8 mask = 1 << (offset % 8);
+        u8 reg = AB8500_GPIO_OUT1_REG + (offset / 8);
+        int ret;
+        u8 data;
+        ret = abx500_get_register_interruptible(ab8500_gpio->dev, AB8500_MISC,
+                                                reg, &data);
+        if (ret < 0) {
+                dev_err(ab8500_gpio->dev, "%s read failed\n", __func__);
+                return ret;
+        }
+        return (data & mask) >> (offset % 8);
+}
+
+static void ab8500_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
+{
+        struct ab8500_gpio *ab8500_gpio = to_ab8500_gpio(chip);
+        int ret;
+        /* Write the data */
+        ret = ab8500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, 1);
+        if (ret < 0)
+                dev_err(ab8500_gpio->dev, "%s write failed\n", __func__);
+}
+
+static int ab8500_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
+                                        int val)
+{
+        int ret;
+        /* set direction as output */
+        ret = ab8500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 1);
+        if (ret < 0)
+                return ret;
+        /* disable pull down */
+        ret = ab8500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG, offset, 1);
+        if (ret < 0)
+                return ret;
+        /* set the output as 1 or 0 */
+        return ab8500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val);
+
+}
+
+static int ab8500_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+        /* set the register as input */
+        return ab8500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 0);
+}
+
+static int ab8500_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+        /*
+         * Only some GPIOs are interrupt capable, and they are
+         * organized in discontiguous clusters:
+         *
+         *      GPIO6 to GPIO13
+         *      GPIO24 and GPIO25
+         *      GPIO36 to GPIO41
+         */
+        static struct ab8500_gpio_irq_cluster {
+                int start;
+                int end;
+        } clusters[] = {
+                {.start = 6,  .end = 13},
+                {.start = 24, .end = 25},
+                {.start = 36, .end = 41},