Commit message (Expand) | Author | Age | |
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* | Merge branch 'dev/s5pv310-irq' into next-s5pv310 | Kukjin Kim | 2010-12-30 |
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| * | ARM: S5PV310: Limit the irqs which support cascade interrupt | Changhwan Youn | 2010-12-08 |
* | | ARM: S5PV310: Add support Power Domain | Changhwan Youn | 2010-12-29 |
* | | ARM: S5PV310: Set bit 22 in the PL310 (cache controller) AuxCtlr register | Changhwan Youn | 2010-12-29 |
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* | ARM: S5PV310: Add support SROMC | Daein Moon | 2010-10-25 |
* | ARM: S5PV310: Add L2 cache init function in cpu.c | Kyungmin Park | 2010-10-25 |
* | ARM: S5P: Add initial map for GPIO2 and GPIO3 | Jongpill Lee | 2010-10-25 |
* | ARM: S5PV310: Add HSMMC platform data | Hyuk Lee | 2010-10-25 |
* | ARM: S5PV310: Fix build error on GPIO map | Kukjin Kim | 2010-10-18 |
* | ARM: S5P: Moves initial map for merging S5P64X0 | Kukjin Kim | 2010-10-17 |
* | ARM: S5PV310: Fix on Secondary CPU startup | Changhwan Youn | 2010-08-27 |
* | ARM: S5PV310: Add CMU block for S5PV310 Clock | Kukjin Kim | 2010-08-27 |
* | ARM: S5PV310: Add new CPU initialization support | Changhwan Youn | 2010-08-05 |