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-rw-r--r--include/asm-powerpc/io.h7
-rw-r--r--include/asm-powerpc/ipic.h12
-rw-r--r--include/asm-powerpc/mpc86xx.h3
-rw-r--r--include/asm-powerpc/mpic.h125
-rw-r--r--include/asm-powerpc/prom.h4
5 files changed, 142 insertions, 9 deletions
diff --git a/include/asm-powerpc/io.h b/include/asm-powerpc/io.h
index a9496f34b04..36c4c34bf56 100644
--- a/include/asm-powerpc/io.h
+++ b/include/asm-powerpc/io.h
@@ -72,6 +72,9 @@ extern unsigned long pci_io_base;
72 * Neither do the standard versions now, these are just here 72 * Neither do the standard versions now, these are just here
73 * for older code. 73 * for older code.
74 */ 74 */
75#define insb(port, buf, ns) _insb((u8 __iomem *)((port)+pci_io_base), (buf), (ns))
76#define insw(port, buf, ns) _insw_ns((u8 __iomem *)((port)+pci_io_base), (buf), (ns))
77#define insl(port, buf, nl) _insl_ns((u8 __iomem *)((port)+pci_io_base), (buf), (nl))
75#define insw_ns(port, buf, ns) _insw_ns((u16 __iomem *)((port)+pci_io_base), (buf), (ns)) 78#define insw_ns(port, buf, ns) _insw_ns((u16 __iomem *)((port)+pci_io_base), (buf), (ns))
76#define insl_ns(port, buf, nl) _insl_ns((u32 __iomem *)((port)+pci_io_base), (buf), (nl)) 79#define insl_ns(port, buf, nl) _insl_ns((u32 __iomem *)((port)+pci_io_base), (buf), (nl))
77#else 80#else
@@ -137,12 +140,12 @@ static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
137#define insw_ns(port, buf, ns) eeh_insw_ns((port), (buf), (ns)) 140#define insw_ns(port, buf, ns) eeh_insw_ns((port), (buf), (ns))
138#define insl_ns(port, buf, nl) eeh_insl_ns((port), (buf), (nl)) 141#define insl_ns(port, buf, nl) eeh_insl_ns((port), (buf), (nl))
139 142
143#endif
144
140#define outsb(port, buf, ns) _outsb((u8 __iomem *)((port)+pci_io_base), (buf), (ns)) 145#define outsb(port, buf, ns) _outsb((u8 __iomem *)((port)+pci_io_base), (buf), (ns))
141#define outsw(port, buf, ns) _outsw_ns((u16 __iomem *)((port)+pci_io_base), (buf), (ns)) 146#define outsw(port, buf, ns) _outsw_ns((u16 __iomem *)((port)+pci_io_base), (buf), (ns))
142#define outsl(port, buf, nl) _outsl_ns((u32 __iomem *)((port)+pci_io_base), (buf), (nl)) 147#define outsl(port, buf, nl) _outsl_ns((u32 __iomem *)((port)+pci_io_base), (buf), (nl))
143 148
144#endif
145
146#define readb_relaxed(addr) readb(addr) 149#define readb_relaxed(addr) readb(addr)
147#define readw_relaxed(addr) readw(addr) 150#define readw_relaxed(addr) readw(addr)
148#define readl_relaxed(addr) readl(addr) 151#define readl_relaxed(addr) readl(addr)
diff --git a/include/asm-powerpc/ipic.h b/include/asm-powerpc/ipic.h
index 0fe396a2b66..53079ec3a51 100644
--- a/include/asm-powerpc/ipic.h
+++ b/include/asm-powerpc/ipic.h
@@ -69,9 +69,6 @@ enum ipic_mcp_irq {
69 IPIC_MCP_MU = 7, 69 IPIC_MCP_MU = 7,
70}; 70};
71 71
72extern void ipic_init(phys_addr_t phys_addr, unsigned int flags,
73 unsigned int irq_offset,
74 unsigned char *senses, unsigned int senses_count);
75extern int ipic_set_priority(unsigned int irq, unsigned int priority); 72extern int ipic_set_priority(unsigned int irq, unsigned int priority);
76extern void ipic_set_highest_priority(unsigned int irq); 73extern void ipic_set_highest_priority(unsigned int irq);
77extern void ipic_set_default_priority(void); 74extern void ipic_set_default_priority(void);
@@ -79,7 +76,16 @@ extern void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq);
79extern void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq); 76extern void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq);
80extern u32 ipic_get_mcp_status(void); 77extern u32 ipic_get_mcp_status(void);
81extern void ipic_clear_mcp_status(u32 mask); 78extern void ipic_clear_mcp_status(u32 mask);
79
80#ifdef CONFIG_PPC_MERGE
81extern void ipic_init(struct device_node *node, unsigned int flags);
82extern unsigned int ipic_get_irq(struct pt_regs *regs);
83#else
84extern void ipic_init(phys_addr_t phys_addr, unsigned int flags,
85 unsigned int irq_offset,
86 unsigned char *senses, unsigned int senses_count);
82extern int ipic_get_irq(struct pt_regs *regs); 87extern int ipic_get_irq(struct pt_regs *regs);
88#endif
83 89
84#endif /* __ASM_IPIC_H__ */ 90#endif /* __ASM_IPIC_H__ */
85#endif /* __KERNEL__ */ 91#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/mpc86xx.h b/include/asm-powerpc/mpc86xx.h
index f260382739f..b85df45b1a8 100644
--- a/include/asm-powerpc/mpc86xx.h
+++ b/include/asm-powerpc/mpc86xx.h
@@ -23,8 +23,6 @@
23#define _ISA_MEM_BASE isa_mem_base 23#define _ISA_MEM_BASE isa_mem_base
24#ifdef CONFIG_PCI 24#ifdef CONFIG_PCI
25#define PCI_DRAM_OFFSET pci_dram_offset 25#define PCI_DRAM_OFFSET pci_dram_offset
26#else
27#define PCI_DRAM_OFFSET 0
28#endif 26#endif
29 27
30#define CPU0_BOOT_RELEASE 0x01000000 28#define CPU0_BOOT_RELEASE 0x01000000
@@ -33,7 +31,6 @@
33#define MCM_PORT_CONFIG_OFFSET 0x1010 31#define MCM_PORT_CONFIG_OFFSET 0x1010
34 32
35/* Offset from CCSRBAR */ 33/* Offset from CCSRBAR */
36#define MPC86xx_OPENPIC_OFFSET (0x40000)
37#define MPC86xx_MCM_OFFSET (0x00000) 34#define MPC86xx_MCM_OFFSET (0x00000)
38#define MPC86xx_MCM_SIZE (0x02000) 35#define MPC86xx_MCM_SIZE (0x02000)
39 36
diff --git a/include/asm-powerpc/mpic.h b/include/asm-powerpc/mpic.h
index eb241c99c45..a9f9604b9ef 100644
--- a/include/asm-powerpc/mpic.h
+++ b/include/asm-powerpc/mpic.h
@@ -41,6 +41,7 @@
41#define MPIC_GREG_IPI_VECTOR_PRI_1 0x000b0 41#define MPIC_GREG_IPI_VECTOR_PRI_1 0x000b0
42#define MPIC_GREG_IPI_VECTOR_PRI_2 0x000c0 42#define MPIC_GREG_IPI_VECTOR_PRI_2 0x000c0
43#define MPIC_GREG_IPI_VECTOR_PRI_3 0x000d0 43#define MPIC_GREG_IPI_VECTOR_PRI_3 0x000d0
44#define MPIC_GREG_IPI_STRIDE 0x10
44#define MPIC_GREG_SPURIOUS 0x000e0 45#define MPIC_GREG_SPURIOUS 0x000e0
45#define MPIC_GREG_TIMER_FREQ 0x000f0 46#define MPIC_GREG_TIMER_FREQ 0x000f0
46 47
@@ -68,6 +69,7 @@
68#define MPIC_CPU_IPI_DISPATCH_1 0x00050 69#define MPIC_CPU_IPI_DISPATCH_1 0x00050
69#define MPIC_CPU_IPI_DISPATCH_2 0x00060 70#define MPIC_CPU_IPI_DISPATCH_2 0x00060
70#define MPIC_CPU_IPI_DISPATCH_3 0x00070 71#define MPIC_CPU_IPI_DISPATCH_3 0x00070
72#define MPIC_CPU_IPI_DISPATCH_STRIDE 0x00010
71#define MPIC_CPU_CURRENT_TASK_PRI 0x00080 73#define MPIC_CPU_CURRENT_TASK_PRI 0x00080
72#define MPIC_CPU_TASKPRI_MASK 0x0000000f 74#define MPIC_CPU_TASKPRI_MASK 0x0000000f
73#define MPIC_CPU_WHOAMI 0x00090 75#define MPIC_CPU_WHOAMI 0x00090
@@ -114,6 +116,103 @@
114#define MPIC_VEC_TIMER_1 248 116#define MPIC_VEC_TIMER_1 248
115#define MPIC_VEC_TIMER_0 247 117#define MPIC_VEC_TIMER_0 247
116 118
119/*
120 * Tsi108 implementation of MPIC has many differences from the original one
121 */
122
123/*
124 * Global registers
125 */
126
127#define TSI108_GREG_BASE 0x00000
128#define TSI108_GREG_FEATURE_0 0x00000
129#define TSI108_GREG_GLOBAL_CONF_0 0x00004
130#define TSI108_GREG_VENDOR_ID 0x0000c
131#define TSI108_GREG_IPI_VECTOR_PRI_0 0x00204 /* Doorbell 0 */
132#define TSI108_GREG_IPI_STRIDE 0x0c
133#define TSI108_GREG_SPURIOUS 0x00010
134#define TSI108_GREG_TIMER_FREQ 0x00014
135
136/*
137 * Timer registers
138 */
139#define TSI108_TIMER_BASE 0x0030
140#define TSI108_TIMER_STRIDE 0x10
141#define TSI108_TIMER_CURRENT_CNT 0x00000
142#define TSI108_TIMER_BASE_CNT 0x00004
143#define TSI108_TIMER_VECTOR_PRI 0x00008
144#define TSI108_TIMER_DESTINATION 0x0000c
145
146/*
147 * Per-Processor registers
148 */
149#define TSI108_CPU_BASE 0x00300
150#define TSI108_CPU_STRIDE 0x00040
151#define TSI108_CPU_IPI_DISPATCH_0 0x00200
152#define TSI108_CPU_IPI_DISPATCH_STRIDE 0x00000
153#define TSI108_CPU_CURRENT_TASK_PRI 0x00000
154#define TSI108_CPU_WHOAMI 0xffffffff
155#define TSI108_CPU_INTACK 0x00004
156#define TSI108_CPU_EOI 0x00008
157
158/*
159 * Per-source registers
160 */
161#define TSI108_IRQ_BASE 0x00100
162#define TSI108_IRQ_STRIDE 0x00008
163#define TSI108_IRQ_VECTOR_PRI 0x00000
164#define TSI108_VECPRI_VECTOR_MASK 0x000000ff
165#define TSI108_VECPRI_POLARITY_POSITIVE 0x01000000
166#define TSI108_VECPRI_POLARITY_NEGATIVE 0x00000000
167#define TSI108_VECPRI_SENSE_LEVEL 0x02000000
168#define TSI108_VECPRI_SENSE_EDGE 0x00000000
169#define TSI108_VECPRI_POLARITY_MASK 0x01000000
170#define TSI108_VECPRI_SENSE_MASK 0x02000000
171#define TSI108_IRQ_DESTINATION 0x00004
172
173/* weird mpic register indices and mask bits in the HW info array */
174enum {
175 MPIC_IDX_GREG_BASE = 0,
176 MPIC_IDX_GREG_FEATURE_0,
177 MPIC_IDX_GREG_GLOBAL_CONF_0,
178 MPIC_IDX_GREG_VENDOR_ID,
179 MPIC_IDX_GREG_IPI_VECTOR_PRI_0,
180 MPIC_IDX_GREG_IPI_STRIDE,
181 MPIC_IDX_GREG_SPURIOUS,
182 MPIC_IDX_GREG_TIMER_FREQ,
183
184 MPIC_IDX_TIMER_BASE,
185 MPIC_IDX_TIMER_STRIDE,
186 MPIC_IDX_TIMER_CURRENT_CNT,
187 MPIC_IDX_TIMER_BASE_CNT,
188 MPIC_IDX_TIMER_VECTOR_PRI,
189 MPIC_IDX_TIMER_DESTINATION,
190
191 MPIC_IDX_CPU_BASE,
192 MPIC_IDX_CPU_STRIDE,
193 MPIC_IDX_CPU_IPI_DISPATCH_0,
194 MPIC_IDX_CPU_IPI_DISPATCH_STRIDE,
195 MPIC_IDX_CPU_CURRENT_TASK_PRI,
196 MPIC_IDX_CPU_WHOAMI,
197 MPIC_IDX_CPU_INTACK,
198 MPIC_IDX_CPU_EOI,
199
200 MPIC_IDX_IRQ_BASE,
201 MPIC_IDX_IRQ_STRIDE,
202 MPIC_IDX_IRQ_VECTOR_PRI,
203
204 MPIC_IDX_VECPRI_VECTOR_MASK,
205 MPIC_IDX_VECPRI_POLARITY_POSITIVE,
206 MPIC_IDX_VECPRI_POLARITY_NEGATIVE,
207 MPIC_IDX_VECPRI_SENSE_LEVEL,
208 MPIC_IDX_VECPRI_SENSE_EDGE,
209 MPIC_IDX_VECPRI_POLARITY_MASK,
210 MPIC_IDX_VECPRI_SENSE_MASK,
211 MPIC_IDX_IRQ_DESTINATION,
212 MPIC_IDX_END
213};
214
215
117#ifdef CONFIG_MPIC_BROKEN_U3 216#ifdef CONFIG_MPIC_BROKEN_U3
118/* Fixup table entry */ 217/* Fixup table entry */
119struct mpic_irq_fixup 218struct mpic_irq_fixup
@@ -171,15 +270,29 @@ struct mpic
171 volatile u32 __iomem *cpuregs[MPIC_MAX_CPUS]; 270 volatile u32 __iomem *cpuregs[MPIC_MAX_CPUS];
172 volatile u32 __iomem *isus[MPIC_MAX_ISU]; 271 volatile u32 __iomem *isus[MPIC_MAX_ISU];
173 272
273#ifdef CONFIG_MPIC_WEIRD
274 /* Pointer to HW info array */
275 u32 *hw_set;
276#endif
277
174 /* link */ 278 /* link */
175 struct mpic *next; 279 struct mpic *next;
176}; 280};
177 281
282/*
283 * MPIC flags (passed to mpic_alloc)
284 *
285 * The top 4 bits contain an MPIC bhw id that is used to index the
286 * register offsets and some masks when CONFIG_MPIC_WEIRD is set.
287 * Note setting any ID (leaving those bits to 0) means standard MPIC
288 */
289
178/* This is the primary controller, only that one has IPIs and 290/* This is the primary controller, only that one has IPIs and
179 * has afinity control. A non-primary MPIC always uses CPU0 291 * has afinity control. A non-primary MPIC always uses CPU0
180 * registers only 292 * registers only
181 */ 293 */
182#define MPIC_PRIMARY 0x00000001 294#define MPIC_PRIMARY 0x00000001
295
183/* Set this for a big-endian MPIC */ 296/* Set this for a big-endian MPIC */
184#define MPIC_BIG_ENDIAN 0x00000002 297#define MPIC_BIG_ENDIAN 0x00000002
185/* Broken U3 MPIC */ 298/* Broken U3 MPIC */
@@ -188,6 +301,18 @@ struct mpic
188#define MPIC_BROKEN_IPI 0x00000008 301#define MPIC_BROKEN_IPI 0x00000008
189/* MPIC wants a reset */ 302/* MPIC wants a reset */
190#define MPIC_WANTS_RESET 0x00000010 303#define MPIC_WANTS_RESET 0x00000010
304/* Spurious vector requires EOI */
305#define MPIC_SPV_EOI 0x00000020
306/* No passthrough disable */
307#define MPIC_NO_PTHROU_DIS 0x00000040
308
309/* MPIC HW modification ID */
310#define MPIC_REGSET_MASK 0xf0000000
311#define MPIC_REGSET(val) (((val) & 0xf ) << 28)
312#define MPIC_GET_REGSET(flags) (((flags) >> 28) & 0xf)
313
314#define MPIC_REGSET_STANDARD MPIC_REGSET(0) /* Original MPIC */
315#define MPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109 PIC */
191 316
192/* Allocate the controller structure and setup the linux irq descs 317/* Allocate the controller structure and setup the linux irq descs
193 * for the range if interrupts passed in. No HW initialization is 318 * for the range if interrupts passed in. No HW initialization is
diff --git a/include/asm-powerpc/prom.h b/include/asm-powerpc/prom.h
index b095a285c84..d0fa1b9aed3 100644
--- a/include/asm-powerpc/prom.h
+++ b/include/asm-powerpc/prom.h
@@ -276,6 +276,7 @@ extern void of_irq_map_init(unsigned int flags);
276 * of_irq_map_raw - Low level interrupt tree parsing 276 * of_irq_map_raw - Low level interrupt tree parsing
277 * @parent: the device interrupt parent 277 * @parent: the device interrupt parent
278 * @intspec: interrupt specifier ("interrupts" property of the device) 278 * @intspec: interrupt specifier ("interrupts" property of the device)
279 * @ointsize: size of the passed in interrupt specifier
279 * @addr: address specifier (start of "reg" property of the device) 280 * @addr: address specifier (start of "reg" property of the device)
280 * @out_irq: structure of_irq filled by this function 281 * @out_irq: structure of_irq filled by this function
281 * 282 *
@@ -288,7 +289,8 @@ extern void of_irq_map_init(unsigned int flags);
288 * 289 *
289 */ 290 */
290 291
291extern int of_irq_map_raw(struct device_node *parent, u32 *intspec, u32 *addr, 292extern int of_irq_map_raw(struct device_node *parent, u32 *intspec,
293 u32 ointsize, u32 *addr,
292 struct of_irq *out_irq); 294 struct of_irq *out_irq);
293 295
294 296