diff options
Diffstat (limited to 'include/linux/pci_regs.h')
| -rw-r--r-- | include/linux/pci_regs.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h index 450684f7eaa..e5effd47ed7 100644 --- a/include/linux/pci_regs.h +++ b/include/linux/pci_regs.h | |||
| @@ -377,6 +377,7 @@ | |||
| 377 | #define PCI_EXP_DEVCAP_RBER 0x8000 /* Role-Based Error Reporting */ | 377 | #define PCI_EXP_DEVCAP_RBER 0x8000 /* Role-Based Error Reporting */ |
| 378 | #define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */ | 378 | #define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */ |
| 379 | #define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */ | 379 | #define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */ |
| 380 | #define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ | ||
| 380 | #define PCI_EXP_DEVCTL 8 /* Device Control */ | 381 | #define PCI_EXP_DEVCTL 8 /* Device Control */ |
| 381 | #define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */ | 382 | #define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */ |
| 382 | #define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */ | 383 | #define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */ |
| @@ -389,6 +390,7 @@ | |||
| 389 | #define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */ | 390 | #define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */ |
| 390 | #define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */ | 391 | #define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */ |
| 391 | #define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */ | 392 | #define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */ |
| 393 | #define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ | ||
| 392 | #define PCI_EXP_DEVSTA 10 /* Device Status */ | 394 | #define PCI_EXP_DEVSTA 10 /* Device Status */ |
| 393 | #define PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */ | 395 | #define PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */ |
| 394 | #define PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */ | 396 | #define PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */ |
| @@ -419,6 +421,10 @@ | |||
| 419 | #define PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS Software Visibility Enable */ | 421 | #define PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS Software Visibility Enable */ |
| 420 | #define PCI_EXP_RTCAP 30 /* Root Capabilities */ | 422 | #define PCI_EXP_RTCAP 30 /* Root Capabilities */ |
| 421 | #define PCI_EXP_RTSTA 32 /* Root Status */ | 423 | #define PCI_EXP_RTSTA 32 /* Root Status */ |
| 424 | #define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */ | ||
| 425 | #define PCI_EXP_DEVCAP2_ARI 0x20 /* Alternative Routing-ID */ | ||
| 426 | #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ | ||
| 427 | #define PCI_EXP_DEVCTL2_ARI 0x20 /* Alternative Routing-ID */ | ||
| 422 | 428 | ||
| 423 | /* Extended Capabilities (PCI-X 2.0 and Express) */ | 429 | /* Extended Capabilities (PCI-X 2.0 and Express) */ |
| 424 | #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) | 430 | #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) |
| @@ -429,6 +435,7 @@ | |||
| 429 | #define PCI_EXT_CAP_ID_VC 2 | 435 | #define PCI_EXT_CAP_ID_VC 2 |
| 430 | #define PCI_EXT_CAP_ID_DSN 3 | 436 | #define PCI_EXT_CAP_ID_DSN 3 |
| 431 | #define PCI_EXT_CAP_ID_PWR 4 | 437 | #define PCI_EXT_CAP_ID_PWR 4 |
| 438 | #define PCI_EXT_CAP_ID_ARI 14 | ||
| 432 | 439 | ||
| 433 | /* Advanced Error Reporting */ | 440 | /* Advanced Error Reporting */ |
| 434 | #define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */ | 441 | #define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */ |
| @@ -536,5 +543,14 @@ | |||
| 536 | #define HT_CAPTYPE_GEN3 0xD0 /* Generation 3 hypertransport configuration */ | 543 | #define HT_CAPTYPE_GEN3 0xD0 /* Generation 3 hypertransport configuration */ |
| 537 | #define HT_CAPTYPE_PM 0xE0 /* Hypertransport powermanagement configuration */ | 544 | #define HT_CAPTYPE_PM 0xE0 /* Hypertransport powermanagement configuration */ |
| 538 | 545 | ||
| 546 | /* Alternative Routing-ID Interpretation */ | ||
| 547 | #define PCI_ARI_CAP 0x04 /* ARI Capability Register */ | ||
| 548 | #define PCI_ARI_CAP_MFVC 0x0001 /* MFVC Function Groups Capability */ | ||
| 549 | #define PCI_ARI_CAP_ACS 0x0002 /* ACS Function Groups Capability */ | ||
| 550 | #define PCI_ARI_CAP_NFN(x) (((x) >> 8) & 0xff) /* Next Function Number */ | ||
| 551 | #define PCI_ARI_CTRL 0x06 /* ARI Control Register */ | ||
| 552 | #define PCI_ARI_CTRL_MFVC 0x0001 /* MFVC Function Groups Enable */ | ||
| 553 | #define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */ | ||
| 554 | #define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */ | ||
| 539 | 555 | ||
| 540 | #endif /* LINUX_PCI_REGS_H */ | 556 | #endif /* LINUX_PCI_REGS_H */ |