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-rw-r--r--include/asm-x86/dma.h318
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diff --git a/include/asm-x86/dma.h b/include/asm-x86/dma.h
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index c9f7a4eec55..00000000000
--- a/include/asm-x86/dma.h
+++ /dev/null
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1/*
2 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
3 * Written by Hennus Bergman, 1992.
4 * High DMA channel support & info by Hannu Savolainen
5 * and John Boyd, Nov. 1992.
6 */
7
8#ifndef ASM_X86__DMA_H
9#define ASM_X86__DMA_H
10
11#include <linux/spinlock.h> /* And spinlocks */
12#include <asm/io.h> /* need byte IO */
13#include <linux/delay.h>
14
15#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
16#define dma_outb outb_p
17#else
18#define dma_outb outb
19#endif
20
21#define dma_inb inb
22
23/*
24 * NOTES about DMA transfers:
25 *
26 * controller 1: channels 0-3, byte operations, ports 00-1F
27 * controller 2: channels 4-7, word operations, ports C0-DF
28 *
29 * - ALL registers are 8 bits only, regardless of transfer size
30 * - channel 4 is not used - cascades 1 into 2.
31 * - channels 0-3 are byte - addresses/counts are for physical bytes
32 * - channels 5-7 are word - addresses/counts are for physical words
33 * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
34 * - transfer count loaded to registers is 1 less than actual count
35 * - controller 2 offsets are all even (2x offsets for controller 1)
36 * - page registers for 5-7 don't use data bit 0, represent 128K pages
37 * - page registers for 0-3 use bit 0, represent 64K pages
38 *
39 * DMA transfers are limited to the lower 16MB of _physical_ memory.
40 * Note that addresses loaded into registers must be _physical_ addresses,
41 * not logical addresses (which may differ if paging is active).
42 *
43 * Address mapping for channels 0-3:
44 *
45 * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
46 * | ... | | ... | | ... |
47 * | ... | | ... | | ... |
48 * | ... | | ... | | ... |
49 * P7 ... P0 A7 ... A0 A7 ... A0
50 * | Page | Addr MSB | Addr LSB | (DMA registers)
51 *
52 * Address mapping for channels 5-7:
53 *
54 * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
55 * | ... | \ \ ... \ \ \ ... \ \
56 * | ... | \ \ ... \ \ \ ... \ (not used)
57 * | ... | \ \ ... \ \ \ ... \
58 * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
59 * | Page | Addr MSB | Addr LSB | (DMA registers)
60 *
61 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
62 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
63 * the hardware level, so odd-byte transfers aren't possible).
64 *
65 * Transfer count (_not # bytes_) is limited to 64K, represented as actual
66 * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
67 * and up to 128K bytes may be transferred on channels 5-7 in one operation.
68 *
69 */
70
71#define MAX_DMA_CHANNELS 8
72
73#ifdef CONFIG_X86_32
74
75/* The maximum address that we can perform a DMA transfer to on this platform */
76#define MAX_DMA_ADDRESS (PAGE_OFFSET + 0x1000000)
77
78#else
79
80/* 16MB ISA DMA zone */
81#define MAX_DMA_PFN ((16 * 1024 * 1024) >> PAGE_SHIFT)
82
83/* 4GB broken PCI/AGP hardware bus master zone */
84#define MAX_DMA32_PFN ((4UL * 1024 * 1024 * 1024) >> PAGE_SHIFT)
85
86/* Compat define for old dma zone */
87#define MAX_DMA_ADDRESS ((unsigned long)__va(MAX_DMA_PFN << PAGE_SHIFT))
88
89#endif
90
91/* 8237 DMA controllers */
92#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
93#define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
94
95/* DMA controller registers */
96#define DMA1_CMD_REG 0x08 /* command register (w) */
97#define DMA1_STAT_REG 0x08 /* status register (r) */
98#define DMA1_REQ_REG 0x09 /* request register (w) */
99#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
100#define DMA1_MODE_REG 0x0B /* mode register (w) */
101#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
102#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
103#define DMA1_RESET_REG 0x0D /* Master Clear (w) */
104#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
105#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
106
107#define DMA2_CMD_REG 0xD0 /* command register (w) */
108#define DMA2_STAT_REG 0xD0 /* status register (r) */
109#define DMA2_REQ_REG 0xD2 /* request register (w) */
110#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
111#define DMA2_MODE_REG 0xD6 /* mode register (w) */
112#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
113#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
114#define DMA2_RESET_REG 0xDA /* Master Clear (w) */
115#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
116#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
117
118#define DMA_ADDR_0 0x00 /* DMA address registers */
119#define DMA_ADDR_1 0x02
120#define DMA_ADDR_2 0x04
121#define DMA_ADDR_3 0x06
122#define DMA_ADDR_4 0xC0
123#define DMA_ADDR_5 0xC4
124#define DMA_ADDR_6 0xC8
125#define DMA_ADDR_7 0xCC
126
127#define DMA_CNT_0 0x01 /* DMA count registers */
128#define DMA_CNT_1 0x03
129#define DMA_CNT_2 0x05
130#define DMA_CNT_3 0x07
131#define DMA_CNT_4 0xC2
132#define DMA_CNT_5 0xC6
133#define DMA_CNT_6 0xCA
134#define DMA_CNT_7 0xCE
135
136#define DMA_PAGE_0 0x87 /* DMA page registers */
137#define DMA_PAGE_1 0x83
138#define DMA_PAGE_2 0x81
139#define DMA_PAGE_3 0x82
140#define DMA_PAGE_5 0x8B
141#define DMA_PAGE_6 0x89
142#define DMA_PAGE_7 0x8A
143
144/* I/O to memory, no autoinit, increment, single mode */
145#define DMA_MODE_READ 0x44
146/* memory to I/O, no autoinit, increment, single mode */
147#define DMA_MODE_WRITE 0x48
148/* pass thru DREQ->HRQ, DACK<-HLDA only */
149#define DMA_MODE_CASCADE 0xC0
150
151#define DMA_AUTOINIT 0x10
152
153
154extern spinlock_t dma_spin_lock;
155
156static inline unsigned long claim_dma_lock(void)
157{
158 unsigned long flags;
159 spin_lock_irqsave(&dma_spin_lock, flags);
160 return flags;
161}
162
163static inline void release_dma_lock(unsigned long flags)
164{
165 spin_unlock_irqrestore(&dma_spin_lock, flags);
166}
167
168/* enable/disable a specific DMA channel */
169static inline void enable_dma(unsigned int dmanr)
170{
171 if (dmanr <= 3)
172 dma_outb(dmanr, DMA1_MASK_REG);
173 else
174 dma_outb(dmanr & 3, DMA2_MASK_REG);
175}
176
177static inline void disable_dma(unsigned int dmanr)
178{
179 if (dmanr <= 3)
180 dma_outb(dmanr | 4, DMA1_MASK_REG);
181 else
182 dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
183}
184
185/* Clear the 'DMA Pointer Flip Flop'.
186 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
187 * Use this once to initialize the FF to a known state.
188 * After that, keep track of it. :-)
189 * --- In order to do that, the DMA routines below should ---
190 * --- only be used while holding the DMA lock ! ---
191 */
192static inline void clear_dma_ff(unsigned int dmanr)
193{
194 if (dmanr <= 3)
195 dma_outb(0, DMA1_CLEAR_FF_REG);
196 else
197 dma_outb(0, DMA2_CLEAR_FF_REG);
198}
199
200/* set mode (above) for a specific DMA channel */
201static inline void set_dma_mode(unsigned int dmanr, char mode)
202{
203 if (dmanr <= 3)
204 dma_outb(mode | dmanr, DMA1_MODE_REG);
205 else
206 dma_outb(mode | (dmanr & 3), DMA2_MODE_REG);
207}
208
209/* Set only the page register bits of the transfer address.
210 * This is used for successive transfers when we know the contents of
211 * the lower 16 bits of the DMA current address register, but a 64k boundary
212 * may have been crossed.
213 */
214static inline void set_dma_page(unsigned int dmanr, char pagenr)
215{
216 switch (dmanr) {
217 case 0:
218 dma_outb(pagenr, DMA_PAGE_0);
219 break;
220 case 1:
221 dma_outb(pagenr, DMA_PAGE_1);
222 break;
223 case 2:
224 dma_outb(pagenr, DMA_PAGE_2);
225 break;
226 case 3:
227 dma_outb(pagenr, DMA_PAGE_3);
228 break;
229 case 5:
230 dma_outb(pagenr & 0xfe, DMA_PAGE_5);
231 break;
232 case 6:
233 dma_outb(pagenr & 0xfe, DMA_PAGE_6);
234 break;
235 case 7:
236 dma_outb(pagenr & 0xfe, DMA_PAGE_7);
237 break;
238 }
239}
240
241
242/* Set transfer address & page bits for specific DMA channel.
243 * Assumes dma flipflop is clear.
244 */
245static inline void set_dma_addr(unsigned int dmanr, unsigned int a)
246{
247 set_dma_page(dmanr, a>>16);
248 if (dmanr <= 3) {
249 dma_outb(a & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE);
250 dma_outb((a >> 8) & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE);
251 } else {
252 dma_outb((a >> 1) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
253 dma_outb((a >> 9) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
254 }
255}
256
257
258/* Set transfer size (max 64k for DMA0..3, 128k for DMA5..7) for
259 * a specific DMA channel.
260 * You must ensure the parameters are valid.
261 * NOTE: from a manual: "the number of transfers is one more
262 * than the initial word count"! This is taken into account.
263 * Assumes dma flip-flop is clear.
264 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
265 */
266static inline void set_dma_count(unsigned int dmanr, unsigned int count)
267{
268 count--;
269 if (dmanr <= 3) {
270 dma_outb(count & 0xff, ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
271 dma_outb((count >> 8) & 0xff,
272 ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
273 } else {
274 dma_outb((count >> 1) & 0xff,
275 ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
276 dma_outb((count >> 9) & 0xff,
277 ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
278 }
279}
280
281
282/* Get DMA residue count. After a DMA transfer, this
283 * should return zero. Reading this while a DMA transfer is
284 * still in progress will return unpredictable results.
285 * If called before the channel has been used, it may return 1.
286 * Otherwise, it returns the number of _bytes_ left to transfer.
287 *
288 * Assumes DMA flip-flop is clear.
289 */
290static inline int get_dma_residue(unsigned int dmanr)
291{
292 unsigned int io_port;
293 /* using short to get 16-bit wrap around */
294 unsigned short count;
295
296 io_port = (dmanr <= 3) ? ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE
297 : ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE;
298
299 count = 1 + dma_inb(io_port);
300 count += dma_inb(io_port) << 8;
301
302 return (dmanr <= 3) ? count : (count << 1);
303}
304
305
306/* These are in kernel/dma.c: */
307extern int request_dma(unsigned int dmanr, const char *device_id);
308extern void free_dma(unsigned int dmanr);
309
310/* From PCI */
311
312#ifdef CONFIG_PCI
313extern int isa_dma_bridge_buggy;
314#else
315#define isa_dma_bridge_buggy (0)
316#endif
317
318#endif /* ASM_X86__DMA_H */
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