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-rw-r--r--include/asm-x86/desc.h409
1 files changed, 0 insertions, 409 deletions
diff --git a/include/asm-x86/desc.h b/include/asm-x86/desc.h
deleted file mode 100644
index f06adac7938..00000000000
--- a/include/asm-x86/desc.h
+++ /dev/null
@@ -1,409 +0,0 @@
1#ifndef ASM_X86__DESC_H
2#define ASM_X86__DESC_H
3
4#ifndef __ASSEMBLY__
5#include <asm/desc_defs.h>
6#include <asm/ldt.h>
7#include <asm/mmu.h>
8#include <linux/smp.h>
9
10static inline void fill_ldt(struct desc_struct *desc,
11 const struct user_desc *info)
12{
13 desc->limit0 = info->limit & 0x0ffff;
14 desc->base0 = info->base_addr & 0x0000ffff;
15
16 desc->base1 = (info->base_addr & 0x00ff0000) >> 16;
17 desc->type = (info->read_exec_only ^ 1) << 1;
18 desc->type |= info->contents << 2;
19 desc->s = 1;
20 desc->dpl = 0x3;
21 desc->p = info->seg_not_present ^ 1;
22 desc->limit = (info->limit & 0xf0000) >> 16;
23 desc->avl = info->useable;
24 desc->d = info->seg_32bit;
25 desc->g = info->limit_in_pages;
26 desc->base2 = (info->base_addr & 0xff000000) >> 24;
27 /*
28 * Don't allow setting of the lm bit. It is useless anyway
29 * because 64bit system calls require __USER_CS:
30 */
31 desc->l = 0;
32}
33
34extern struct desc_ptr idt_descr;
35extern gate_desc idt_table[];
36
37struct gdt_page {
38 struct desc_struct gdt[GDT_ENTRIES];
39} __attribute__((aligned(PAGE_SIZE)));
40DECLARE_PER_CPU(struct gdt_page, gdt_page);
41
42static inline struct desc_struct *get_cpu_gdt_table(unsigned int cpu)
43{
44 return per_cpu(gdt_page, cpu).gdt;
45}
46
47#ifdef CONFIG_X86_64
48
49static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func,
50 unsigned dpl, unsigned ist, unsigned seg)
51{
52 gate->offset_low = PTR_LOW(func);
53 gate->segment = __KERNEL_CS;
54 gate->ist = ist;
55 gate->p = 1;
56 gate->dpl = dpl;
57 gate->zero0 = 0;
58 gate->zero1 = 0;
59 gate->type = type;
60 gate->offset_middle = PTR_MIDDLE(func);
61 gate->offset_high = PTR_HIGH(func);
62}
63
64#else
65static inline void pack_gate(gate_desc *gate, unsigned char type,
66 unsigned long base, unsigned dpl, unsigned flags,
67 unsigned short seg)
68{
69 gate->a = (seg << 16) | (base & 0xffff);
70 gate->b = (base & 0xffff0000) |
71 (((0x80 | type | (dpl << 5)) & 0xff) << 8);
72}
73
74#endif
75
76static inline int desc_empty(const void *ptr)
77{
78 const u32 *desc = ptr;
79 return !(desc[0] | desc[1]);
80}
81
82#ifdef CONFIG_PARAVIRT
83#include <asm/paravirt.h>
84#else
85#define load_TR_desc() native_load_tr_desc()
86#define load_gdt(dtr) native_load_gdt(dtr)
87#define load_idt(dtr) native_load_idt(dtr)
88#define load_tr(tr) asm volatile("ltr %0"::"m" (tr))
89#define load_ldt(ldt) asm volatile("lldt %0"::"m" (ldt))
90
91#define store_gdt(dtr) native_store_gdt(dtr)
92#define store_idt(dtr) native_store_idt(dtr)
93#define store_tr(tr) (tr = native_store_tr())
94#define store_ldt(ldt) asm("sldt %0":"=m" (ldt))
95
96#define load_TLS(t, cpu) native_load_tls(t, cpu)
97#define set_ldt native_set_ldt
98
99#define write_ldt_entry(dt, entry, desc) \
100 native_write_ldt_entry(dt, entry, desc)
101#define write_gdt_entry(dt, entry, desc, type) \
102 native_write_gdt_entry(dt, entry, desc, type)
103#define write_idt_entry(dt, entry, g) \
104 native_write_idt_entry(dt, entry, g)
105
106static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries)
107{
108}
109
110static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries)
111{
112}
113#endif /* CONFIG_PARAVIRT */
114
115static inline void native_write_idt_entry(gate_desc *idt, int entry,
116 const gate_desc *gate)
117{
118 memcpy(&idt[entry], gate, sizeof(*gate));
119}
120
121static inline void native_write_ldt_entry(struct desc_struct *ldt, int entry,
122 const void *desc)
123{
124 memcpy(&ldt[entry], desc, 8);
125}
126
127static inline void native_write_gdt_entry(struct desc_struct *gdt, int entry,
128 const void *desc, int type)
129{
130 unsigned int size;
131 switch (type) {
132 case DESC_TSS:
133 size = sizeof(tss_desc);
134 break;
135 case DESC_LDT:
136 size = sizeof(ldt_desc);
137 break;
138 default:
139 size = sizeof(struct desc_struct);
140 break;
141 }
142 memcpy(&gdt[entry], desc, size);
143}
144
145static inline void pack_descriptor(struct desc_struct *desc, unsigned long base,
146 unsigned long limit, unsigned char type,
147 unsigned char flags)
148{
149 desc->a = ((base & 0xffff) << 16) | (limit & 0xffff);
150 desc->b = (base & 0xff000000) | ((base & 0xff0000) >> 16) |
151 (limit & 0x000f0000) | ((type & 0xff) << 8) |
152 ((flags & 0xf) << 20);
153 desc->p = 1;
154}
155
156
157static inline void set_tssldt_descriptor(void *d, unsigned long addr,
158 unsigned type, unsigned size)
159{
160#ifdef CONFIG_X86_64
161 struct ldttss_desc64 *desc = d;
162 memset(desc, 0, sizeof(*desc));
163 desc->limit0 = size & 0xFFFF;
164 desc->base0 = PTR_LOW(addr);
165 desc->base1 = PTR_MIDDLE(addr) & 0xFF;
166 desc->type = type;
167 desc->p = 1;
168 desc->limit1 = (size >> 16) & 0xF;
169 desc->base2 = (PTR_MIDDLE(addr) >> 8) & 0xFF;
170 desc->base3 = PTR_HIGH(addr);
171#else
172 pack_descriptor((struct desc_struct *)d, addr, size, 0x80 | type, 0);
173#endif
174}
175
176static inline void __set_tss_desc(unsigned cpu, unsigned int entry, void *addr)
177{
178 struct desc_struct *d = get_cpu_gdt_table(cpu);
179 tss_desc tss;
180
181 /*
182 * sizeof(unsigned long) coming from an extra "long" at the end
183 * of the iobitmap. See tss_struct definition in processor.h
184 *
185 * -1? seg base+limit should be pointing to the address of the
186 * last valid byte
187 */
188 set_tssldt_descriptor(&tss, (unsigned long)addr, DESC_TSS,
189 IO_BITMAP_OFFSET + IO_BITMAP_BYTES +
190 sizeof(unsigned long) - 1);
191 write_gdt_entry(d, entry, &tss, DESC_TSS);
192}
193
194#define set_tss_desc(cpu, addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr)
195
196static inline void native_set_ldt(const void *addr, unsigned int entries)
197{
198 if (likely(entries == 0))
199 asm volatile("lldt %w0"::"q" (0));
200 else {
201 unsigned cpu = smp_processor_id();
202 ldt_desc ldt;
203
204 set_tssldt_descriptor(&ldt, (unsigned long)addr, DESC_LDT,
205 entries * LDT_ENTRY_SIZE - 1);
206 write_gdt_entry(get_cpu_gdt_table(cpu), GDT_ENTRY_LDT,
207 &ldt, DESC_LDT);
208 asm volatile("lldt %w0"::"q" (GDT_ENTRY_LDT*8));
209 }
210}
211
212static inline void native_load_tr_desc(void)
213{
214 asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));
215}
216
217static inline void native_load_gdt(const struct desc_ptr *dtr)
218{
219 asm volatile("lgdt %0"::"m" (*dtr));
220}
221
222static inline void native_load_idt(const struct desc_ptr *dtr)
223{
224 asm volatile("lidt %0"::"m" (*dtr));
225}
226
227static inline void native_store_gdt(struct desc_ptr *dtr)
228{
229 asm volatile("sgdt %0":"=m" (*dtr));
230}
231
232static inline void native_store_idt(struct desc_ptr *dtr)
233{
234 asm volatile("sidt %0":"=m" (*dtr));
235}
236
237static inline unsigned long native_store_tr(void)
238{
239 unsigned long tr;
240 asm volatile("str %0":"=r" (tr));
241 return tr;
242}
243
244static inline void native_load_tls(struct thread_struct *t, unsigned int cpu)
245{
246 unsigned int i;
247 struct desc_struct *gdt = get_cpu_gdt_table(cpu);
248
249 for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++)
250 gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i];
251}
252
253#define _LDT_empty(info) \
254 ((info)->base_addr == 0 && \
255 (info)->limit == 0 && \
256 (info)->contents == 0 && \
257 (info)->read_exec_only == 1 && \
258 (info)->seg_32bit == 0 && \
259 (info)->limit_in_pages == 0 && \
260 (info)->seg_not_present == 1 && \
261 (info)->useable == 0)
262
263#ifdef CONFIG_X86_64
264#define LDT_empty(info) (_LDT_empty(info) && ((info)->lm == 0))
265#else
266#define LDT_empty(info) (_LDT_empty(info))
267#endif
268
269static inline void clear_LDT(void)
270{
271 set_ldt(NULL, 0);
272}
273
274/*
275 * load one particular LDT into the current CPU
276 */
277static inline void load_LDT_nolock(mm_context_t *pc)
278{
279 set_ldt(pc->ldt, pc->size);
280}
281
282static inline void load_LDT(mm_context_t *pc)
283{
284 preempt_disable();
285 load_LDT_nolock(pc);
286 preempt_enable();
287}
288
289static inline unsigned long get_desc_base(const struct desc_struct *desc)
290{
291 return desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24);
292}
293
294static inline unsigned long get_desc_limit(const struct desc_struct *desc)
295{
296 return desc->limit0 | (desc->limit << 16);
297}
298
299static inline void _set_gate(int gate, unsigned type, void *addr,
300 unsigned dpl, unsigned ist, unsigned seg)
301{
302 gate_desc s;
303 pack_gate(&s, type, (unsigned long)addr, dpl, ist, seg);
304 /*
305 * does not need to be atomic because it is only done once at
306 * setup time
307 */
308 write_idt_entry(idt_table, gate, &s);
309}
310
311/*
312 * This needs to use 'idt_table' rather than 'idt', and
313 * thus use the _nonmapped_ version of the IDT, as the
314 * Pentium F0 0F bugfix can have resulted in the mapped
315 * IDT being write-protected.
316 */
317static inline void set_intr_gate(unsigned int n, void *addr)
318{
319 BUG_ON((unsigned)n > 0xFF);
320 _set_gate(n, GATE_INTERRUPT, addr, 0, 0, __KERNEL_CS);
321}
322
323#define SYS_VECTOR_FREE 0
324#define SYS_VECTOR_ALLOCED 1
325
326extern int first_system_vector;
327extern char system_vectors[];
328
329static inline void alloc_system_vector(int vector)
330{
331 if (system_vectors[vector] == SYS_VECTOR_FREE) {
332 system_vectors[vector] = SYS_VECTOR_ALLOCED;
333 if (first_system_vector > vector)
334 first_system_vector = vector;
335 } else
336 BUG();
337}
338
339static inline void alloc_intr_gate(unsigned int n, void *addr)
340{
341 alloc_system_vector(n);
342 set_intr_gate(n, addr);
343}
344
345/*
346 * This routine sets up an interrupt gate at directory privilege level 3.
347 */
348static inline void set_system_intr_gate(unsigned int n, void *addr)
349{
350 BUG_ON((unsigned)n > 0xFF);
351 _set_gate(n, GATE_INTERRUPT, addr, 0x3, 0, __KERNEL_CS);
352}
353
354static inline void set_system_trap_gate(unsigned int n, void *addr)
355{
356 BUG_ON((unsigned)n > 0xFF);
357 _set_gate(n, GATE_TRAP, addr, 0x3, 0, __KERNEL_CS);
358}
359
360static inline void set_trap_gate(unsigned int n, void *addr)
361{
362 BUG_ON((unsigned)n > 0xFF);
363 _set_gate(n, GATE_TRAP, addr, 0, 0, __KERNEL_CS);
364}
365
366static inline void set_task_gate(unsigned int n, unsigned int gdt_entry)
367{
368 BUG_ON((unsigned)n > 0xFF);
369 _set_gate(n, GATE_TASK, (void *)0, 0, 0, (gdt_entry<<3));
370}
371
372static inline void set_intr_gate_ist(int n, void *addr, unsigned ist)
373{
374 BUG_ON((unsigned)n > 0xFF);
375 _set_gate(n, GATE_INTERRUPT, addr, 0, ist, __KERNEL_CS);
376}
377
378static inline void set_system_intr_gate_ist(int n, void *addr, unsigned ist)
379{
380 BUG_ON((unsigned)n > 0xFF);
381 _set_gate(n, GATE_INTERRUPT, addr, 0x3, ist, __KERNEL_CS);
382}
383
384#else
385/*
386 * GET_DESC_BASE reads the descriptor base of the specified segment.
387 *
388 * Args:
389 * idx - descriptor index
390 * gdt - GDT pointer
391 * base - 32bit register to which the base will be written
392 * lo_w - lo word of the "base" register
393 * lo_b - lo byte of the "base" register
394 * hi_b - hi byte of the low word of the "base" register
395 *
396 * Example:
397 * GET_DESC_BASE(GDT_ENTRY_ESPFIX_SS, %ebx, %eax, %ax, %al, %ah)
398 * Will read the base address of GDT_ENTRY_ESPFIX_SS and put it into %eax.
399 */
400#define GET_DESC_BASE(idx, gdt, base, lo_w, lo_b, hi_b) \
401 movb idx * 8 + 4(gdt), lo_b; \
402 movb idx * 8 + 7(gdt), hi_b; \
403 shll $16, base; \
404 movw idx * 8 + 2(gdt), lo_w;
405
406
407#endif /* __ASSEMBLY__ */
408
409#endif /* ASM_X86__DESC_H */
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