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-rw-r--r--include/asm-mips/cpu-info.h4
-rw-r--r--include/asm-mips/gic.h4
-rw-r--r--include/asm-mips/lasat/serial.h4
-rw-r--r--include/asm-mips/mach-au1x00/au1000.h1
-rw-r--r--include/asm-mips/pgtable-bits.h2
5 files changed, 7 insertions, 8 deletions
diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h
index 0c5a358863f..2de73dbb2e9 100644
--- a/include/asm-mips/cpu-info.h
+++ b/include/asm-mips/cpu-info.h
@@ -56,7 +56,7 @@ struct cpuinfo_mips {
56 struct cache_desc tcache; /* Tertiary/split secondary cache */ 56 struct cache_desc tcache; /* Tertiary/split secondary cache */
57 int srsets; /* Shadow register sets */ 57 int srsets; /* Shadow register sets */
58 int core; /* physical core number */ 58 int core; /* physical core number */
59#if defined(CONFIG_MIPS_MT_SMTC) 59#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
60 /* 60 /*
61 * In the MIPS MT "SMTC" model, each TC is considered 61 * In the MIPS MT "SMTC" model, each TC is considered
62 * to be a "CPU" for the purposes of scheduling, but 62 * to be a "CPU" for the purposes of scheduling, but
@@ -64,7 +64,7 @@ struct cpuinfo_mips {
64 * to all TCs within the same VPE. 64 * to all TCs within the same VPE.
65 */ 65 */
66 int vpe_id; /* Virtual Processor number */ 66 int vpe_id; /* Virtual Processor number */
67#endif /* CONFIG_MIPS_MT */ 67#endif
68#ifdef CONFIG_MIPS_MT_SMTC 68#ifdef CONFIG_MIPS_MT_SMTC
69 int tc_id; /* Thread Context number */ 69 int tc_id; /* Thread Context number */
70#endif 70#endif
diff --git a/include/asm-mips/gic.h b/include/asm-mips/gic.h
index 3a492f225f0..954807d9d66 100644
--- a/include/asm-mips/gic.h
+++ b/include/asm-mips/gic.h
@@ -24,8 +24,8 @@
24 24
25#define MSK(n) ((1 << (n)) - 1) 25#define MSK(n) ((1 << (n)) - 1)
26#define REG32(addr) (*(volatile unsigned int *) (addr)) 26#define REG32(addr) (*(volatile unsigned int *) (addr))
27#define REG(base, offs) REG32((unsigned int)(base) + offs##_##OFS) 27#define REG(base, offs) REG32((unsigned long)(base) + offs##_##OFS)
28#define REGP(base, phys) REG32((unsigned int)(base) + (phys)) 28#define REGP(base, phys) REG32((unsigned long)(base) + (phys))
29 29
30/* Accessors */ 30/* Accessors */
31#define GIC_REG(segment, offset) \ 31#define GIC_REG(segment, offset) \
diff --git a/include/asm-mips/lasat/serial.h b/include/asm-mips/lasat/serial.h
index bafe68b1061..1c37d70579b 100644
--- a/include/asm-mips/lasat/serial.h
+++ b/include/asm-mips/lasat/serial.h
@@ -4,10 +4,10 @@
4#define LASAT_BASE_BAUD_100 (7372800 / 16) 4#define LASAT_BASE_BAUD_100 (7372800 / 16)
5#define LASAT_UART_REGS_BASE_100 0x1c8b0000 5#define LASAT_UART_REGS_BASE_100 0x1c8b0000
6#define LASAT_UART_REGS_SHIFT_100 2 6#define LASAT_UART_REGS_SHIFT_100 2
7#define LASATINT_UART_100 8 7#define LASATINT_UART_100 16
8 8
9/* * LASAT 200 boards serial configuration */ 9/* * LASAT 200 boards serial configuration */
10#define LASAT_BASE_BAUD_200 (100000000 / 16 / 12) 10#define LASAT_BASE_BAUD_200 (100000000 / 16 / 12)
11#define LASAT_UART_REGS_BASE_200 (Vrc5074_PHYS_BASE + 0x0300) 11#define LASAT_UART_REGS_BASE_200 (Vrc5074_PHYS_BASE + 0x0300)
12#define LASAT_UART_REGS_SHIFT_200 3 12#define LASAT_UART_REGS_SHIFT_200 3
13#define LASATINT_UART_200 13 13#define LASATINT_UART_200 21
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h
index 1b5064dac00..0d302bad449 100644
--- a/include/asm-mips/mach-au1x00/au1000.h
+++ b/include/asm-mips/mach-au1x00/au1000.h
@@ -615,6 +615,7 @@ enum soc_au1500_ints {
615 AU1000_RTC_MATCH1_INT, 615 AU1000_RTC_MATCH1_INT,
616 AU1000_RTC_MATCH2_INT, 616 AU1000_RTC_MATCH2_INT,
617 AU1500_PCI_ERR_INT, 617 AU1500_PCI_ERR_INT,
618 AU1500_RESERVED_INT,
618 AU1000_USB_DEV_REQ_INT, 619 AU1000_USB_DEV_REQ_INT,
619 AU1000_USB_DEV_SUS_INT, 620 AU1000_USB_DEV_SUS_INT,
620 AU1000_USB_HOST_INT, 621 AU1000_USB_HOST_INT,
diff --git a/include/asm-mips/pgtable-bits.h b/include/asm-mips/pgtable-bits.h
index 60e2f9338fc..51b34a48c84 100644
--- a/include/asm-mips/pgtable-bits.h
+++ b/include/asm-mips/pgtable-bits.h
@@ -134,6 +134,4 @@
134 134
135#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) 135#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK)
136 136
137#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT>>_CACHE_SHIFT)
138
139#endif /* _ASM_PGTABLE_BITS_H */ 137#endif /* _ASM_PGTABLE_BITS_H */