1 files changed, 62 insertions, 0 deletions
diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h
index d2808edfd4e..22361d5e3bf 100644
--- a/include/asm-mips/war.h
+++ b/include/asm-mips/war.h
@@ -4,6 +4,7 @@
 * for more details.
 *
 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle
+ * Copyright (C) 2007  Maciej W. Rozycki
 */
 #ifndef _ASM_WAR_H
 #define _ASM_WAR_H
@@ -11,6 +12,67 @@
 #include <war.h>
 /*
+ * Work around certain R4000 CPU errata (as implemented by GCC):
+ *
+ * - A double-word or a variable shift may give an incorrect result
+ *   if executed immediately after starting an integer division:
+ *   "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
+ *   erratum #28
+ *   "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
+ *   #19
+ *
+ * - A double-word or a variable shift may give an incorrect result
+ *   if executed while an integer multiplication is in progress:
+ *   "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
+ *   errata #16 & #28
+ *
+ * - An integer division may give an incorrect result if started in
+ *   a delay slot of a taken branch or a jump:
+ *   "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
+ *   erratum #52
+ */
+#ifdef CONFIG_CPU_R4000_WORKAROUNDS
+#define R4000_WAR 1
+#else
+#define R4000_WAR 0
+#endif
+/*
+ * Work around certain R4400 CPU errata (as implemented by GCC):
+ *
+ * - A double-word or a variable shift may give an incorrect result
+ *   if executed immediately after starting an integer division:
+ *   "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10
+ *   "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
+ */
+#ifdef CONFIG_CPU_R4400_WORKAROUNDS
+#define R4400_WAR 1
+#else
+#define R4400_WAR 0
+#endif
+/*
+ * Work around the "daddi" and "daddiu" CPU errata:
+ *
+ * - The `daddi' instruction fails to trap on overflow.
+ *   "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
+ *   erratum #23
+ *
+ * - The `daddiu' instruction can produce an incorrect result.
+ *   "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
+ *   erratum #41
+ *   "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
+ *   #15
+ *   "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7
+ *   "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
+ */
+#ifdef CONFIG_CPU_DADDI_WORKAROUNDS
+#define DADDI_WAR 1
+#else
+#define DADDI_WAR 0
+#endif
+/*
 * Another R4600 erratum.  Due to the lack of errata information the exact
 * technical details aren't known.  I've experimentally found that disabling
 * interrupts during indexed I-cache flushes seems to be sufficient to deal

diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h index d2808edfd4e..22361d5e3bf 100644 --- a/include/asm-mips/war.h +++ b/include/asm-mips/war.h
@@ -4,6 +4,7 @@
4	* for more details.	4	* for more details.
5	*	5	*
6	* Copyright (C) 2002, 2004, 2007 by Ralf Baechle	6	* Copyright (C) 2002, 2004, 2007 by Ralf Baechle
		7	* Copyright (C) 2007 Maciej W. Rozycki
7	*/	8	*/
8	#ifndef _ASM_WAR_H	9	#ifndef _ASM_WAR_H
9	#define _ASM_WAR_H	10	#define _ASM_WAR_H
@@ -11,6 +12,67 @@
11	#include <war.h>	12	#include <war.h>
12		13
13	/*	14	/*
		15	* Work around certain R4000 CPU errata (as implemented by GCC):
		16	*
		17	* - A double-word or a variable shift may give an incorrect result
		18	* if executed immediately after starting an integer division:
		19	* "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
		20	* erratum #28
		21	* "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
		22	* #19
		23	*
		24	* - A double-word or a variable shift may give an incorrect result
		25	* if executed while an integer multiplication is in progress:
		26	* "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
		27	* errata #16 & #28
		28	*
		29	* - An integer division may give an incorrect result if started in
		30	* a delay slot of a taken branch or a jump:
		31	* "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
		32	* erratum #52
		33	*/
		34	#ifdef CONFIG_CPU_R4000_WORKAROUNDS
		35	#define R4000_WAR 1
		36	#else
		37	#define R4000_WAR 0
		38	#endif
		39
		40	/*
		41	* Work around certain R4400 CPU errata (as implemented by GCC):
		42	*
		43	* - A double-word or a variable shift may give an incorrect result
		44	* if executed immediately after starting an integer division:
		45	* "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10
		46	* "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
		47	*/
		48	#ifdef CONFIG_CPU_R4400_WORKAROUNDS
		49	#define R4400_WAR 1
		50	#else
		51	#define R4400_WAR 0
		52	#endif
		53
		54	/*
		55	* Work around the "daddi" and "daddiu" CPU errata:
		56	*
		57	* - The `daddi' instruction fails to trap on overflow.
		58	* "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
		59	* erratum #23
		60	*
		61	* - The `daddiu' instruction can produce an incorrect result.
		62	* "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
		63	* erratum #41
		64	* "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
		65	* #15
		66	* "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7
		67	* "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
		68	*/
		69	#ifdef CONFIG_CPU_DADDI_WORKAROUNDS
		70	#define DADDI_WAR 1
		71	#else
		72	#define DADDI_WAR 0
		73	#endif
		74
		75	/*
14	* Another R4600 erratum. Due to the lack of errata information the exact	76	* Another R4600 erratum. Due to the lack of errata information the exact
15	* technical details aren't known. I've experimentally found that disabling	77	* technical details aren't known. I've experimentally found that disabling
16	* interrupts during indexed I-cache flushes seems to be sufficient to deal	78	* interrupts during indexed I-cache flushes seems to be sufficient to deal