diff options
Diffstat (limited to 'include/asm-mips/sgi/hpc3.h')
| -rw-r--r-- | include/asm-mips/sgi/hpc3.h | 40 |
1 files changed, 20 insertions, 20 deletions
diff --git a/include/asm-mips/sgi/hpc3.h b/include/asm-mips/sgi/hpc3.h index ac3dfc7af5b..fcec52bafb2 100644 --- a/include/asm-mips/sgi/hpc3.h +++ b/include/asm-mips/sgi/hpc3.h | |||
| @@ -128,26 +128,26 @@ struct hpc3_ethregs { | |||
| 128 | volatile u32 rx_gfptr; /* current GIO fifo ptr */ | 128 | volatile u32 rx_gfptr; /* current GIO fifo ptr */ |
| 129 | volatile u32 rx_dfptr; /* current device fifo ptr */ | 129 | volatile u32 rx_dfptr; /* current device fifo ptr */ |
| 130 | u32 _unused1; /* padding */ | 130 | u32 _unused1; /* padding */ |
| 131 | volatile u32 rx_reset; /* reset register */ | 131 | volatile u32 reset; /* reset register */ |
| 132 | #define HPC3_ERXRST_CRESET 0x1 /* Reset dma channel and external controller */ | 132 | #define HPC3_ERST_CRESET 0x1 /* Reset dma channel and external controller */ |
| 133 | #define HPC3_ERXRST_CLRIRQ 0x2 /* Clear channel interrupt */ | 133 | #define HPC3_ERST_CLRIRQ 0x2 /* Clear channel interrupt */ |
| 134 | #define HPC3_ERXRST_LBACK 0x4 /* Enable diagnostic loopback mode of Seeq8003 */ | 134 | #define HPC3_ERST_LBACK 0x4 /* Enable diagnostic loopback mode of Seeq8003 */ |
| 135 | 135 | ||
| 136 | volatile u32 rx_dconfig; /* DMA configuration register */ | 136 | volatile u32 dconfig; /* DMA configuration register */ |
| 137 | #define HPC3_ERXDCFG_D1 0x0000f /* Cycles to spend in D1 state for PIO */ | 137 | #define HPC3_EDCFG_D1 0x0000f /* Cycles to spend in D1 state for PIO */ |
| 138 | #define HPC3_ERXDCFG_D2 0x000f0 /* Cycles to spend in D2 state for PIO */ | 138 | #define HPC3_EDCFG_D2 0x000f0 /* Cycles to spend in D2 state for PIO */ |
| 139 | #define HPC3_ERXDCFG_D3 0x00f00 /* Cycles to spend in D3 state for PIO */ | 139 | #define HPC3_EDCFG_D3 0x00f00 /* Cycles to spend in D3 state for PIO */ |
| 140 | #define HPC3_ERXDCFG_WCTRL 0x01000 /* Enable writes of desc into ex ctrl port */ | 140 | #define HPC3_EDCFG_WCTRL 0x01000 /* Enable writes of desc into ex ctrl port */ |
| 141 | #define HPC3_ERXDCFG_FRXDC 0x02000 /* Clear eop stat bits upon rxdc, hw seeq fix */ | 141 | #define HPC3_EDCFG_FRXDC 0x02000 /* Clear eop stat bits upon rxdc, hw seeq fix */ |
| 142 | #define HPC3_ERXDCFG_FEOP 0x04000 /* Bad packet marker timeout enable */ | 142 | #define HPC3_EDCFG_FEOP 0x04000 /* Bad packet marker timeout enable */ |
| 143 | #define HPC3_ERXDCFG_FIRQ 0x08000 /* Another bad packet timeout enable */ | 143 | #define HPC3_EDCFG_FIRQ 0x08000 /* Another bad packet timeout enable */ |
| 144 | #define HPC3_ERXDCFG_PTO 0x30000 /* Programmed timeout value for above two */ | 144 | #define HPC3_EDCFG_PTO 0x30000 /* Programmed timeout value for above two */ |
| 145 | 145 | ||
| 146 | volatile u32 rx_pconfig; /* PIO configuration register */ | 146 | volatile u32 pconfig; /* PIO configuration register */ |
| 147 | #define HPC3_ERXPCFG_P1 0x000f /* Cycles to spend in P1 state for PIO */ | 147 | #define HPC3_EPCFG_P1 0x000f /* Cycles to spend in P1 state for PIO */ |
| 148 | #define HPC3_ERXPCFG_P2 0x00f0 /* Cycles to spend in P2 state for PIO */ | 148 | #define HPC3_EPCFG_P2 0x00f0 /* Cycles to spend in P2 state for PIO */ |
| 149 | #define HPC3_ERXPCFG_P3 0x0f00 /* Cycles to spend in P3 state for PIO */ | 149 | #define HPC3_EPCFG_P3 0x0f00 /* Cycles to spend in P3 state for PIO */ |
| 150 | #define HPC3_ERXPCFG_TST 0x1000 /* Diagnistic ram test feature bit */ | 150 | #define HPC3_EPCFG_TST 0x1000 /* Diagnistic ram test feature bit */ |
| 151 | 151 | ||
| 152 | u32 _unused2[0x1000/4 - 8]; /* padding */ | 152 | u32 _unused2[0x1000/4 - 8]; /* padding */ |
| 153 | 153 | ||