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diff --git a/include/asm-arm/arch-s3c2410/regs-udc.h b/include/asm-arm/arch-s3c2410/regs-udc.h
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1/* linux/include/asm/arch-s3c2410/regs-udc.h
2 *
3 * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
4 *
5 * This include file is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * Changelog:
11 * 01-08-2004 Initial creation
12 * 12-09-2004 Cleanup for submission
13 * 24-10-2004 Fixed S3C2410_UDC_MAXP_REG definition
14 * 10-03-2005 Changed S3C2410_VA to S3C24XX_VA
15 */
16
17#ifndef __ASM_ARCH_REGS_UDC_H
18#define __ASM_ARCH_REGS_UDC_H
19
20
21#define S3C2410_USBDREG(x) ((x) + S3C24XX_VA_USBDEV)
22
23#define S3C2410_UDC_FUNC_ADDR_REG S3C2410_USBDREG(0x0140)
24#define S3C2410_UDC_PWR_REG S3C2410_USBDREG(0x0144)
25#define S3C2410_UDC_EP_INT_REG S3C2410_USBDREG(0x0148)
26
27#define S3C2410_UDC_USB_INT_REG S3C2410_USBDREG(0x0158)
28#define S3C2410_UDC_EP_INT_EN_REG S3C2410_USBDREG(0x015c)
29
30#define S3C2410_UDC_USB_INT_EN_REG S3C2410_USBDREG(0x016c)
31
32#define S3C2410_UDC_FRAME_NUM1_REG S3C2410_USBDREG(0x0170)
33#define S3C2410_UDC_FRAME_NUM2_REG S3C2410_USBDREG(0x0174)
34
35#define S3C2410_UDC_EP0_FIFO_REG S3C2410_USBDREG(0x01c0)
36#define S3C2410_UDC_EP1_FIFO_REG S3C2410_USBDREG(0x01c4)
37#define S3C2410_UDC_EP2_FIFO_REG S3C2410_USBDREG(0x01c8)
38#define S3C2410_UDC_EP3_FIFO_REG S3C2410_USBDREG(0x01cc)
39#define S3C2410_UDC_EP4_FIFO_REG S3C2410_USBDREG(0x01d0)
40
41#define S3C2410_UDC_EP1_DMA_CON S3C2410_USBDREG(0x0200)
42#define S3C2410_UDC_EP1_DMA_UNIT S3C2410_USBDREG(0x0204)
43#define S3C2410_UDC_EP1_DMA_FIFO S3C2410_USBDREG(0x0208)
44#define S3C2410_UDC_EP1_DMA_TTC_L S3C2410_USBDREG(0x020c)
45#define S3C2410_UDC_EP1_DMA_TTC_M S3C2410_USBDREG(0x0210)
46#define S3C2410_UDC_EP1_DMA_TTC_H S3C2410_USBDREG(0x0214)
47
48#define S3C2410_UDC_EP2_DMA_CON S3C2410_USBDREG(0x0218)
49#define S3C2410_UDC_EP2_DMA_UNIT S3C2410_USBDREG(0x021c)
50#define S3C2410_UDC_EP2_DMA_FIFO S3C2410_USBDREG(0x0220)
51#define S3C2410_UDC_EP2_DMA_TTC_L S3C2410_USBDREG(0x0224)
52#define S3C2410_UDC_EP2_DMA_TTC_M S3C2410_USBDREG(0x0228)
53#define S3C2410_UDC_EP2_DMA_TTC_H S3C2410_USBDREG(0x022c)
54
55#define S3C2410_UDC_EP3_DMA_CON S3C2410_USBDREG(0x0240)
56#define S3C2410_UDC_EP3_DMA_UNIT S3C2410_USBDREG(0x0244)
57#define S3C2410_UDC_EP3_DMA_FIFO S3C2410_USBDREG(0x0248)
58#define S3C2410_UDC_EP3_DMA_TTC_L S3C2410_USBDREG(0x024c)
59#define S3C2410_UDC_EP3_DMA_TTC_M S3C2410_USBDREG(0x0250)
60#define S3C2410_UDC_EP3_DMA_TTC_H S3C2410_USBDREG(0x0254)
61
62#define S3C2410_UDC_EP4_DMA_CON S3C2410_USBDREG(0x0258)
63#define S3C2410_UDC_EP4_DMA_UNIT S3C2410_USBDREG(0x025c)
64#define S3C2410_UDC_EP4_DMA_FIFO S3C2410_USBDREG(0x0260)
65#define S3C2410_UDC_EP4_DMA_TTC_L S3C2410_USBDREG(0x0264)
66#define S3C2410_UDC_EP4_DMA_TTC_M S3C2410_USBDREG(0x0268)
67#define S3C2410_UDC_EP4_DMA_TTC_H S3C2410_USBDREG(0x026c)
68
69#define S3C2410_UDC_INDEX_REG S3C2410_USBDREG(0x0178)
70
71/* indexed registers */
72
73#define S3C2410_UDC_MAXP_REG S3C2410_USBDREG(0x0180)
74
75#define S3C2410_UDC_EP0_CSR_REG S3C2410_USBDREG(0x0184)
76
77#define S3C2410_UDC_IN_CSR1_REG S3C2410_USBDREG(0x0184)
78#define S3C2410_UDC_IN_CSR2_REG S3C2410_USBDREG(0x0188)
79
80#define S3C2410_UDC_OUT_CSR1_REG S3C2410_USBDREG(0x0190)
81#define S3C2410_UDC_OUT_CSR2_REG S3C2410_USBDREG(0x0194)
82#define S3C2410_UDC_OUT_FIFO_CNT1_REG S3C2410_USBDREG(0x0198)
83#define S3C2410_UDC_OUT_FIFO_CNT2_REG S3C2410_USBDREG(0x019c)
84
85
86
87#define S3C2410_UDC_PWR_ISOUP (1<<7) // R/W
88#define S3C2410_UDC_PWR_RESET (1<<3) // R
89#define S3C2410_UDC_PWR_RESUME (1<<2) // R/W
90#define S3C2410_UDC_PWR_SUSPEND (1<<1) // R
91#define S3C2410_UDC_PWR_ENSUSPEND (1<<0) // R/W
92
93#define S3C2410_UDC_PWR_DEFAULT 0x00
94
95#define S3C2410_UDC_INT_EP4 (1<<4) // R/W (clear only)
96#define S3C2410_UDC_INT_EP3 (1<<3) // R/W (clear only)
97#define S3C2410_UDC_INT_EP2 (1<<2) // R/W (clear only)
98#define S3C2410_UDC_INT_EP1 (1<<1) // R/W (clear only)
99#define S3C2410_UDC_INT_EP0 (1<<0) // R/W (clear only)
100
101#define S3C2410_UDC_USBINT_RESET (1<<2) // R/W (clear only)
102#define S3C2410_UDC_USBINT_RESUME (1<<1) // R/W (clear only)
103#define S3C2410_UDC_USBINT_SUSPEND (1<<0) // R/W (clear only)
104
105#define S3C2410_UDC_INTE_EP4 (1<<4) // R/W
106#define S3C2410_UDC_INTE_EP3 (1<<3) // R/W
107#define S3C2410_UDC_INTE_EP2 (1<<2) // R/W
108#define S3C2410_UDC_INTE_EP1 (1<<1) // R/W
109#define S3C2410_UDC_INTE_EP0 (1<<0) // R/W
110
111#define S3C2410_UDC_USBINTE_RESET (1<<2) // R/W
112#define S3C2410_UDC_USBINTE_SUSPEND (1<<0) // R/W
113
114
115#define S3C2410_UDC_INDEX_EP0 (0x00)
116#define S3C2410_UDC_INDEX_EP1 (0x01) // ??
117#define S3C2410_UDC_INDEX_EP2 (0x02) // ??
118#define S3C2410_UDC_INDEX_EP3 (0x03) // ??
119#define S3C2410_UDC_INDEX_EP4 (0x04) // ??
120
121#define S3C2410_UDC_ICSR1_CLRDT (1<<6) // R/W
122#define S3C2410_UDC_ICSR1_SENTSTL (1<<5) // R/W (clear only)
123#define S3C2410_UDC_ICSR1_SENDSTL (1<<4) // R/W
124#define S3C2410_UDC_ICSR1_FFLUSH (1<<3) // W (set only)
125#define S3C2410_UDC_ICSR1_UNDRUN (1<<2) // R/W (clear only)
126#define S3C2410_UDC_ICSR1_PKTRDY (1<<0) // R/W (set only)
127
128#define S3C2410_UDC_ICSR2_AUTOSET (1<<7) // R/W
129#define S3C2410_UDC_ICSR2_ISO (1<<6) // R/W
130#define S3C2410_UDC_ICSR2_MODEIN (1<<5) // R/W
131#define S3C2410_UDC_ICSR2_DMAIEN (1<<4) // R/W
132
133#define S3C2410_UDC_OCSR1_CLRDT (1<<7) // R/W
134#define S3C2410_UDC_OCSR1_SENTSTL (1<<6) // R/W (clear only)
135#define S3C2410_UDC_OCSR1_SENDSTL (1<<5) // R/W
136#define S3C2410_UDC_OCSR1_FFLUSH (1<<4) // R/W
137#define S3C2410_UDC_OCSR1_DERROR (1<<3) // R
138#define S3C2410_UDC_OCSR1_OVRRUN (1<<2) // R/W (clear only)
139#define S3C2410_UDC_OCSR1_PKTRDY (1<<0) // R/W (clear only)
140
141#define S3C2410_UDC_OCSR2_AUTOCLR (1<<7) // R/W
142#define S3C2410_UDC_OCSR2_ISO (1<<6) // R/W
143#define S3C2410_UDC_OCSR2_DMAIEN (1<<5) // R/W
144
145#define S3C2410_UDC_SETIX(x) \
146 __raw_writel(S3C2410_UDC_INDEX_ ## x, S3C2410_UDC_INDEX_REG);
147
148
149#define S3C2410_UDC_EP0_CSR_OPKRDY (1<<0)
150#define S3C2410_UDC_EP0_CSR_IPKRDY (1<<1)
151#define S3C2410_UDC_EP0_CSR_SENTSTL (1<<2)
152#define S3C2410_UDC_EP0_CSR_DE (1<<3)
153#define S3C2410_UDC_EP0_CSR_SE (1<<4)
154#define S3C2410_UDC_EP0_CSR_SENDSTL (1<<5)
155#define S3C2410_UDC_EP0_CSR_SOPKTRDY (1<<6)
156#define S3C2410_UDC_EP0_CSR_SSE (1<<7)
157
158#define S3C2410_UDC_MAXP_8 (1<<0)
159#define S3C2410_UDC_MAXP_16 (1<<1)
160#define S3C2410_UDC_MAXP_32 (1<<2)
161#define S3C2410_UDC_MAXP_64 (1<<3)
162
163
164#endif