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-rw-r--r--drivers/acpi/toshiba_acpi.c54
-rw-r--r--drivers/cdrom/cdrom.c16
-rw-r--r--drivers/char/cp437.uni12
-rw-r--r--drivers/char/vt.c2
-rw-r--r--drivers/i2c/busses/i2c-highlander.c4
-rw-r--r--drivers/i2c/busses/i2c-pmcmsp.c2
-rw-r--r--drivers/net/e1000e/ich8lan.c9
-rw-r--r--drivers/net/sungem.c144
-rw-r--r--drivers/pcmcia/bfin_cf_pcmcia.c2
-rw-r--r--drivers/scsi/device_handler/scsi_dh_hp_sw.c12
-rw-r--r--drivers/video/aty/radeon_accel.c295
-rw-r--r--drivers/video/aty/radeon_backlight.c2
-rw-r--r--drivers/video/aty/radeon_base.c46
-rw-r--r--drivers/video/aty/radeon_pm.c6
-rw-r--r--drivers/video/aty/radeonfb.h40
-rw-r--r--drivers/video/imxfb.c468
-rw-r--r--drivers/video/imxfb.h73
17 files changed, 542 insertions, 645 deletions
diff --git a/drivers/acpi/toshiba_acpi.c b/drivers/acpi/toshiba_acpi.c
index 25f531d892d..40e60fc2e59 100644
--- a/drivers/acpi/toshiba_acpi.c
+++ b/drivers/acpi/toshiba_acpi.c
@@ -824,32 +824,36 @@ static int __init toshiba_acpi_init(void)
824 toshiba_acpi_exit(); 824 toshiba_acpi_exit();
825 return -ENOMEM; 825 return -ENOMEM;
826 } 826 }
827 }
828 827
829 /* Register input device for kill switch */ 828 /* Register input device for kill switch */
830 toshiba_acpi.poll_dev = input_allocate_polled_device(); 829 toshiba_acpi.poll_dev = input_allocate_polled_device();
831 if (!toshiba_acpi.poll_dev) { 830 if (!toshiba_acpi.poll_dev) {
832 printk(MY_ERR "unable to allocate kill-switch input device\n"); 831 printk(MY_ERR
833 toshiba_acpi_exit(); 832 "unable to allocate kill-switch input device\n");
834 return -ENOMEM; 833 toshiba_acpi_exit();
835 } 834 return -ENOMEM;
836 toshiba_acpi.poll_dev->private = &toshiba_acpi; 835 }
837 toshiba_acpi.poll_dev->poll = bt_poll_rfkill; 836 toshiba_acpi.poll_dev->private = &toshiba_acpi;
838 toshiba_acpi.poll_dev->poll_interval = 1000; /* msecs */ 837 toshiba_acpi.poll_dev->poll = bt_poll_rfkill;
839 838 toshiba_acpi.poll_dev->poll_interval = 1000; /* msecs */
840 toshiba_acpi.poll_dev->input->name = toshiba_acpi.rfk_name; 839
841 toshiba_acpi.poll_dev->input->id.bustype = BUS_HOST; 840 toshiba_acpi.poll_dev->input->name = toshiba_acpi.rfk_name;
842 toshiba_acpi.poll_dev->input->id.vendor = 0x0930; /* Toshiba USB ID */ 841 toshiba_acpi.poll_dev->input->id.bustype = BUS_HOST;
843 set_bit(EV_SW, toshiba_acpi.poll_dev->input->evbit); 842 /* Toshiba USB ID */
844 set_bit(SW_RFKILL_ALL, toshiba_acpi.poll_dev->input->swbit); 843 toshiba_acpi.poll_dev->input->id.vendor = 0x0930;
845 input_report_switch(toshiba_acpi.poll_dev->input, SW_RFKILL_ALL, TRUE); 844 set_bit(EV_SW, toshiba_acpi.poll_dev->input->evbit);
846 input_sync(toshiba_acpi.poll_dev->input); 845 set_bit(SW_RFKILL_ALL, toshiba_acpi.poll_dev->input->swbit);
847 846 input_report_switch(toshiba_acpi.poll_dev->input,
848 ret = input_register_polled_device(toshiba_acpi.poll_dev); 847 SW_RFKILL_ALL, TRUE);
849 if (ret) { 848 input_sync(toshiba_acpi.poll_dev->input);
850 printk(MY_ERR "unable to register kill-switch input device\n"); 849
851 toshiba_acpi_exit(); 850 ret = input_register_polled_device(toshiba_acpi.poll_dev);
852 return ret; 851 if (ret) {
852 printk(MY_ERR
853 "unable to register kill-switch input device\n");
854 toshiba_acpi_exit();
855 return ret;
856 }
853 } 857 }
854 858
855 return 0; 859 return 0;
diff --git a/drivers/cdrom/cdrom.c b/drivers/cdrom/cdrom.c
index d16b02423d6..7d2e91cccb1 100644
--- a/drivers/cdrom/cdrom.c
+++ b/drivers/cdrom/cdrom.c
@@ -2081,10 +2081,6 @@ static int cdrom_read_cdda_bpc(struct cdrom_device_info *cdi, __u8 __user *ubuf,
2081 if (!q) 2081 if (!q)
2082 return -ENXIO; 2082 return -ENXIO;
2083 2083
2084 rq = blk_get_request(q, READ, GFP_KERNEL);
2085 if (!rq)
2086 return -ENOMEM;
2087
2088 cdi->last_sense = 0; 2084 cdi->last_sense = 0;
2089 2085
2090 while (nframes) { 2086 while (nframes) {
@@ -2096,9 +2092,17 @@ static int cdrom_read_cdda_bpc(struct cdrom_device_info *cdi, __u8 __user *ubuf,
2096 2092
2097 len = nr * CD_FRAMESIZE_RAW; 2093 len = nr * CD_FRAMESIZE_RAW;
2098 2094
2095 rq = blk_get_request(q, READ, GFP_KERNEL);
2096 if (!rq) {
2097 ret = -ENOMEM;
2098 break;
2099 }
2100
2099 ret = blk_rq_map_user(q, rq, NULL, ubuf, len, GFP_KERNEL); 2101 ret = blk_rq_map_user(q, rq, NULL, ubuf, len, GFP_KERNEL);
2100 if (ret) 2102 if (ret) {
2103 blk_put_request(rq);
2101 break; 2104 break;
2105 }
2102 2106
2103 rq->cmd[0] = GPCMD_READ_CD; 2107 rq->cmd[0] = GPCMD_READ_CD;
2104 rq->cmd[1] = 1 << 2; 2108 rq->cmd[1] = 1 << 2;
@@ -2124,6 +2128,7 @@ static int cdrom_read_cdda_bpc(struct cdrom_device_info *cdi, __u8 __user *ubuf,
2124 2128
2125 if (blk_rq_unmap_user(bio)) 2129 if (blk_rq_unmap_user(bio))
2126 ret = -EFAULT; 2130 ret = -EFAULT;
2131 blk_put_request(rq);
2127 2132
2128 if (ret) 2133 if (ret)
2129 break; 2134 break;
@@ -2133,7 +2138,6 @@ static int cdrom_read_cdda_bpc(struct cdrom_device_info *cdi, __u8 __user *ubuf,
2133 ubuf += len; 2138 ubuf += len;
2134 } 2139 }
2135 2140
2136 blk_put_request(rq);
2137 return ret; 2141 return ret;
2138} 2142}
2139 2143
diff --git a/drivers/char/cp437.uni b/drivers/char/cp437.uni
index 1f06889a96b..bc6163484f6 100644
--- a/drivers/char/cp437.uni
+++ b/drivers/char/cp437.uni
@@ -27,7 +27,7 @@
270x0c U+2640 270x0c U+2640
280x0d U+266a 280x0d U+266a
290x0e U+266b 290x0e U+266b
300x0f U+263c 300x0f U+263c U+00a4
310x10 U+25b6 U+25ba 310x10 U+25b6 U+25ba
320x11 U+25c0 U+25c4 320x11 U+25c0 U+25c4
330x12 U+2195 330x12 U+2195
@@ -55,7 +55,7 @@
550x24 U+0024 550x24 U+0024
560x25 U+0025 560x25 U+0025
570x26 U+0026 570x26 U+0026
580x27 U+0027 580x27 U+0027 U+00b4
590x28 U+0028 590x28 U+0028
600x29 U+0029 600x29 U+0029
610x2a U+002a 610x2a U+002a
@@ -84,7 +84,7 @@
840x41 U+0041 U+00c0 U+00c1 U+00c2 U+00c3 840x41 U+0041 U+00c0 U+00c1 U+00c2 U+00c3
850x42 U+0042 850x42 U+0042
860x43 U+0043 U+00a9 860x43 U+0043 U+00a9
870x44 U+0044 870x44 U+0044 U+00d0
880x45 U+0045 U+00c8 U+00ca U+00cb 880x45 U+0045 U+00c8 U+00ca U+00cb
890x46 U+0046 890x46 U+0046
900x47 U+0047 900x47 U+0047
@@ -140,7 +140,7 @@
1400x79 U+0079 U+00fd 1400x79 U+0079 U+00fd
1410x7a U+007a 1410x7a U+007a
1420x7b U+007b 1420x7b U+007b
1430x7c U+007c U+00a5 1430x7c U+007c U+00a6
1440x7d U+007d 1440x7d U+007d
1450x7e U+007e 1450x7e U+007e
146# 146#
@@ -263,10 +263,10 @@
2630xe8 U+03a6 U+00d8 2630xe8 U+03a6 U+00d8
2640xe9 U+0398 2640xe9 U+0398
2650xea U+03a9 U+2126 2650xea U+03a9 U+2126
2660xeb U+03b4 2660xeb U+03b4 U+00f0
2670xec U+221e 2670xec U+221e
2680xed U+03c6 U+00f8 2680xed U+03c6 U+00f8
2690xee U+03b5 2690xee U+03b5 U+2208
2700xef U+2229 2700xef U+2229
2710xf0 U+2261 2710xf0 U+2261
2720xf1 U+00b1 2720xf1 U+00b1
diff --git a/drivers/char/vt.c b/drivers/char/vt.c
index a5af6072e2b..008176edbd6 100644
--- a/drivers/char/vt.c
+++ b/drivers/char/vt.c
@@ -2274,7 +2274,7 @@ rescan_last_byte:
2274 continue; /* nothing to display */ 2274 continue; /* nothing to display */
2275 } 2275 }
2276 /* Glyph not found */ 2276 /* Glyph not found */
2277 if ((!(vc->vc_utf && !vc->vc_disp_ctrl) || c < 128) && !(c & ~charmask)) { 2277 if ((!(vc->vc_utf && !vc->vc_disp_ctrl) && c < 128) && !(c & ~charmask)) {
2278 /* In legacy mode use the glyph we get by a 1:1 mapping. 2278 /* In legacy mode use the glyph we get by a 1:1 mapping.
2279 This would make absolutely no sense with Unicode in mind, 2279 This would make absolutely no sense with Unicode in mind,
2280 but do this for ASCII characters since a font may lack 2280 but do this for ASCII characters since a font may lack
diff --git a/drivers/i2c/busses/i2c-highlander.c b/drivers/i2c/busses/i2c-highlander.c
index f4d22ae9d29..e5a8dae4a28 100644
--- a/drivers/i2c/busses/i2c-highlander.c
+++ b/drivers/i2c/busses/i2c-highlander.c
@@ -92,7 +92,7 @@ static void highlander_i2c_setup(struct highlander_i2c_dev *dev)
92static void smbus_write_data(u8 *src, u16 *dst, int len) 92static void smbus_write_data(u8 *src, u16 *dst, int len)
93{ 93{
94 for (; len > 1; len -= 2) { 94 for (; len > 1; len -= 2) {
95 *dst++ = be16_to_cpup((u16 *)src); 95 *dst++ = be16_to_cpup((__be16 *)src);
96 src += 2; 96 src += 2;
97 } 97 }
98 98
@@ -103,7 +103,7 @@ static void smbus_write_data(u8 *src, u16 *dst, int len)
103static void smbus_read_data(u16 *src, u8 *dst, int len) 103static void smbus_read_data(u16 *src, u8 *dst, int len)
104{ 104{
105 for (; len > 1; len -= 2) { 105 for (; len > 1; len -= 2) {
106 *(u16 *)dst = cpu_to_be16p(src++); 106 *(__be16 *)dst = cpu_to_be16p(src++);
107 dst += 2; 107 dst += 2;
108 } 108 }
109 109
diff --git a/drivers/i2c/busses/i2c-pmcmsp.c b/drivers/i2c/busses/i2c-pmcmsp.c
index dcf2045b522..0bdb2d7f057 100644
--- a/drivers/i2c/busses/i2c-pmcmsp.c
+++ b/drivers/i2c/busses/i2c-pmcmsp.c
@@ -486,7 +486,7 @@ static enum pmcmsptwi_xfer_result pmcmsptwi_xfer_cmd(
486 486
487 if (cmd->type == MSP_TWI_CMD_WRITE || 487 if (cmd->type == MSP_TWI_CMD_WRITE ||
488 cmd->type == MSP_TWI_CMD_WRITE_READ) { 488 cmd->type == MSP_TWI_CMD_WRITE_READ) {
489 __be64 tmp = cpu_to_be64p((u64 *)cmd->write_data); 489 u64 tmp = be64_to_cpup((__be64 *)cmd->write_data);
490 tmp >>= (MSP_MAX_BYTES_PER_RW - cmd->write_len) * 8; 490 tmp >>= (MSP_MAX_BYTES_PER_RW - cmd->write_len) * 8;
491 dev_dbg(&pmcmsptwi_adapter.dev, "Writing 0x%016llx\n", tmp); 491 dev_dbg(&pmcmsptwi_adapter.dev, "Writing 0x%016llx\n", tmp);
492 pmcmsptwi_writel(tmp & 0x00000000ffffffffLL, 492 pmcmsptwi_writel(tmp & 0x00000000ffffffffLL,
diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c
index 523b9716a54..d115a6d30f2 100644
--- a/drivers/net/e1000e/ich8lan.c
+++ b/drivers/net/e1000e/ich8lan.c
@@ -1893,12 +1893,17 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
1893 ctrl |= E1000_CTRL_PHY_RST; 1893 ctrl |= E1000_CTRL_PHY_RST;
1894 } 1894 }
1895 ret_val = e1000_acquire_swflag_ich8lan(hw); 1895 ret_val = e1000_acquire_swflag_ich8lan(hw);
1896 /* Whether or not the swflag was acquired, we need to reset the part */
1896 hw_dbg(hw, "Issuing a global reset to ich8lan"); 1897 hw_dbg(hw, "Issuing a global reset to ich8lan");
1897 ew32(CTRL, (ctrl | E1000_CTRL_RST)); 1898 ew32(CTRL, (ctrl | E1000_CTRL_RST));
1898 msleep(20); 1899 msleep(20);
1899 1900
1900 /* release the swflag because it is not reset by hardware reset */ 1901 if (!ret_val) {
1901 e1000_release_swflag_ich8lan(hw); 1902 /* release the swflag because it is not reset by
1903 * hardware reset
1904 */
1905 e1000_release_swflag_ich8lan(hw);
1906 }
1902 1907
1903 ret_val = e1000e_get_auto_rd_done(hw); 1908 ret_val = e1000e_get_auto_rd_done(hw);
1904 if (ret_val) { 1909 if (ret_val) {
diff --git a/drivers/net/sungem.c b/drivers/net/sungem.c
index 1349e419673..fed7eba65ea 100644
--- a/drivers/net/sungem.c
+++ b/drivers/net/sungem.c
@@ -1142,6 +1142,70 @@ static int gem_start_xmit(struct sk_buff *skb, struct net_device *dev)
1142 return NETDEV_TX_OK; 1142 return NETDEV_TX_OK;
1143} 1143}
1144 1144
1145static void gem_pcs_reset(struct gem *gp)
1146{
1147 int limit;
1148 u32 val;
1149
1150 /* Reset PCS unit. */
1151 val = readl(gp->regs + PCS_MIICTRL);
1152 val |= PCS_MIICTRL_RST;
1153 writel(val, gp->regs + PCS_MIICTRL);
1154
1155 limit = 32;
1156 while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) {
1157 udelay(100);
1158 if (limit-- <= 0)
1159 break;
1160 }
1161 if (limit <= 0)
1162 printk(KERN_WARNING "%s: PCS reset bit would not clear.\n",
1163 gp->dev->name);
1164}
1165
1166static void gem_pcs_reinit_adv(struct gem *gp)
1167{
1168 u32 val;
1169
1170 /* Make sure PCS is disabled while changing advertisement
1171 * configuration.
1172 */
1173 val = readl(gp->regs + PCS_CFG);
1174 val &= ~(PCS_CFG_ENABLE | PCS_CFG_TO);
1175 writel(val, gp->regs + PCS_CFG);
1176
1177 /* Advertise all capabilities except assymetric
1178 * pause.
1179 */
1180 val = readl(gp->regs + PCS_MIIADV);
1181 val |= (PCS_MIIADV_FD | PCS_MIIADV_HD |
1182 PCS_MIIADV_SP | PCS_MIIADV_AP);
1183 writel(val, gp->regs + PCS_MIIADV);
1184
1185 /* Enable and restart auto-negotiation, disable wrapback/loopback,
1186 * and re-enable PCS.
1187 */
1188 val = readl(gp->regs + PCS_MIICTRL);
1189 val |= (PCS_MIICTRL_RAN | PCS_MIICTRL_ANE);
1190 val &= ~PCS_MIICTRL_WB;
1191 writel(val, gp->regs + PCS_MIICTRL);
1192
1193 val = readl(gp->regs + PCS_CFG);
1194 val |= PCS_CFG_ENABLE;
1195 writel(val, gp->regs + PCS_CFG);
1196
1197 /* Make sure serialink loopback is off. The meaning
1198 * of this bit is logically inverted based upon whether
1199 * you are in Serialink or SERDES mode.
1200 */
1201 val = readl(gp->regs + PCS_SCTRL);
1202 if (gp->phy_type == phy_serialink)
1203 val &= ~PCS_SCTRL_LOOP;
1204 else
1205 val |= PCS_SCTRL_LOOP;
1206 writel(val, gp->regs + PCS_SCTRL);
1207}
1208
1145#define STOP_TRIES 32 1209#define STOP_TRIES 32
1146 1210
1147/* Must be invoked under gp->lock and gp->tx_lock. */ 1211/* Must be invoked under gp->lock and gp->tx_lock. */
@@ -1168,6 +1232,9 @@ static void gem_reset(struct gem *gp)
1168 1232
1169 if (limit <= 0) 1233 if (limit <= 0)
1170 printk(KERN_ERR "%s: SW reset is ghetto.\n", gp->dev->name); 1234 printk(KERN_ERR "%s: SW reset is ghetto.\n", gp->dev->name);
1235
1236 if (gp->phy_type == phy_serialink || gp->phy_type == phy_serdes)
1237 gem_pcs_reinit_adv(gp);
1171} 1238}
1172 1239
1173/* Must be invoked under gp->lock and gp->tx_lock. */ 1240/* Must be invoked under gp->lock and gp->tx_lock. */
@@ -1324,7 +1391,7 @@ static int gem_set_link_modes(struct gem *gp)
1324 gp->phy_type == phy_serdes) { 1391 gp->phy_type == phy_serdes) {
1325 u32 pcs_lpa = readl(gp->regs + PCS_MIILP); 1392 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1326 1393
1327 if (pcs_lpa & PCS_MIIADV_FD) 1394 if ((pcs_lpa & PCS_MIIADV_FD) || gp->phy_type == phy_serdes)
1328 full_duplex = 1; 1395 full_duplex = 1;
1329 speed = SPEED_1000; 1396 speed = SPEED_1000;
1330 } 1397 }
@@ -1488,6 +1555,9 @@ static void gem_link_timer(unsigned long data)
1488 val = readl(gp->regs + PCS_MIISTAT); 1555 val = readl(gp->regs + PCS_MIISTAT);
1489 1556
1490 if ((val & PCS_MIISTAT_LS) != 0) { 1557 if ((val & PCS_MIISTAT_LS) != 0) {
1558 if (gp->lstate == link_up)
1559 goto restart;
1560
1491 gp->lstate = link_up; 1561 gp->lstate = link_up;
1492 netif_carrier_on(gp->dev); 1562 netif_carrier_on(gp->dev);
1493 (void)gem_set_link_modes(gp); 1563 (void)gem_set_link_modes(gp);
@@ -1708,61 +1778,8 @@ static void gem_init_phy(struct gem *gp)
1708 if (gp->phy_mii.def && gp->phy_mii.def->ops->init) 1778 if (gp->phy_mii.def && gp->phy_mii.def->ops->init)
1709 gp->phy_mii.def->ops->init(&gp->phy_mii); 1779 gp->phy_mii.def->ops->init(&gp->phy_mii);
1710 } else { 1780 } else {
1711 u32 val; 1781 gem_pcs_reset(gp);
1712 int limit; 1782 gem_pcs_reinit_adv(gp);
1713
1714 /* Reset PCS unit. */
1715 val = readl(gp->regs + PCS_MIICTRL);
1716 val |= PCS_MIICTRL_RST;
1717 writel(val, gp->regs + PCS_MIICTRL);
1718
1719 limit = 32;
1720 while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) {
1721 udelay(100);
1722 if (limit-- <= 0)
1723 break;
1724 }
1725 if (limit <= 0)
1726 printk(KERN_WARNING "%s: PCS reset bit would not clear.\n",
1727 gp->dev->name);
1728
1729 /* Make sure PCS is disabled while changing advertisement
1730 * configuration.
1731 */
1732 val = readl(gp->regs + PCS_CFG);
1733 val &= ~(PCS_CFG_ENABLE | PCS_CFG_TO);
1734 writel(val, gp->regs + PCS_CFG);
1735
1736 /* Advertise all capabilities except assymetric
1737 * pause.
1738 */
1739 val = readl(gp->regs + PCS_MIIADV);
1740 val |= (PCS_MIIADV_FD | PCS_MIIADV_HD |
1741 PCS_MIIADV_SP | PCS_MIIADV_AP);
1742 writel(val, gp->regs + PCS_MIIADV);
1743
1744 /* Enable and restart auto-negotiation, disable wrapback/loopback,
1745 * and re-enable PCS.
1746 */
1747 val = readl(gp->regs + PCS_MIICTRL);
1748 val |= (PCS_MIICTRL_RAN | PCS_MIICTRL_ANE);
1749 val &= ~PCS_MIICTRL_WB;
1750 writel(val, gp->regs + PCS_MIICTRL);
1751
1752 val = readl(gp->regs + PCS_CFG);
1753 val |= PCS_CFG_ENABLE;
1754 writel(val, gp->regs + PCS_CFG);
1755
1756 /* Make sure serialink loopback is off. The meaning
1757 * of this bit is logically inverted based upon whether
1758 * you are in Serialink or SERDES mode.
1759 */
1760 val = readl(gp->regs + PCS_SCTRL);
1761 if (gp->phy_type == phy_serialink)
1762 val &= ~PCS_SCTRL_LOOP;
1763 else
1764 val |= PCS_SCTRL_LOOP;
1765 writel(val, gp->regs + PCS_SCTRL);
1766 } 1783 }
1767 1784
1768 /* Default aneg parameters */ 1785 /* Default aneg parameters */
@@ -2680,6 +2697,21 @@ static int gem_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2680 cmd->speed = 0; 2697 cmd->speed = 0;
2681 cmd->duplex = cmd->port = cmd->phy_address = 2698 cmd->duplex = cmd->port = cmd->phy_address =
2682 cmd->transceiver = cmd->autoneg = 0; 2699 cmd->transceiver = cmd->autoneg = 0;
2700
2701 /* serdes means usually a Fibre connector, with most fixed */
2702 if (gp->phy_type == phy_serdes) {
2703 cmd->port = PORT_FIBRE;
2704 cmd->supported = (SUPPORTED_1000baseT_Half |
2705 SUPPORTED_1000baseT_Full |
2706 SUPPORTED_FIBRE | SUPPORTED_Autoneg |
2707 SUPPORTED_Pause | SUPPORTED_Asym_Pause);
2708 cmd->advertising = cmd->supported;
2709 cmd->transceiver = XCVR_INTERNAL;
2710 if (gp->lstate == link_up)
2711 cmd->speed = SPEED_1000;
2712 cmd->duplex = DUPLEX_FULL;
2713 cmd->autoneg = 1;
2714 }
2683 } 2715 }
2684 cmd->maxtxpkt = cmd->maxrxpkt = 0; 2716 cmd->maxtxpkt = cmd->maxrxpkt = 0;
2685 2717
diff --git a/drivers/pcmcia/bfin_cf_pcmcia.c b/drivers/pcmcia/bfin_cf_pcmcia.c
index bb7338863fb..b59d4115d20 100644
--- a/drivers/pcmcia/bfin_cf_pcmcia.c
+++ b/drivers/pcmcia/bfin_cf_pcmcia.c
@@ -334,6 +334,6 @@ static void __exit bfin_cf_exit(void)
334module_init(bfin_cf_init); 334module_init(bfin_cf_init);
335module_exit(bfin_cf_exit); 335module_exit(bfin_cf_exit);
336 336
337MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>") 337MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
338MODULE_DESCRIPTION("BFIN CF/PCMCIA Driver"); 338MODULE_DESCRIPTION("BFIN CF/PCMCIA Driver");
339MODULE_LICENSE("GPL"); 339MODULE_LICENSE("GPL");
diff --git a/drivers/scsi/device_handler/scsi_dh_hp_sw.c b/drivers/scsi/device_handler/scsi_dh_hp_sw.c
index 9aec4ca64e5..f7da7530875 100644
--- a/drivers/scsi/device_handler/scsi_dh_hp_sw.c
+++ b/drivers/scsi/device_handler/scsi_dh_hp_sw.c
@@ -107,6 +107,7 @@ static int hp_sw_tur(struct scsi_device *sdev, struct hp_sw_dh_data *h)
107 struct request *req; 107 struct request *req;
108 int ret; 108 int ret;
109 109
110retry:
110 req = blk_get_request(sdev->request_queue, WRITE, GFP_NOIO); 111 req = blk_get_request(sdev->request_queue, WRITE, GFP_NOIO);
111 if (!req) 112 if (!req)
112 return SCSI_DH_RES_TEMP_UNAVAIL; 113 return SCSI_DH_RES_TEMP_UNAVAIL;
@@ -121,7 +122,6 @@ static int hp_sw_tur(struct scsi_device *sdev, struct hp_sw_dh_data *h)
121 memset(req->sense, 0, SCSI_SENSE_BUFFERSIZE); 122 memset(req->sense, 0, SCSI_SENSE_BUFFERSIZE);
122 req->sense_len = 0; 123 req->sense_len = 0;
123 124
124retry:
125 ret = blk_execute_rq(req->q, NULL, req, 1); 125 ret = blk_execute_rq(req->q, NULL, req, 1);
126 if (ret == -EIO) { 126 if (ret == -EIO) {
127 if (req->sense_len > 0) { 127 if (req->sense_len > 0) {
@@ -136,8 +136,10 @@ retry:
136 h->path_state = HP_SW_PATH_ACTIVE; 136 h->path_state = HP_SW_PATH_ACTIVE;
137 ret = SCSI_DH_OK; 137 ret = SCSI_DH_OK;
138 } 138 }
139 if (ret == SCSI_DH_IMM_RETRY) 139 if (ret == SCSI_DH_IMM_RETRY) {
140 blk_put_request(req);
140 goto retry; 141 goto retry;
142 }
141 if (ret == SCSI_DH_DEV_OFFLINED) { 143 if (ret == SCSI_DH_DEV_OFFLINED) {
142 h->path_state = HP_SW_PATH_PASSIVE; 144 h->path_state = HP_SW_PATH_PASSIVE;
143 ret = SCSI_DH_OK; 145 ret = SCSI_DH_OK;
@@ -200,6 +202,7 @@ static int hp_sw_start_stop(struct scsi_device *sdev, struct hp_sw_dh_data *h)
200 struct request *req; 202 struct request *req;
201 int ret, retry; 203 int ret, retry;
202 204
205retry:
203 req = blk_get_request(sdev->request_queue, WRITE, GFP_NOIO); 206 req = blk_get_request(sdev->request_queue, WRITE, GFP_NOIO);
204 if (!req) 207 if (!req)
205 return SCSI_DH_RES_TEMP_UNAVAIL; 208 return SCSI_DH_RES_TEMP_UNAVAIL;
@@ -216,7 +219,6 @@ static int hp_sw_start_stop(struct scsi_device *sdev, struct hp_sw_dh_data *h)
216 req->sense_len = 0; 219 req->sense_len = 0;
217 retry = h->retries; 220 retry = h->retries;
218 221
219retry:
220 ret = blk_execute_rq(req->q, NULL, req, 1); 222 ret = blk_execute_rq(req->q, NULL, req, 1);
221 if (ret == -EIO) { 223 if (ret == -EIO) {
222 if (req->sense_len > 0) { 224 if (req->sense_len > 0) {
@@ -231,8 +233,10 @@ retry:
231 ret = SCSI_DH_OK; 233 ret = SCSI_DH_OK;
232 234
233 if (ret == SCSI_DH_RETRY) { 235 if (ret == SCSI_DH_RETRY) {
234 if (--retry) 236 if (--retry) {
237 blk_put_request(req);
235 goto retry; 238 goto retry;
239 }
236 ret = SCSI_DH_IO; 240 ret = SCSI_DH_IO;
237 } 241 }
238 242
diff --git a/drivers/video/aty/radeon_accel.c b/drivers/video/aty/radeon_accel.c
index 8da5e5ab854..a469a3d6edc 100644
--- a/drivers/video/aty/radeon_accel.c
+++ b/drivers/video/aty/radeon_accel.c
@@ -5,61 +5,61 @@
5 * --dte 5 * --dte
6 */ 6 */
7 7
8#define FLUSH_CACHE_WORKAROUND 1 8static void radeon_fixup_offset(struct radeonfb_info *rinfo)
9
10void radeon_fifo_update_and_wait(struct radeonfb_info *rinfo, int entries)
11{ 9{
12 int i; 10 u32 local_base;
11
12 /* *** Ugly workaround *** */
13 /*
14 * On some platforms, the video memory is mapped at 0 in radeon chip space
15 * (like PPCs) by the firmware. X will always move it up so that it's seen
16 * by the chip to be at the same address as the PCI BAR.
17 * That means that when switching back from X, there is a mismatch between
18 * the offsets programmed into the engine. This means that potentially,
19 * accel operations done before radeonfb has a chance to re-init the engine
20 * will have incorrect offsets, and potentially trash system memory !
21 *
22 * The correct fix is for fbcon to never call any accel op before the engine
23 * has properly been re-initialized (by a call to set_var), but this is a
24 * complex fix. This workaround in the meantime, called before every accel
25 * operation, makes sure the offsets are in sync.
26 */
13 27
14 for (i=0; i<2000000; i++) { 28 radeon_fifo_wait (1);
15 rinfo->fifo_free = INREG(RBBM_STATUS) & 0x7f; 29 local_base = INREG(MC_FB_LOCATION) << 16;
16 if (rinfo->fifo_free >= entries) 30 if (local_base == rinfo->fb_local_base)
17 return; 31 return;
18 udelay(10);
19 }
20 printk(KERN_ERR "radeonfb: FIFO Timeout !\n");
21 /* XXX Todo: attempt to reset the engine */
22}
23 32
24static inline void radeon_fifo_wait(struct radeonfb_info *rinfo, int entries) 33 rinfo->fb_local_base = local_base;
25{
26 if (entries <= rinfo->fifo_free)
27 rinfo->fifo_free -= entries;
28 else
29 radeon_fifo_update_and_wait(rinfo, entries);
30}
31 34
32static inline void radeonfb_set_creg(struct radeonfb_info *rinfo, u32 reg, 35 radeon_fifo_wait (3);
33 u32 *cache, u32 new_val) 36 OUTREG(DEFAULT_PITCH_OFFSET, (rinfo->pitch << 0x16) |
34{ 37 (rinfo->fb_local_base >> 10));
35 if (new_val == *cache) 38 OUTREG(DST_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
36 return; 39 OUTREG(SRC_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
37 *cache = new_val;
38 radeon_fifo_wait(rinfo, 1);
39 OUTREG(reg, new_val);
40} 40}
41 41
42static void radeonfb_prim_fillrect(struct radeonfb_info *rinfo, 42static void radeonfb_prim_fillrect(struct radeonfb_info *rinfo,
43 const struct fb_fillrect *region) 43 const struct fb_fillrect *region)
44{ 44{
45 radeonfb_set_creg(rinfo, DP_GUI_MASTER_CNTL, &rinfo->dp_gui_mc_cache, 45 radeon_fifo_wait(4);
46 rinfo->dp_gui_mc_base | GMC_BRUSH_SOLID_COLOR | ROP3_P); 46
47 radeonfb_set_creg(rinfo, DP_CNTL, &rinfo->dp_cntl_cache, 47 OUTREG(DP_GUI_MASTER_CNTL,
48 DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 48 rinfo->dp_gui_master_cntl /* contains, like GMC_DST_32BPP */
49 radeonfb_set_creg(rinfo, DP_BRUSH_FRGD_CLR, &rinfo->dp_brush_fg_cache, 49 | GMC_BRUSH_SOLID_COLOR
50 region->color); 50 | ROP3_P);
51 51 if (radeon_get_dstbpp(rinfo->depth) != DST_8BPP)
52 /* Ensure the dst cache is flushed and the engine idle before 52 OUTREG(DP_BRUSH_FRGD_CLR, rinfo->pseudo_palette[region->color]);
53 * issuing the operation. 53 else
54 * 54 OUTREG(DP_BRUSH_FRGD_CLR, region->color);
55 * This works around engine lockups on some cards 55 OUTREG(DP_WRITE_MSK, 0xffffffff);
56 */ 56 OUTREG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM));
57#if FLUSH_CACHE_WORKAROUND 57
58 radeon_fifo_wait(rinfo, 2); 58 radeon_fifo_wait(2);
59 OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL); 59 OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL);
60 OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE)); 60 OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE));
61#endif 61
62 radeon_fifo_wait(rinfo, 2); 62 radeon_fifo_wait(2);
63 OUTREG(DST_Y_X, (region->dy << 16) | region->dx); 63 OUTREG(DST_Y_X, (region->dy << 16) | region->dx);
64 OUTREG(DST_WIDTH_HEIGHT, (region->width << 16) | region->height); 64 OUTREG(DST_WIDTH_HEIGHT, (region->width << 16) | region->height);
65} 65}
@@ -70,14 +70,15 @@ void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region)
70 struct fb_fillrect modded; 70 struct fb_fillrect modded;
71 int vxres, vyres; 71 int vxres, vyres;
72 72
73 WARN_ON(rinfo->gfx_mode); 73 if (info->state != FBINFO_STATE_RUNNING)
74 if (info->state != FBINFO_STATE_RUNNING || rinfo->gfx_mode)
75 return; 74 return;
76 if (info->flags & FBINFO_HWACCEL_DISABLED) { 75 if (info->flags & FBINFO_HWACCEL_DISABLED) {
77 cfb_fillrect(info, region); 76 cfb_fillrect(info, region);
78 return; 77 return;
79 } 78 }
80 79
80 radeon_fixup_offset(rinfo);
81
81 vxres = info->var.xres_virtual; 82 vxres = info->var.xres_virtual;
82 vyres = info->var.yres_virtual; 83 vyres = info->var.yres_virtual;
83 84
@@ -90,10 +91,6 @@ void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region)
90 if(modded.dx + modded.width > vxres) modded.width = vxres - modded.dx; 91 if(modded.dx + modded.width > vxres) modded.width = vxres - modded.dx;
91 if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy; 92 if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy;
92 93
93 if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
94 info->fix.visual == FB_VISUAL_DIRECTCOLOR )
95 modded.color = ((u32 *) (info->pseudo_palette))[region->color];
96
97 radeonfb_prim_fillrect(rinfo, &modded); 94 radeonfb_prim_fillrect(rinfo, &modded);
98} 95}
99 96
@@ -112,22 +109,22 @@ static void radeonfb_prim_copyarea(struct radeonfb_info *rinfo,
112 if ( xdir < 0 ) { sx += w-1; dx += w-1; } 109 if ( xdir < 0 ) { sx += w-1; dx += w-1; }
113 if ( ydir < 0 ) { sy += h-1; dy += h-1; } 110 if ( ydir < 0 ) { sy += h-1; dy += h-1; }
114 111
115 radeonfb_set_creg(rinfo, DP_GUI_MASTER_CNTL, &rinfo->dp_gui_mc_cache, 112 radeon_fifo_wait(3);
116 rinfo->dp_gui_mc_base | 113 OUTREG(DP_GUI_MASTER_CNTL,
117 GMC_BRUSH_NONE | 114 rinfo->dp_gui_master_cntl /* i.e. GMC_DST_32BPP */
118 GMC_SRC_DATATYPE_COLOR | 115 | GMC_BRUSH_NONE
119 ROP3_S | 116 | GMC_SRC_DSTCOLOR
120 DP_SRC_SOURCE_MEMORY); 117 | ROP3_S
121 radeonfb_set_creg(rinfo, DP_CNTL, &rinfo->dp_cntl_cache, 118 | DP_SRC_SOURCE_MEMORY );
122 (xdir>=0 ? DST_X_LEFT_TO_RIGHT : 0) | 119 OUTREG(DP_WRITE_MSK, 0xffffffff);
123 (ydir>=0 ? DST_Y_TOP_TO_BOTTOM : 0)); 120 OUTREG(DP_CNTL, (xdir>=0 ? DST_X_LEFT_TO_RIGHT : 0)
124 121 | (ydir>=0 ? DST_Y_TOP_TO_BOTTOM : 0));
125#if FLUSH_CACHE_WORKAROUND 122
126 radeon_fifo_wait(rinfo, 2); 123 radeon_fifo_wait(2);
127 OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL); 124 OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL);
128 OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE)); 125 OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE));
129#endif 126
130 radeon_fifo_wait(rinfo, 3); 127 radeon_fifo_wait(3);
131 OUTREG(SRC_Y_X, (sy << 16) | sx); 128 OUTREG(SRC_Y_X, (sy << 16) | sx);
132 OUTREG(DST_Y_X, (dy << 16) | dx); 129 OUTREG(DST_Y_X, (dy << 16) | dx);
133 OUTREG(DST_HEIGHT_WIDTH, (h << 16) | w); 130 OUTREG(DST_HEIGHT_WIDTH, (h << 16) | w);
@@ -146,14 +143,15 @@ void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
146 modded.width = area->width; 143 modded.width = area->width;
147 modded.height = area->height; 144 modded.height = area->height;
148 145
149 WARN_ON(rinfo->gfx_mode); 146 if (info->state != FBINFO_STATE_RUNNING)
150 if (info->state != FBINFO_STATE_RUNNING || rinfo->gfx_mode)
151 return; 147 return;
152 if (info->flags & FBINFO_HWACCEL_DISABLED) { 148 if (info->flags & FBINFO_HWACCEL_DISABLED) {
153 cfb_copyarea(info, area); 149 cfb_copyarea(info, area);
154 return; 150 return;
155 } 151 }
156 152
153 radeon_fixup_offset(rinfo);
154
157 vxres = info->var.xres_virtual; 155 vxres = info->var.xres_virtual;
158 vyres = info->var.yres_virtual; 156 vyres = info->var.yres_virtual;
159 157
@@ -170,116 +168,13 @@ void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
170 radeonfb_prim_copyarea(rinfo, &modded); 168 radeonfb_prim_copyarea(rinfo, &modded);
171} 169}
172 170
173static void radeonfb_prim_imageblit(struct radeonfb_info *rinfo,
174 const struct fb_image *image,
175 u32 fg, u32 bg)
176{
177 unsigned int dwords;
178 u32 *bits;
179
180 radeonfb_set_creg(rinfo, DP_GUI_MASTER_CNTL, &rinfo->dp_gui_mc_cache,
181 rinfo->dp_gui_mc_base |
182 GMC_BRUSH_NONE | GMC_DST_CLIP_LEAVE |
183 GMC_SRC_DATATYPE_MONO_FG_BG |
184 ROP3_S |
185 GMC_BYTE_ORDER_MSB_TO_LSB |
186 DP_SRC_SOURCE_HOST_DATA);
187 radeonfb_set_creg(rinfo, DP_CNTL, &rinfo->dp_cntl_cache,
188 DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM);
189 radeonfb_set_creg(rinfo, DP_SRC_FRGD_CLR, &rinfo->dp_src_fg_cache, fg);
190 radeonfb_set_creg(rinfo, DP_SRC_BKGD_CLR, &rinfo->dp_src_bg_cache, bg);
191
192 /* Ensure the dst cache is flushed and the engine idle before
193 * issuing the operation.
194 *
195 * This works around engine lockups on some cards
196 */
197#if FLUSH_CACHE_WORKAROUND
198 radeon_fifo_wait(rinfo, 2);
199 OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL);
200 OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE));
201#endif
202
203 /* X here pads width to a multiple of 32 and uses the clipper to
204 * adjust the result. Is that really necessary ? Things seem to
205 * work ok for me without that and the doco doesn't seem to imply]
206 * there is such a restriction.
207 */
208 radeon_fifo_wait(rinfo, 4);
209 OUTREG(SC_TOP_LEFT, (image->dy << 16) | image->dx);
210 OUTREG(SC_BOTTOM_RIGHT, ((image->dy + image->height) << 16) |
211 (image->dx + image->width));
212 OUTREG(DST_Y_X, (image->dy << 16) | image->dx);
213
214 OUTREG(DST_HEIGHT_WIDTH, (image->height << 16) | ((image->width + 31) & ~31));
215
216 dwords = (image->width + 31) >> 5;
217 dwords *= image->height;
218 bits = (u32*)(image->data);
219
220 while(dwords >= 8) {
221 radeon_fifo_wait(rinfo, 8);
222#if BITS_PER_LONG == 64
223 __raw_writeq(*((u64 *)(bits)), rinfo->mmio_base + HOST_DATA0);
224 __raw_writeq(*((u64 *)(bits+2)), rinfo->mmio_base + HOST_DATA2);
225 __raw_writeq(*((u64 *)(bits+4)), rinfo->mmio_base + HOST_DATA4);
226 __raw_writeq(*((u64 *)(bits+6)), rinfo->mmio_base + HOST_DATA6);
227 bits += 8;
228#else
229 __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA0);
230 __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA1);
231 __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA2);
232 __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA3);
233 __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA4);
234 __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA5);
235 __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA6);
236 __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA7);
237#endif
238 dwords -= 8;
239 }
240 while(dwords--) {
241 radeon_fifo_wait(rinfo, 1);
242 __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA0);
243 }
244}
245
246void radeonfb_imageblit(struct fb_info *info, const struct fb_image *image) 171void radeonfb_imageblit(struct fb_info *info, const struct fb_image *image)
247{ 172{
248 struct radeonfb_info *rinfo = info->par; 173 struct radeonfb_info *rinfo = info->par;
249 u32 fg, bg;
250 174
251 WARN_ON(rinfo->gfx_mode); 175 if (info->state != FBINFO_STATE_RUNNING)
252 if (info->state != FBINFO_STATE_RUNNING || rinfo->gfx_mode)
253 return;
254
255 if (!image->width || !image->height)
256 return; 176 return;
257 177 radeon_engine_idle();
258 /* We only do 1 bpp color expansion for now */
259 if (!accel_cexp ||
260 (info->flags & FBINFO_HWACCEL_DISABLED) || image->depth != 1)
261 goto fallback;
262
263 /* Fallback if running out of the screen. We may do clipping
264 * in the future */
265 if ((image->dx + image->width) > info->var.xres_virtual ||
266 (image->dy + image->height) > info->var.yres_virtual)
267 goto fallback;
268
269 if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
270 info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
271 fg = ((u32*)(info->pseudo_palette))[image->fg_color];
272 bg = ((u32*)(info->pseudo_palette))[image->bg_color];
273 } else {
274 fg = image->fg_color;
275 bg = image->bg_color;
276 }
277
278 radeonfb_prim_imageblit(rinfo, image, fg, bg);
279 return;
280
281 fallback:
282 radeon_engine_idle(rinfo);
283 178
284 cfb_imageblit(info, image); 179 cfb_imageblit(info, image);
285} 180}
@@ -290,8 +185,7 @@ int radeonfb_sync(struct fb_info *info)
290 185
291 if (info->state != FBINFO_STATE_RUNNING) 186 if (info->state != FBINFO_STATE_RUNNING)
292 return 0; 187 return 0;
293 188 radeon_engine_idle();
294 radeon_engine_idle(rinfo);
295 189
296 return 0; 190 return 0;
297} 191}
@@ -367,10 +261,9 @@ void radeonfb_engine_init (struct radeonfb_info *rinfo)
367 /* disable 3D engine */ 261 /* disable 3D engine */
368 OUTREG(RB3D_CNTL, 0); 262 OUTREG(RB3D_CNTL, 0);
369 263
370 rinfo->fifo_free = 0;
371 radeonfb_engine_reset(rinfo); 264 radeonfb_engine_reset(rinfo);
372 265
373 radeon_fifo_wait(rinfo, 1); 266 radeon_fifo_wait (1);
374 if (IS_R300_VARIANT(rinfo)) { 267 if (IS_R300_VARIANT(rinfo)) {
375 OUTREG(RB2D_DSTCACHE_MODE, INREG(RB2D_DSTCACHE_MODE) | 268 OUTREG(RB2D_DSTCACHE_MODE, INREG(RB2D_DSTCACHE_MODE) |
376 RB2D_DC_AUTOFLUSH_ENABLE | 269 RB2D_DC_AUTOFLUSH_ENABLE |
@@ -384,7 +277,7 @@ void radeonfb_engine_init (struct radeonfb_info *rinfo)
384 OUTREG(RB2D_DSTCACHE_MODE, 0); 277 OUTREG(RB2D_DSTCACHE_MODE, 0);
385 } 278 }
386 279
387 radeon_fifo_wait(rinfo, 3); 280 radeon_fifo_wait (3);
388 /* We re-read MC_FB_LOCATION from card as it can have been 281 /* We re-read MC_FB_LOCATION from card as it can have been
389 * modified by XFree drivers (ouch !) 282 * modified by XFree drivers (ouch !)
390 */ 283 */
@@ -395,57 +288,41 @@ void radeonfb_engine_init (struct radeonfb_info *rinfo)
395 OUTREG(DST_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10)); 288 OUTREG(DST_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
396 OUTREG(SRC_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10)); 289 OUTREG(SRC_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
397 290
398 radeon_fifo_wait(rinfo, 1); 291 radeon_fifo_wait (1);
399#ifdef __BIG_ENDIAN 292#if defined(__BIG_ENDIAN)
400 OUTREGP(DP_DATATYPE, HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN); 293 OUTREGP(DP_DATATYPE, HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN);
401#else 294#else
402 OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN); 295 OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN);
403#endif 296#endif
404 radeon_fifo_wait(rinfo, 2); 297 radeon_fifo_wait (2);
405 OUTREG(DEFAULT_SC_TOP_LEFT, 0); 298 OUTREG(DEFAULT_SC_TOP_LEFT, 0);
406 OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX | 299 OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX |
407 DEFAULT_SC_BOTTOM_MAX)); 300 DEFAULT_SC_BOTTOM_MAX));
408 301
409 /* set default DP_GUI_MASTER_CNTL */
410 temp = radeon_get_dstbpp(rinfo->depth); 302 temp = radeon_get_dstbpp(rinfo->depth);
411 rinfo->dp_gui_mc_base = ((temp << 8) | GMC_CLR_CMP_CNTL_DIS); 303 rinfo->dp_gui_master_cntl = ((temp << 8) | GMC_CLR_CMP_CNTL_DIS);
412 304
413 rinfo->dp_gui_mc_cache = rinfo->dp_gui_mc_base | 305 radeon_fifo_wait (1);
414 GMC_BRUSH_SOLID_COLOR | 306 OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
415 GMC_SRC_DATATYPE_COLOR; 307 GMC_BRUSH_SOLID_COLOR |
416 radeon_fifo_wait(rinfo, 1); 308 GMC_SRC_DATATYPE_COLOR));
417 OUTREG(DP_GUI_MASTER_CNTL, rinfo->dp_gui_mc_cache);
418 309
310 radeon_fifo_wait (7);
419 311
420 /* clear line drawing regs */ 312 /* clear line drawing regs */
421 radeon_fifo_wait(rinfo, 2);
422 OUTREG(DST_LINE_START, 0); 313 OUTREG(DST_LINE_START, 0);
423 OUTREG(DST_LINE_END, 0); 314 OUTREG(DST_LINE_END, 0);
424 315
425 /* set brush and source color regs */ 316 /* set brush color regs */
426 rinfo->dp_brush_fg_cache = 0xffffffff; 317 OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff);
427 rinfo->dp_brush_bg_cache = 0x00000000; 318 OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000);
428 rinfo->dp_src_fg_cache = 0xffffffff; 319
429 rinfo->dp_src_bg_cache = 0x00000000; 320 /* set source color regs */
430 radeon_fifo_wait(rinfo, 4); 321 OUTREG(DP_SRC_FRGD_CLR, 0xffffffff);
431 OUTREG(DP_BRUSH_FRGD_CLR, rinfo->dp_brush_fg_cache); 322 OUTREG(DP_SRC_BKGD_CLR, 0x00000000);
432 OUTREG(DP_BRUSH_BKGD_CLR, rinfo->dp_brush_bg_cache);
433 OUTREG(DP_SRC_FRGD_CLR, rinfo->dp_src_fg_cache);
434 OUTREG(DP_SRC_BKGD_CLR, rinfo->dp_src_bg_cache);
435
436 /* Default direction */
437 rinfo->dp_cntl_cache = DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM;
438 radeon_fifo_wait(rinfo, 1);
439 OUTREG(DP_CNTL, rinfo->dp_cntl_cache);
440 323
441 /* default write mask */ 324 /* default write mask */
442 radeon_fifo_wait(rinfo, 1);
443 OUTREG(DP_WRITE_MSK, 0xffffffff); 325 OUTREG(DP_WRITE_MSK, 0xffffffff);
444 326
445 /* Default to no swapping of host data */ 327 radeon_engine_idle ();
446 radeon_fifo_wait(rinfo, 1);
447 OUTREG(RBBM_GUICNTL, RBBM_GUICNTL_HOST_DATA_SWAP_NONE);
448
449 /* Make sure it's settled */
450 radeon_engine_idle(rinfo);
451} 328}
diff --git a/drivers/video/aty/radeon_backlight.c b/drivers/video/aty/radeon_backlight.c
index f343ba83f0a..1a056adb61c 100644
--- a/drivers/video/aty/radeon_backlight.c
+++ b/drivers/video/aty/radeon_backlight.c
@@ -66,7 +66,7 @@ static int radeon_bl_update_status(struct backlight_device *bd)
66 level = bd->props.brightness; 66 level = bd->props.brightness;
67 67
68 del_timer_sync(&rinfo->lvds_timer); 68 del_timer_sync(&rinfo->lvds_timer);
69 radeon_engine_idle(rinfo); 69 radeon_engine_idle();
70 70
71 lvds_gen_cntl = INREG(LVDS_GEN_CNTL); 71 lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
72 if (level > 0) { 72 if (level > 0) {
diff --git a/drivers/video/aty/radeon_base.c b/drivers/video/aty/radeon_base.c
index d5b27f9d374..d0f1a7fc2c9 100644
--- a/drivers/video/aty/radeon_base.c
+++ b/drivers/video/aty/radeon_base.c
@@ -282,8 +282,6 @@ static int backlight = 1;
282static int backlight = 0; 282static int backlight = 0;
283#endif 283#endif
284 284
285int accel_cexp = 0;
286
287/* 285/*
288 * prototypes 286 * prototypes
289 */ 287 */
@@ -854,6 +852,7 @@ static int radeonfb_pan_display (struct fb_var_screeninfo *var,
854 if (rinfo->asleep) 852 if (rinfo->asleep)
855 return 0; 853 return 0;
856 854
855 radeon_fifo_wait(2);
857 OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset) 856 OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset)
858 * var->bits_per_pixel / 8) & ~7); 857 * var->bits_per_pixel / 8) & ~7);
859 return 0; 858 return 0;
@@ -883,6 +882,7 @@ static int radeonfb_ioctl (struct fb_info *info, unsigned int cmd,
883 if (rc) 882 if (rc)
884 return rc; 883 return rc;
885 884
885 radeon_fifo_wait(2);
886 if (value & 0x01) { 886 if (value & 0x01) {
887 tmp = INREG(LVDS_GEN_CNTL); 887 tmp = INREG(LVDS_GEN_CNTL);
888 888
@@ -940,7 +940,7 @@ int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch)
940 if (rinfo->lock_blank) 940 if (rinfo->lock_blank)
941 return 0; 941 return 0;
942 942
943 radeon_engine_idle(rinfo); 943 radeon_engine_idle();
944 944
945 val = INREG(CRTC_EXT_CNTL); 945 val = INREG(CRTC_EXT_CNTL);
946 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | 946 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
@@ -1048,7 +1048,7 @@ static int radeonfb_blank (int blank, struct fb_info *info)
1048 1048
1049 if (rinfo->asleep) 1049 if (rinfo->asleep)
1050 return 0; 1050 return 0;
1051 1051
1052 return radeon_screen_blank(rinfo, blank, 0); 1052 return radeon_screen_blank(rinfo, blank, 0);
1053} 1053}
1054 1054
@@ -1074,6 +1074,8 @@ static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
1074 pindex = regno; 1074 pindex = regno;
1075 1075
1076 if (!rinfo->asleep) { 1076 if (!rinfo->asleep) {
1077 radeon_fifo_wait(9);
1078
1077 if (rinfo->bpp == 16) { 1079 if (rinfo->bpp == 16) {
1078 pindex = regno * 8; 1080 pindex = regno * 8;
1079 1081
@@ -1242,6 +1244,8 @@ static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_reg
1242{ 1244{
1243 int i; 1245 int i;
1244 1246
1247 radeon_fifo_wait(20);
1248
1245 /* Workaround from XFree */ 1249 /* Workaround from XFree */
1246 if (rinfo->is_mobility) { 1250 if (rinfo->is_mobility) {
1247 /* A temporal workaround for the occational blanking on certain laptop 1251 /* A temporal workaround for the occational blanking on certain laptop
@@ -1337,7 +1341,7 @@ static void radeon_lvds_timer_func(unsigned long data)
1337{ 1341{
1338 struct radeonfb_info *rinfo = (struct radeonfb_info *)data; 1342 struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1339 1343
1340 radeon_engine_idle(rinfo); 1344 radeon_engine_idle();
1341 1345
1342 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl); 1346 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
1343} 1347}
@@ -1355,11 +1359,10 @@ void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1355 if (nomodeset) 1359 if (nomodeset)
1356 return; 1360 return;
1357 1361
1358 radeon_engine_idle(rinfo);
1359
1360 if (!regs_only) 1362 if (!regs_only)
1361 radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0); 1363 radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0);
1362 1364
1365 radeon_fifo_wait(31);
1363 for (i=0; i<10; i++) 1366 for (i=0; i<10; i++)
1364 OUTREG(common_regs[i].reg, common_regs[i].val); 1367 OUTREG(common_regs[i].reg, common_regs[i].val);
1365 1368
@@ -1387,6 +1390,7 @@ void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1387 radeon_write_pll_regs(rinfo, mode); 1390 radeon_write_pll_regs(rinfo, mode);
1388 1391
1389 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) { 1392 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1393 radeon_fifo_wait(10);
1390 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp); 1394 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
1391 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp); 1395 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
1392 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid); 1396 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
@@ -1401,6 +1405,7 @@ void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1401 if (!regs_only) 1405 if (!regs_only)
1402 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0); 1406 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0);
1403 1407
1408 radeon_fifo_wait(2);
1404 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl); 1409 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
1405 1410
1406 return; 1411 return;
@@ -1551,7 +1556,7 @@ static int radeonfb_set_par(struct fb_info *info)
1551 /* We always want engine to be idle on a mode switch, even 1556 /* We always want engine to be idle on a mode switch, even
1552 * if we won't actually change the mode 1557 * if we won't actually change the mode
1553 */ 1558 */
1554 radeon_engine_idle(rinfo); 1559 radeon_engine_idle();
1555 1560
1556 hSyncStart = mode->xres + mode->right_margin; 1561 hSyncStart = mode->xres + mode->right_margin;
1557 hSyncEnd = hSyncStart + mode->hsync_len; 1562 hSyncEnd = hSyncStart + mode->hsync_len;
@@ -1846,6 +1851,7 @@ static int radeonfb_set_par(struct fb_info *info)
1846 return 0; 1851 return 0;
1847} 1852}
1848 1853
1854
1849static struct fb_ops radeonfb_ops = { 1855static struct fb_ops radeonfb_ops = {
1850 .owner = THIS_MODULE, 1856 .owner = THIS_MODULE,
1851 .fb_check_var = radeonfb_check_var, 1857 .fb_check_var = radeonfb_check_var,
@@ -1869,7 +1875,6 @@ static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
1869 info->par = rinfo; 1875 info->par = rinfo;
1870 info->pseudo_palette = rinfo->pseudo_palette; 1876 info->pseudo_palette = rinfo->pseudo_palette;
1871 info->flags = FBINFO_DEFAULT 1877 info->flags = FBINFO_DEFAULT
1872 | FBINFO_HWACCEL_IMAGEBLIT
1873 | FBINFO_HWACCEL_COPYAREA 1878 | FBINFO_HWACCEL_COPYAREA
1874 | FBINFO_HWACCEL_FILLRECT 1879 | FBINFO_HWACCEL_FILLRECT
1875 | FBINFO_HWACCEL_XPAN 1880 | FBINFO_HWACCEL_XPAN
@@ -1877,7 +1882,6 @@ static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
1877 info->fbops = &radeonfb_ops; 1882 info->fbops = &radeonfb_ops;
1878 info->screen_base = rinfo->fb_base; 1883 info->screen_base = rinfo->fb_base;
1879 info->screen_size = rinfo->mapped_vram; 1884 info->screen_size = rinfo->mapped_vram;
1880
1881 /* Fill fix common fields */ 1885 /* Fill fix common fields */
1882 strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id)); 1886 strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
1883 info->fix.smem_start = rinfo->fb_base_phys; 1887 info->fix.smem_start = rinfo->fb_base_phys;
@@ -1892,25 +1896,8 @@ static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
1892 info->fix.mmio_len = RADEON_REGSIZE; 1896 info->fix.mmio_len = RADEON_REGSIZE;
1893 info->fix.accel = FB_ACCEL_ATI_RADEON; 1897 info->fix.accel = FB_ACCEL_ATI_RADEON;
1894 1898
1895 /* Allocate colormap */
1896 fb_alloc_cmap(&info->cmap, 256, 0); 1899 fb_alloc_cmap(&info->cmap, 256, 0);
1897 1900
1898 /* Setup pixmap used for acceleration */
1899#define PIXMAP_SIZE (2048 * 4)
1900
1901 info->pixmap.addr = kmalloc(PIXMAP_SIZE, GFP_KERNEL);
1902 if (!info->pixmap.addr) {
1903 printk(KERN_ERR "radeonfb: Failed to allocate pixmap !\n");
1904 noaccel = 1;
1905 goto bail;
1906 }
1907 info->pixmap.size = PIXMAP_SIZE;
1908 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1909 info->pixmap.scan_align = 4;
1910 info->pixmap.buf_align = 4;
1911 info->pixmap.access_align = 32;
1912
1913bail:
1914 if (noaccel) 1901 if (noaccel)
1915 info->flags |= FBINFO_HWACCEL_DISABLED; 1902 info->flags |= FBINFO_HWACCEL_DISABLED;
1916 1903
@@ -2019,6 +2006,7 @@ static void radeon_identify_vram(struct radeonfb_info *rinfo)
2019 u32 tom = INREG(NB_TOM); 2006 u32 tom = INREG(NB_TOM);
2020 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024); 2007 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
2021 2008
2009 radeon_fifo_wait(6);
2022 OUTREG(MC_FB_LOCATION, tom); 2010 OUTREG(MC_FB_LOCATION, tom);
2023 OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); 2011 OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2024 OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); 2012 OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
@@ -2522,8 +2510,6 @@ static int __init radeonfb_setup (char *options)
2522 } else if (!strncmp(this_opt, "ignore_devlist", 14)) { 2510 } else if (!strncmp(this_opt, "ignore_devlist", 14)) {
2523 ignore_devlist = 1; 2511 ignore_devlist = 1;
2524#endif 2512#endif
2525 } else if (!strncmp(this_opt, "accel_cexp", 12)) {
2526 accel_cexp = 1;
2527 } else 2513 } else
2528 mode_option = this_opt; 2514 mode_option = this_opt;
2529 } 2515 }
@@ -2571,8 +2557,6 @@ module_param(monitor_layout, charp, 0);
2571MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)"); 2557MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)");
2572module_param(force_measure_pll, bool, 0); 2558module_param(force_measure_pll, bool, 0);
2573MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)"); 2559MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)");
2574module_param(accel_cexp, bool, 0);
2575MODULE_PARM_DESC(accel_cexp, "Use acceleration engine for color expansion");
2576#ifdef CONFIG_MTRR 2560#ifdef CONFIG_MTRR
2577module_param(nomtrr, bool, 0); 2561module_param(nomtrr, bool, 0);
2578MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers"); 2562MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
diff --git a/drivers/video/aty/radeon_pm.c b/drivers/video/aty/radeon_pm.c
index 3df5015f1d1..675abdafc2d 100644
--- a/drivers/video/aty/radeon_pm.c
+++ b/drivers/video/aty/radeon_pm.c
@@ -2653,9 +2653,9 @@ int radeonfb_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
2653 2653
2654 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) { 2654 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
2655 /* Make sure engine is reset */ 2655 /* Make sure engine is reset */
2656 radeon_engine_idle(rinfo); 2656 radeon_engine_idle();
2657 radeonfb_engine_reset(rinfo); 2657 radeonfb_engine_reset(rinfo);
2658 radeon_engine_idle(rinfo); 2658 radeon_engine_idle();
2659 } 2659 }
2660 2660
2661 /* Blank display and LCD */ 2661 /* Blank display and LCD */
@@ -2767,7 +2767,7 @@ int radeonfb_pci_resume(struct pci_dev *pdev)
2767 2767
2768 rinfo->asleep = 0; 2768 rinfo->asleep = 0;
2769 } else 2769 } else
2770 radeon_engine_idle(rinfo); 2770 radeon_engine_idle();
2771 2771
2772 /* Restore display & engine */ 2772 /* Restore display & engine */
2773 radeon_write_mode (rinfo, &rinfo->state, 1); 2773 radeon_write_mode (rinfo, &rinfo->state, 1);
diff --git a/drivers/video/aty/radeonfb.h b/drivers/video/aty/radeonfb.h
index 974ca6d8654..3ea1b00fdd2 100644
--- a/drivers/video/aty/radeonfb.h
+++ b/drivers/video/aty/radeonfb.h
@@ -336,15 +336,7 @@ struct radeonfb_info {
336 int mon2_type; 336 int mon2_type;
337 u8 *mon2_EDID; 337 u8 *mon2_EDID;
338 338
339 /* accel bits */ 339 u32 dp_gui_master_cntl;
340 u32 dp_gui_mc_base;
341 u32 dp_gui_mc_cache;
342 u32 dp_cntl_cache;
343 u32 dp_brush_fg_cache;
344 u32 dp_brush_bg_cache;
345 u32 dp_src_fg_cache;
346 u32 dp_src_bg_cache;
347 u32 fifo_free;
348 340
349 struct pll_info pll; 341 struct pll_info pll;
350 342
@@ -356,7 +348,6 @@ struct radeonfb_info {
356 int lock_blank; 348 int lock_blank;
357 int dynclk; 349 int dynclk;
358 int no_schedule; 350 int no_schedule;
359 int gfx_mode;
360 enum radeon_pm_mode pm_mode; 351 enum radeon_pm_mode pm_mode;
361 reinit_function_ptr reinit_func; 352 reinit_function_ptr reinit_func;
362 353
@@ -401,14 +392,8 @@ static inline void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms)
401#define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr) 392#define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
402#define INREG16(addr) readw((rinfo->mmio_base)+addr) 393#define INREG16(addr) readw((rinfo->mmio_base)+addr)
403#define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr) 394#define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr)
404
405#ifdef CONFIG_PPC
406#define INREG(addr) ({ eieio(); ld_le32(rinfo->mmio_base+(addr)); })
407#define OUTREG(addr,val) do { eieio(); st_le32(rinfo->mmio_base+(addr),(val)); } while(0)
408#else
409#define INREG(addr) readl((rinfo->mmio_base)+addr) 395#define INREG(addr) readl((rinfo->mmio_base)+addr)
410#define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr) 396#define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
411#endif
412 397
413static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, 398static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr,
414 u32 val, u32 mask) 399 u32 val, u32 mask)
@@ -550,7 +535,17 @@ static inline u32 radeon_get_dstbpp(u16 depth)
550 * 2D Engine helper routines 535 * 2D Engine helper routines
551 */ 536 */
552 537
553extern void radeon_fifo_update_and_wait(struct radeonfb_info *rinfo, int entries); 538static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
539{
540 int i;
541
542 for (i=0; i<2000000; i++) {
543 if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
544 return;
545 udelay(1);
546 }
547 printk(KERN_ERR "radeonfb: FIFO Timeout !\n");
548}
554 549
555static inline void radeon_engine_flush (struct radeonfb_info *rinfo) 550static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
556{ 551{
@@ -563,7 +558,7 @@ static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
563 /* Ensure FIFO is empty, ie, make sure the flush commands 558 /* Ensure FIFO is empty, ie, make sure the flush commands
564 * has reached the cache 559 * has reached the cache
565 */ 560 */
566 radeon_fifo_update_and_wait(rinfo, 64); 561 _radeon_fifo_wait (rinfo, 64);
567 562
568 /* Wait for the flush to complete */ 563 /* Wait for the flush to complete */
569 for (i=0; i < 2000000; i++) { 564 for (i=0; i < 2000000; i++) {
@@ -575,12 +570,12 @@ static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
575} 570}
576 571
577 572
578static inline void radeon_engine_idle(struct radeonfb_info *rinfo) 573static inline void _radeon_engine_idle(struct radeonfb_info *rinfo)
579{ 574{
580 int i; 575 int i;
581 576
582 /* ensure FIFO is empty before waiting for idle */ 577 /* ensure FIFO is empty before waiting for idle */
583 radeon_fifo_update_and_wait (rinfo, 64); 578 _radeon_fifo_wait (rinfo, 64);
584 579
585 for (i=0; i<2000000; i++) { 580 for (i=0; i<2000000; i++) {
586 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) { 581 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
@@ -593,6 +588,8 @@ static inline void radeon_engine_idle(struct radeonfb_info *rinfo)
593} 588}
594 589
595 590
591#define radeon_engine_idle() _radeon_engine_idle(rinfo)
592#define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries)
596#define radeon_msleep(ms) _radeon_msleep(rinfo,ms) 593#define radeon_msleep(ms) _radeon_msleep(rinfo,ms)
597 594
598 595
@@ -622,7 +619,6 @@ extern void radeonfb_imageblit(struct fb_info *p, const struct fb_image *image);
622extern int radeonfb_sync(struct fb_info *info); 619extern int radeonfb_sync(struct fb_info *info);
623extern void radeonfb_engine_init (struct radeonfb_info *rinfo); 620extern void radeonfb_engine_init (struct radeonfb_info *rinfo);
624extern void radeonfb_engine_reset(struct radeonfb_info *rinfo); 621extern void radeonfb_engine_reset(struct radeonfb_info *rinfo);
625extern void radeon_fixup_mem_offset(struct radeonfb_info *rinfo);
626 622
627/* Other functions */ 623/* Other functions */
628extern int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch); 624extern int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch);
@@ -638,6 +634,4 @@ static inline void radeonfb_bl_init(struct radeonfb_info *rinfo) {}
638static inline void radeonfb_bl_exit(struct radeonfb_info *rinfo) {} 634static inline void radeonfb_bl_exit(struct radeonfb_info *rinfo) {}
639#endif 635#endif
640 636
641extern int accel_cexp;
642
643#endif /* __RADEONFB_H__ */ 637#endif /* __RADEONFB_H__ */
diff --git a/drivers/video/imxfb.c b/drivers/video/imxfb.c
index ccd986140c9..d58c68cd456 100644
--- a/drivers/video/imxfb.c
+++ b/drivers/video/imxfb.c
@@ -1,6 +1,4 @@
1/* 1/*
2 * linux/drivers/video/imxfb.c
3 *
4 * Freescale i.MX Frame Buffer device driver 2 * Freescale i.MX Frame Buffer device driver
5 * 3 *
6 * Copyright (C) 2004 Sascha Hauer, Pengutronix 4 * Copyright (C) 2004 Sascha Hauer, Pengutronix
@@ -16,7 +14,6 @@
16 * linux-arm-kernel@lists.arm.linux.org.uk 14 * linux-arm-kernel@lists.arm.linux.org.uk
17 */ 15 */
18 16
19//#define DEBUG 1
20 17
21#include <linux/module.h> 18#include <linux/module.h>
22#include <linux/kernel.h> 19#include <linux/kernel.h>
@@ -32,9 +29,8 @@
32#include <linux/cpufreq.h> 29#include <linux/cpufreq.h>
33#include <linux/platform_device.h> 30#include <linux/platform_device.h>
34#include <linux/dma-mapping.h> 31#include <linux/dma-mapping.h>
32#include <linux/io.h>
35 33
36#include <mach/hardware.h>
37#include <asm/io.h>
38#include <mach/imxfb.h> 34#include <mach/imxfb.h>
39 35
40/* 36/*
@@ -42,23 +38,150 @@
42 */ 38 */
43#define DEBUG_VAR 1 39#define DEBUG_VAR 1
44 40
45#include "imxfb.h" 41#define DRIVER_NAME "imx-fb"
42
43#define LCDC_SSA 0x00
44
45#define LCDC_SIZE 0x04
46#define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20)
47#define SIZE_YMAX(y) ((y) & 0x1ff)
48
49#define LCDC_VPW 0x08
50#define VPW_VPW(x) ((x) & 0x3ff)
51
52#define LCDC_CPOS 0x0C
53#define CPOS_CC1 (1<<31)
54#define CPOS_CC0 (1<<30)
55#define CPOS_OP (1<<28)
56#define CPOS_CXP(x) (((x) & 3ff) << 16)
57#define CPOS_CYP(y) ((y) & 0x1ff)
58
59#define LCDC_LCWHB 0x10
60#define LCWHB_BK_EN (1<<31)
61#define LCWHB_CW(w) (((w) & 0x1f) << 24)
62#define LCWHB_CH(h) (((h) & 0x1f) << 16)
63#define LCWHB_BD(x) ((x) & 0xff)
64
65#define LCDC_LCHCC 0x14
66#define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11)
67#define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5)
68#define LCHCC_CUR_COL_B(b) ((b) & 0x1f)
69
70#define LCDC_PCR 0x18
71
72#define LCDC_HCR 0x1C
73#define HCR_H_WIDTH(x) (((x) & 0x3f) << 26)
74#define HCR_H_WAIT_1(x) (((x) & 0xff) << 8)
75#define HCR_H_WAIT_2(x) ((x) & 0xff)
76
77#define LCDC_VCR 0x20
78#define VCR_V_WIDTH(x) (((x) & 0x3f) << 26)
79#define VCR_V_WAIT_1(x) (((x) & 0xff) << 8)
80#define VCR_V_WAIT_2(x) ((x) & 0xff)
81
82#define LCDC_POS 0x24
83#define POS_POS(x) ((x) & 1f)
84
85#define LCDC_LSCR1 0x28
86/* bit fields in imxfb.h */
87
88#define LCDC_PWMR 0x2C
89/* bit fields in imxfb.h */
90
91#define LCDC_DMACR 0x30
92/* bit fields in imxfb.h */
93
94#define LCDC_RMCR 0x34
95#define RMCR_LCDC_EN (1<<1)
96#define RMCR_SELF_REF (1<<0)
97
98#define LCDC_LCDICR 0x38
99#define LCDICR_INT_SYN (1<<2)
100#define LCDICR_INT_CON (1)
101
102#define LCDC_LCDISR 0x40
103#define LCDISR_UDR_ERR (1<<3)
104#define LCDISR_ERR_RES (1<<2)
105#define LCDISR_EOF (1<<1)
106#define LCDISR_BOF (1<<0)
107
108/*
109 * These are the bitfields for each
110 * display depth that we support.
111 */
112struct imxfb_rgb {
113 struct fb_bitfield red;
114 struct fb_bitfield green;
115 struct fb_bitfield blue;
116 struct fb_bitfield transp;
117};
118
119struct imxfb_info {
120 struct platform_device *pdev;
121 void __iomem *regs;
46 122
47static struct imxfb_rgb def_rgb_16 = { 123 u_int max_bpp;
48 .red = { .offset = 8, .length = 4, }, 124 u_int max_xres;
49 .green = { .offset = 4, .length = 4, }, 125 u_int max_yres;
50 .blue = { .offset = 0, .length = 4, }, 126
51 .transp = { .offset = 0, .length = 0, }, 127 /*
128 * These are the addresses we mapped
129 * the framebuffer memory region to.
130 */
131 dma_addr_t map_dma;
132 u_char *map_cpu;
133 u_int map_size;
134
135 u_char *screen_cpu;
136 dma_addr_t screen_dma;
137 u_int palette_size;
138
139 dma_addr_t dbar1;
140 dma_addr_t dbar2;
141
142 u_int pcr;
143 u_int pwmr;
144 u_int lscr1;
145 u_int dmacr;
146 u_int cmap_inverse:1,
147 cmap_static:1,
148 unused:30;
149
150 void (*lcd_power)(int);
151 void (*backlight_power)(int);
152};
153
154#define IMX_NAME "IMX"
155
156/*
157 * Minimum X and Y resolutions
158 */
159#define MIN_XRES 64
160#define MIN_YRES 64
161
162static struct imxfb_rgb def_rgb_16_tft = {
163 .red = {.offset = 11, .length = 5,},
164 .green = {.offset = 5, .length = 6,},
165 .blue = {.offset = 0, .length = 5,},
166 .transp = {.offset = 0, .length = 0,},
167};
168
169static struct imxfb_rgb def_rgb_16_stn = {
170 .red = {.offset = 8, .length = 4,},
171 .green = {.offset = 4, .length = 4,},
172 .blue = {.offset = 0, .length = 4,},
173 .transp = {.offset = 0, .length = 0,},
52}; 174};
53 175
54static struct imxfb_rgb def_rgb_8 = { 176static struct imxfb_rgb def_rgb_8 = {
55 .red = { .offset = 0, .length = 8, }, 177 .red = {.offset = 0, .length = 8,},
56 .green = { .offset = 0, .length = 8, }, 178 .green = {.offset = 0, .length = 8,},
57 .blue = { .offset = 0, .length = 8, }, 179 .blue = {.offset = 0, .length = 8,},
58 .transp = { .offset = 0, .length = 0, }, 180 .transp = {.offset = 0, .length = 0,},
59}; 181};
60 182
61static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *info); 183static int imxfb_activate_var(struct fb_var_screeninfo *var,
184 struct fb_info *info);
62 185
63static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf) 186static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
64{ 187{
@@ -67,10 +190,8 @@ static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
67 return chan << bf->offset; 190 return chan << bf->offset;
68} 191}
69 192
70#define LCDC_PALETTE(x) __REG2(IMX_LCDC_BASE+0x800, (x)<<2) 193static int imxfb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
71static int 194 u_int trans, struct fb_info *info)
72imxfb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
73 u_int trans, struct fb_info *info)
74{ 195{
75 struct imxfb_info *fbi = info->par; 196 struct imxfb_info *fbi = info->par;
76 u_int val, ret = 1; 197 u_int val, ret = 1;
@@ -81,14 +202,13 @@ imxfb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
81 (CNVT_TOHW(green,4) << 4) | 202 (CNVT_TOHW(green,4) << 4) |
82 CNVT_TOHW(blue, 4); 203 CNVT_TOHW(blue, 4);
83 204
84 LCDC_PALETTE(regno) = val; 205 writel(val, fbi->regs + 0x800 + (regno << 2));
85 ret = 0; 206 ret = 0;
86 } 207 }
87 return ret; 208 return ret;
88} 209}
89 210
90static int 211static int imxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
91imxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
92 u_int trans, struct fb_info *info) 212 u_int trans, struct fb_info *info)
93{ 213{
94 struct imxfb_info *fbi = info->par; 214 struct imxfb_info *fbi = info->par;
@@ -148,11 +268,10 @@ imxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
148 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale, 268 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
149 * bitfields, horizontal timing, vertical timing. 269 * bitfields, horizontal timing, vertical timing.
150 */ 270 */
151static int 271static int imxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
152imxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
153{ 272{
154 struct imxfb_info *fbi = info->par; 273 struct imxfb_info *fbi = info->par;
155 int rgbidx; 274 struct imxfb_rgb *rgb;
156 275
157 if (var->xres < MIN_XRES) 276 if (var->xres < MIN_XRES)
158 var->xres = MIN_XRES; 277 var->xres = MIN_XRES;
@@ -168,23 +287,25 @@ imxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
168 pr_debug("var->bits_per_pixel=%d\n", var->bits_per_pixel); 287 pr_debug("var->bits_per_pixel=%d\n", var->bits_per_pixel);
169 switch (var->bits_per_pixel) { 288 switch (var->bits_per_pixel) {
170 case 16: 289 case 16:
171 rgbidx = RGB_16; 290 default:
291 if (readl(fbi->regs + LCDC_PCR) & PCR_TFT)
292 rgb = &def_rgb_16_tft;
293 else
294 rgb = &def_rgb_16_stn;
172 break; 295 break;
173 case 8: 296 case 8:
174 rgbidx = RGB_8; 297 rgb = &def_rgb_8;
175 break; 298 break;
176 default:
177 rgbidx = RGB_16;
178 } 299 }
179 300
180 /* 301 /*
181 * Copy the RGB parameters for this display 302 * Copy the RGB parameters for this display
182 * from the machine specific parameters. 303 * from the machine specific parameters.
183 */ 304 */
184 var->red = fbi->rgb[rgbidx]->red; 305 var->red = rgb->red;
185 var->green = fbi->rgb[rgbidx]->green; 306 var->green = rgb->green;
186 var->blue = fbi->rgb[rgbidx]->blue; 307 var->blue = rgb->blue;
187 var->transp = fbi->rgb[rgbidx]->transp; 308 var->transp = rgb->transp;
188 309
189 pr_debug("RGBT length = %d:%d:%d:%d\n", 310 pr_debug("RGBT length = %d:%d:%d:%d\n",
190 var->red.length, var->green.length, var->blue.length, 311 var->red.length, var->green.length, var->blue.length,
@@ -221,8 +342,7 @@ static int imxfb_set_par(struct fb_info *info)
221 info->fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR; 342 info->fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
222 } 343 }
223 344
224 info->fix.line_length = var->xres_virtual * 345 info->fix.line_length = var->xres_virtual * var->bits_per_pixel / 8;
225 var->bits_per_pixel / 8;
226 fbi->palette_size = var->bits_per_pixel == 8 ? 256 : 16; 346 fbi->palette_size = var->bits_per_pixel == 8 ? 256 : 16;
227 347
228 imxfb_activate_var(var, info); 348 imxfb_activate_var(var, info);
@@ -235,22 +355,27 @@ static void imxfb_enable_controller(struct imxfb_info *fbi)
235 pr_debug("Enabling LCD controller\n"); 355 pr_debug("Enabling LCD controller\n");
236 356
237 /* initialize LCDC */ 357 /* initialize LCDC */
238 LCDC_RMCR &= ~RMCR_LCDC_EN; /* just to be safe... */ 358 writel(readl(fbi->regs + LCDC_RMCR) & ~RMCR_LCDC_EN,
359 fbi->regs + LCDC_RMCR); /* just to be safe... */
360
361 writel(fbi->screen_dma, fbi->regs + LCDC_SSA);
239 362
240 LCDC_SSA = fbi->screen_dma;
241 /* physical screen start address */ 363 /* physical screen start address */
242 LCDC_VPW = VPW_VPW(fbi->max_xres * fbi->max_bpp / 8 / 4); 364 writel(VPW_VPW(fbi->max_xres * fbi->max_bpp / 8 / 4),
365 fbi->regs + LCDC_VPW);
243 366
244 LCDC_POS = 0x00000000; /* panning offset 0 (0 pixel offset) */ 367 /* panning offset 0 (0 pixel offset) */
368 writel(0x00000000, fbi->regs + LCDC_POS);
245 369
246 /* disable hardware cursor */ 370 /* disable hardware cursor */
247 LCDC_CPOS &= ~(CPOS_CC0 | CPOS_CC1); 371 writel(readl(fbi->regs + LCDC_CPOS) & ~(CPOS_CC0 | CPOS_CC1),
372 fbi->regs + LCDC_CPOS);
248 373
249 LCDC_RMCR = RMCR_LCDC_EN; 374 writel(RMCR_LCDC_EN, fbi->regs + LCDC_RMCR);
250 375
251 if(fbi->backlight_power) 376 if (fbi->backlight_power)
252 fbi->backlight_power(1); 377 fbi->backlight_power(1);
253 if(fbi->lcd_power) 378 if (fbi->lcd_power)
254 fbi->lcd_power(1); 379 fbi->lcd_power(1);
255} 380}
256 381
@@ -258,12 +383,12 @@ static void imxfb_disable_controller(struct imxfb_info *fbi)
258{ 383{
259 pr_debug("Disabling LCD controller\n"); 384 pr_debug("Disabling LCD controller\n");
260 385
261 if(fbi->backlight_power) 386 if (fbi->backlight_power)
262 fbi->backlight_power(0); 387 fbi->backlight_power(0);
263 if(fbi->lcd_power) 388 if (fbi->lcd_power)
264 fbi->lcd_power(0); 389 fbi->lcd_power(0);
265 390
266 LCDC_RMCR = 0; 391 writel(0, fbi->regs + LCDC_RMCR);
267} 392}
268 393
269static int imxfb_blank(int blank, struct fb_info *info) 394static int imxfb_blank(int blank, struct fb_info *info)
@@ -340,74 +465,26 @@ static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *inf
340 info->fix.id, var->lower_margin); 465 info->fix.id, var->lower_margin);
341#endif 466#endif
342 467
343 LCDC_HCR = HCR_H_WIDTH(var->hsync_len) | 468 writel(HCR_H_WIDTH(var->hsync_len) |
344 HCR_H_WAIT_1(var->left_margin) | 469 HCR_H_WAIT_1(var->right_margin) |
345 HCR_H_WAIT_2(var->right_margin); 470 HCR_H_WAIT_2(var->left_margin),
471 fbi->regs + LCDC_HCR);
346 472
347 LCDC_VCR = VCR_V_WIDTH(var->vsync_len) | 473 writel(VCR_V_WIDTH(var->vsync_len) |
348 VCR_V_WAIT_1(var->upper_margin) | 474 VCR_V_WAIT_1(var->lower_margin) |
349 VCR_V_WAIT_2(var->lower_margin); 475 VCR_V_WAIT_2(var->upper_margin),
476 fbi->regs + LCDC_VCR);
350 477
351 LCDC_SIZE = SIZE_XMAX(var->xres) | SIZE_YMAX(var->yres); 478 writel(SIZE_XMAX(var->xres) | SIZE_YMAX(var->yres),
352 LCDC_PCR = fbi->pcr; 479 fbi->regs + LCDC_SIZE);
353 LCDC_PWMR = fbi->pwmr; 480 writel(fbi->pcr, fbi->regs + LCDC_PCR);
354 LCDC_LSCR1 = fbi->lscr1; 481 writel(fbi->pwmr, fbi->regs + LCDC_PWMR);
355 LCDC_DMACR = fbi->dmacr; 482 writel(fbi->lscr1, fbi->regs + LCDC_LSCR1);
483 writel(fbi->dmacr, fbi->regs + LCDC_DMACR);
356 484
357 return 0; 485 return 0;
358} 486}
359 487
360static void imxfb_setup_gpio(struct imxfb_info *fbi)
361{
362 int width;
363
364 LCDC_RMCR &= ~(RMCR_LCDC_EN | RMCR_SELF_REF);
365
366 if( fbi->pcr & PCR_TFT )
367 width = 16;
368 else
369 width = 1 << ((fbi->pcr >> 28) & 0x3);
370
371 switch(width) {
372 case 16:
373 imx_gpio_mode(PD30_PF_LD15);
374 imx_gpio_mode(PD29_PF_LD14);
375 imx_gpio_mode(PD28_PF_LD13);
376 imx_gpio_mode(PD27_PF_LD12);
377 imx_gpio_mode(PD26_PF_LD11);
378 imx_gpio_mode(PD25_PF_LD10);
379 imx_gpio_mode(PD24_PF_LD9);
380 imx_gpio_mode(PD23_PF_LD8);
381 case 8:
382 imx_gpio_mode(PD22_PF_LD7);
383 imx_gpio_mode(PD21_PF_LD6);
384 imx_gpio_mode(PD20_PF_LD5);
385 imx_gpio_mode(PD19_PF_LD4);
386 case 4:
387 imx_gpio_mode(PD18_PF_LD3);
388 imx_gpio_mode(PD17_PF_LD2);
389 case 2:
390 imx_gpio_mode(PD16_PF_LD1);
391 case 1:
392 imx_gpio_mode(PD15_PF_LD0);
393 }
394
395 /* initialize GPIOs */
396 imx_gpio_mode(PD6_PF_LSCLK);
397 imx_gpio_mode(PD11_PF_CONTRAST);
398 imx_gpio_mode(PD14_PF_FLM_VSYNC);
399 imx_gpio_mode(PD13_PF_LP_HSYNC);
400 imx_gpio_mode(PD12_PF_ACD_OE);
401
402 /* These are only needed for Sharp HR TFT displays */
403 if (fbi->pcr & PCR_SHARP) {
404 imx_gpio_mode(PD7_PF_REV);
405 imx_gpio_mode(PD8_PF_CLS);
406 imx_gpio_mode(PD9_PF_PS);
407 imx_gpio_mode(PD10_PF_SPL_SPR);
408 }
409}
410
411#ifdef CONFIG_PM 488#ifdef CONFIG_PM
412/* 489/*
413 * Power management hooks. Note that we won't be called from IRQ context, 490 * Power management hooks. Note that we won't be called from IRQ context,
@@ -416,7 +493,8 @@ static void imxfb_setup_gpio(struct imxfb_info *fbi)
416static int imxfb_suspend(struct platform_device *dev, pm_message_t state) 493static int imxfb_suspend(struct platform_device *dev, pm_message_t state)
417{ 494{
418 struct imxfb_info *fbi = platform_get_drvdata(dev); 495 struct imxfb_info *fbi = platform_get_drvdata(dev);
419 pr_debug("%s\n",__func__); 496
497 pr_debug("%s\n", __func__);
420 498
421 imxfb_disable_controller(fbi); 499 imxfb_disable_controller(fbi);
422 return 0; 500 return 0;
@@ -425,7 +503,8 @@ static int imxfb_suspend(struct platform_device *dev, pm_message_t state)
425static int imxfb_resume(struct platform_device *dev) 503static int imxfb_resume(struct platform_device *dev)
426{ 504{
427 struct imxfb_info *fbi = platform_get_drvdata(dev); 505 struct imxfb_info *fbi = platform_get_drvdata(dev);
428 pr_debug("%s\n",__func__); 506
507 pr_debug("%s\n", __func__);
429 508
430 imxfb_enable_controller(fbi); 509 imxfb_enable_controller(fbi);
431 return 0; 510 return 0;
@@ -435,149 +514,136 @@ static int imxfb_resume(struct platform_device *dev)
435#define imxfb_resume NULL 514#define imxfb_resume NULL
436#endif 515#endif
437 516
438static int __init imxfb_init_fbinfo(struct device *dev) 517static int __init imxfb_init_fbinfo(struct platform_device *pdev)
439{ 518{
440 struct imxfb_mach_info *inf = dev->platform_data; 519 struct imx_fb_platform_data *pdata = pdev->dev.platform_data;
441 struct fb_info *info = dev_get_drvdata(dev); 520 struct fb_info *info = dev_get_drvdata(&pdev->dev);
442 struct imxfb_info *fbi = info->par; 521 struct imxfb_info *fbi = info->par;
443 522
444 pr_debug("%s\n",__func__); 523 pr_debug("%s\n",__func__);
445 524
446 info->pseudo_palette = kmalloc( sizeof(u32) * 16, GFP_KERNEL); 525 info->pseudo_palette = kmalloc(sizeof(u32) * 16, GFP_KERNEL);
447 if (!info->pseudo_palette) 526 if (!info->pseudo_palette)
448 return -ENOMEM; 527 return -ENOMEM;
449 528
450 memset(fbi, 0, sizeof(struct imxfb_info)); 529 memset(fbi, 0, sizeof(struct imxfb_info));
451 fbi->dev = dev;
452 530
453 strlcpy(info->fix.id, IMX_NAME, sizeof(info->fix.id)); 531 strlcpy(info->fix.id, IMX_NAME, sizeof(info->fix.id));
454 532
455 info->fix.type = FB_TYPE_PACKED_PIXELS; 533 info->fix.type = FB_TYPE_PACKED_PIXELS;
456 info->fix.type_aux = 0; 534 info->fix.type_aux = 0;
457 info->fix.xpanstep = 0; 535 info->fix.xpanstep = 0;
458 info->fix.ypanstep = 0; 536 info->fix.ypanstep = 0;
459 info->fix.ywrapstep = 0; 537 info->fix.ywrapstep = 0;
460 info->fix.accel = FB_ACCEL_NONE; 538 info->fix.accel = FB_ACCEL_NONE;
461 539
462 info->var.nonstd = 0; 540 info->var.nonstd = 0;
463 info->var.activate = FB_ACTIVATE_NOW; 541 info->var.activate = FB_ACTIVATE_NOW;
464 info->var.height = -1; 542 info->var.height = -1;
465 info->var.width = -1; 543 info->var.width = -1;
466 info->var.accel_flags = 0; 544 info->var.accel_flags = 0;
467 info->var.vmode = FB_VMODE_NONINTERLACED; 545 info->var.vmode = FB_VMODE_NONINTERLACED;
468 546
469 info->fbops = &imxfb_ops; 547 info->fbops = &imxfb_ops;
470 info->flags = FBINFO_FLAG_DEFAULT | FBINFO_READS_FAST; 548 info->flags = FBINFO_FLAG_DEFAULT |
471 549 FBINFO_READS_FAST;
472 fbi->rgb[RGB_16] = &def_rgb_16; 550
473 fbi->rgb[RGB_8] = &def_rgb_8; 551 fbi->max_xres = pdata->xres;
474 552 info->var.xres = pdata->xres;
475 fbi->max_xres = inf->xres; 553 info->var.xres_virtual = pdata->xres;
476 info->var.xres = inf->xres; 554 fbi->max_yres = pdata->yres;
477 info->var.xres_virtual = inf->xres; 555 info->var.yres = pdata->yres;
478 fbi->max_yres = inf->yres; 556 info->var.yres_virtual = pdata->yres;
479 info->var.yres = inf->yres; 557 fbi->max_bpp = pdata->bpp;
480 info->var.yres_virtual = inf->yres; 558 info->var.bits_per_pixel = pdata->bpp;
481 fbi->max_bpp = inf->bpp; 559 info->var.nonstd = pdata->nonstd;
482 info->var.bits_per_pixel = inf->bpp; 560 info->var.pixclock = pdata->pixclock;
483 info->var.nonstd = inf->nonstd; 561 info->var.hsync_len = pdata->hsync_len;
484 info->var.pixclock = inf->pixclock; 562 info->var.left_margin = pdata->left_margin;
485 info->var.hsync_len = inf->hsync_len; 563 info->var.right_margin = pdata->right_margin;
486 info->var.left_margin = inf->left_margin; 564 info->var.vsync_len = pdata->vsync_len;
487 info->var.right_margin = inf->right_margin; 565 info->var.upper_margin = pdata->upper_margin;
488 info->var.vsync_len = inf->vsync_len; 566 info->var.lower_margin = pdata->lower_margin;
489 info->var.upper_margin = inf->upper_margin; 567 info->var.sync = pdata->sync;
490 info->var.lower_margin = inf->lower_margin; 568 info->var.grayscale = pdata->cmap_greyscale;
491 info->var.sync = inf->sync; 569 fbi->cmap_inverse = pdata->cmap_inverse;
492 info->var.grayscale = inf->cmap_greyscale; 570 fbi->cmap_static = pdata->cmap_static;
493 fbi->cmap_inverse = inf->cmap_inverse; 571 fbi->pcr = pdata->pcr;
494 fbi->cmap_static = inf->cmap_static; 572 fbi->lscr1 = pdata->lscr1;
495 fbi->pcr = inf->pcr; 573 fbi->dmacr = pdata->dmacr;
496 fbi->lscr1 = inf->lscr1; 574 fbi->pwmr = pdata->pwmr;
497 fbi->dmacr = inf->dmacr; 575 fbi->lcd_power = pdata->lcd_power;
498 fbi->pwmr = inf->pwmr; 576 fbi->backlight_power = pdata->backlight_power;
499 fbi->lcd_power = inf->lcd_power;
500 fbi->backlight_power = inf->backlight_power;
501 info->fix.smem_len = fbi->max_xres * fbi->max_yres * 577 info->fix.smem_len = fbi->max_xres * fbi->max_yres *
502 fbi->max_bpp / 8; 578 fbi->max_bpp / 8;
503 579
504 return 0; 580 return 0;
505} 581}
506 582
507/*
508 * Allocates the DRAM memory for the frame buffer. This buffer is
509 * remapped into a non-cached, non-buffered, memory region to
510 * allow pixel writes to occur without flushing the cache.
511 * Once this area is remapped, all virtual memory access to the
512 * video memory should occur at the new region.
513 */
514static int __init imxfb_map_video_memory(struct fb_info *info)
515{
516 struct imxfb_info *fbi = info->par;
517
518 fbi->map_size = PAGE_ALIGN(info->fix.smem_len);
519 fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
520 &fbi->map_dma,GFP_KERNEL);
521
522 if (fbi->map_cpu) {
523 info->screen_base = fbi->map_cpu;
524 fbi->screen_cpu = fbi->map_cpu;
525 fbi->screen_dma = fbi->map_dma;
526 info->fix.smem_start = fbi->screen_dma;
527 }
528
529 return fbi->map_cpu ? 0 : -ENOMEM;
530}
531
532static int __init imxfb_probe(struct platform_device *pdev) 583static int __init imxfb_probe(struct platform_device *pdev)
533{ 584{
534 struct imxfb_info *fbi; 585 struct imxfb_info *fbi;
535 struct fb_info *info; 586 struct fb_info *info;
536 struct imxfb_mach_info *inf; 587 struct imx_fb_platform_data *pdata;
537 struct resource *res; 588 struct resource *res;
538 int ret; 589 int ret;
539 590
540 printk("i.MX Framebuffer driver\n"); 591 printk("i.MX Framebuffer driver\n");
541 592
542 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 593 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
543 if(!res) 594 if (!res)
544 return -ENODEV; 595 return -ENODEV;
545 596
546 inf = pdev->dev.platform_data; 597 pdata = pdev->dev.platform_data;
547 if(!inf) { 598 if (!pdata) {
548 dev_err(&pdev->dev,"No platform_data available\n"); 599 dev_err(&pdev->dev,"No platform_data available\n");
549 return -ENOMEM; 600 return -ENOMEM;
550 } 601 }
551 602
552 info = framebuffer_alloc(sizeof(struct imxfb_info), &pdev->dev); 603 info = framebuffer_alloc(sizeof(struct imxfb_info), &pdev->dev);
553 if(!info) 604 if (!info)
554 return -ENOMEM; 605 return -ENOMEM;
555 606
556 fbi = info->par; 607 fbi = info->par;
557 608
558 platform_set_drvdata(pdev, info); 609 platform_set_drvdata(pdev, info);
559 610
560 ret = imxfb_init_fbinfo(&pdev->dev); 611 ret = imxfb_init_fbinfo(pdev);
561 if( ret < 0 ) 612 if (ret < 0)
562 goto failed_init; 613 goto failed_init;
563 614
564 res = request_mem_region(res->start, res->end - res->start + 1, "IMXFB"); 615 res = request_mem_region(res->start, resource_size(res),
616 DRIVER_NAME);
565 if (!res) { 617 if (!res) {
566 ret = -EBUSY; 618 ret = -EBUSY;
567 goto failed_regs; 619 goto failed_req;
620 }
621
622 fbi->regs = ioremap(res->start, resource_size(res));
623 if (fbi->regs == NULL) {
624 printk(KERN_ERR"Cannot map frame buffer registers\n");
625 goto failed_ioremap;
568 } 626 }
569 627
570 if (!inf->fixed_screen_cpu) { 628 if (!pdata->fixed_screen_cpu) {
571 ret = imxfb_map_video_memory(info); 629 fbi->map_size = PAGE_ALIGN(info->fix.smem_len);
572 if (ret) { 630 fbi->map_cpu = dma_alloc_writecombine(&pdev->dev,
631 fbi->map_size, &fbi->map_dma, GFP_KERNEL);
632
633 if (!fbi->map_cpu) {
573 dev_err(&pdev->dev, "Failed to allocate video RAM: %d\n", ret); 634 dev_err(&pdev->dev, "Failed to allocate video RAM: %d\n", ret);
574 ret = -ENOMEM; 635 ret = -ENOMEM;
575 goto failed_map; 636 goto failed_map;
576 } 637 }
638
639 info->screen_base = fbi->map_cpu;
640 fbi->screen_cpu = fbi->map_cpu;
641 fbi->screen_dma = fbi->map_dma;
642 info->fix.smem_start = fbi->screen_dma;
577 } else { 643 } else {
578 /* Fixed framebuffer mapping enables location of the screen in eSRAM */ 644 /* Fixed framebuffer mapping enables location of the screen in eSRAM */
579 fbi->map_cpu = inf->fixed_screen_cpu; 645 fbi->map_cpu = pdata->fixed_screen_cpu;
580 fbi->map_dma = inf->fixed_screen_dma; 646 fbi->map_dma = pdata->fixed_screen_dma;
581 info->screen_base = fbi->map_cpu; 647 info->screen_base = fbi->map_cpu;
582 fbi->screen_cpu = fbi->map_cpu; 648 fbi->screen_cpu = fbi->map_cpu;
583 fbi->screen_dma = fbi->map_dma; 649 fbi->screen_dma = fbi->map_dma;
@@ -590,12 +656,10 @@ static int __init imxfb_probe(struct platform_device *pdev)
590 */ 656 */
591 imxfb_check_var(&info->var, info); 657 imxfb_check_var(&info->var, info);
592 658
593 ret = fb_alloc_cmap(&info->cmap, 1<<info->var.bits_per_pixel, 0); 659 ret = fb_alloc_cmap(&info->cmap, 1 << info->var.bits_per_pixel, 0);
594 if (ret < 0) 660 if (ret < 0)
595 goto failed_cmap; 661 goto failed_cmap;
596 662
597 imxfb_setup_gpio(fbi);
598
599 imxfb_set_par(info); 663 imxfb_set_par(info);
600 ret = register_framebuffer(info); 664 ret = register_framebuffer(info);
601 if (ret < 0) { 665 if (ret < 0) {
@@ -610,20 +674,22 @@ static int __init imxfb_probe(struct platform_device *pdev)
610failed_register: 674failed_register:
611 fb_dealloc_cmap(&info->cmap); 675 fb_dealloc_cmap(&info->cmap);
612failed_cmap: 676failed_cmap:
613 if (!inf->fixed_screen_cpu) 677 if (!pdata->fixed_screen_cpu)
614 dma_free_writecombine(&pdev->dev,fbi->map_size,fbi->map_cpu, 678 dma_free_writecombine(&pdev->dev,fbi->map_size,fbi->map_cpu,
615 fbi->map_dma); 679 fbi->map_dma);
616failed_map: 680failed_map:
617 kfree(info->pseudo_palette); 681 iounmap(fbi->regs);
618failed_regs: 682failed_ioremap:
619 release_mem_region(res->start, res->end - res->start); 683 release_mem_region(res->start, res->end - res->start);
684failed_req:
685 kfree(info->pseudo_palette);
620failed_init: 686failed_init:
621 platform_set_drvdata(pdev, NULL); 687 platform_set_drvdata(pdev, NULL);
622 framebuffer_release(info); 688 framebuffer_release(info);
623 return ret; 689 return ret;
624} 690}
625 691
626static int imxfb_remove(struct platform_device *pdev) 692static int __devexit imxfb_remove(struct platform_device *pdev)
627{ 693{
628 struct fb_info *info = platform_get_drvdata(pdev); 694 struct fb_info *info = platform_get_drvdata(pdev);
629 struct imxfb_info *fbi = info->par; 695 struct imxfb_info *fbi = info->par;
@@ -639,6 +705,7 @@ static int imxfb_remove(struct platform_device *pdev)
639 kfree(info->pseudo_palette); 705 kfree(info->pseudo_palette);
640 framebuffer_release(info); 706 framebuffer_release(info);
641 707
708 iounmap(fbi->regs);
642 release_mem_region(res->start, res->end - res->start + 1); 709 release_mem_region(res->start, res->end - res->start + 1);
643 platform_set_drvdata(pdev, NULL); 710 platform_set_drvdata(pdev, NULL);
644 711
@@ -653,19 +720,18 @@ void imxfb_shutdown(struct platform_device * dev)
653} 720}
654 721
655static struct platform_driver imxfb_driver = { 722static struct platform_driver imxfb_driver = {
656 .probe = imxfb_probe,
657 .suspend = imxfb_suspend, 723 .suspend = imxfb_suspend,
658 .resume = imxfb_resume, 724 .resume = imxfb_resume,
659 .remove = imxfb_remove, 725 .remove = __devexit_p(imxfb_remove),
660 .shutdown = imxfb_shutdown, 726 .shutdown = imxfb_shutdown,
661 .driver = { 727 .driver = {
662 .name = "imx-fb", 728 .name = DRIVER_NAME,
663 }, 729 },
664}; 730};
665 731
666int __init imxfb_init(void) 732int __init imxfb_init(void)
667{ 733{
668 return platform_driver_register(&imxfb_driver); 734 return platform_driver_probe(&imxfb_driver, imxfb_probe);
669} 735}
670 736
671static void __exit imxfb_cleanup(void) 737static void __exit imxfb_cleanup(void)
diff --git a/drivers/video/imxfb.h b/drivers/video/imxfb.h
deleted file mode 100644
index e837a8b48eb..00000000000
--- a/drivers/video/imxfb.h
+++ /dev/null
@@ -1,73 +0,0 @@
1/*
2 * linux/drivers/video/imxfb.h
3 *
4 * Freescale i.MX Frame Buffer device driver
5 *
6 * Copyright (C) 2004 S.Hauer, Pengutronix
7 *
8 * Copyright (C) 1999 Eric A. Thomas
9 * Based on acornfb.c Copyright (C) Russell King.
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file COPYING in the main directory of this archive
13 * for more details.
14 */
15
16/*
17 * These are the bitfields for each
18 * display depth that we support.
19 */
20struct imxfb_rgb {
21 struct fb_bitfield red;
22 struct fb_bitfield green;
23 struct fb_bitfield blue;
24 struct fb_bitfield transp;
25};
26
27#define RGB_16 (0)
28#define RGB_8 (1)
29#define NR_RGB 2
30
31struct imxfb_info {
32 struct device *dev;
33 struct imxfb_rgb *rgb[NR_RGB];
34
35 u_int max_bpp;
36 u_int max_xres;
37 u_int max_yres;
38
39 /*
40 * These are the addresses we mapped
41 * the framebuffer memory region to.
42 */
43 dma_addr_t map_dma;
44 u_char * map_cpu;
45 u_int map_size;
46
47 u_char * screen_cpu;
48 dma_addr_t screen_dma;
49 u_int palette_size;
50
51 dma_addr_t dbar1;
52 dma_addr_t dbar2;
53
54 u_int pcr;
55 u_int pwmr;
56 u_int lscr1;
57 u_int dmacr;
58 u_int cmap_inverse:1,
59 cmap_static:1,
60 unused:30;
61
62 void (*lcd_power)(int);
63 void (*backlight_power)(int);
64};
65
66#define IMX_NAME "IMX"
67
68/*
69 * Minimum X and Y resolutions
70 */
71#define MIN_XRES 64
72#define MIN_YRES 64
73
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-19 16:35:49 -0500