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-rw-r--r--drivers/acpi/ac.c8
-rw-r--r--drivers/acpi/video.c3
-rw-r--r--drivers/ata/Kconfig10
-rw-r--r--drivers/ata/ahci.c23
-rw-r--r--drivers/ata/ata_piix.c7
-rw-r--r--drivers/ata/libata-core.c4
-rw-r--r--drivers/ata/libata-scsi.c16
-rw-r--r--drivers/ata/libata.h2
-rw-r--r--drivers/ata/pata_pcmcia.c2
-rw-r--r--drivers/ata/sata_mv.c21
-rw-r--r--drivers/atm/he.c11
-rw-r--r--drivers/atm/he.h13
-rw-r--r--drivers/atm/iphase.c27
-rw-r--r--drivers/char/agp/agp.h6
-rw-r--r--drivers/char/agp/alpha-agp.c4
-rw-r--r--drivers/char/agp/amd-k7-agp.c4
-rw-r--r--drivers/char/agp/amd64-agp.c4
-rw-r--r--drivers/char/agp/ati-agp.c4
-rw-r--r--drivers/char/agp/backend.c16
-rw-r--r--drivers/char/agp/compat_ioctl.c2
-rw-r--r--drivers/char/agp/efficeon-agp.c6
-rw-r--r--drivers/char/agp/frontend.c12
-rw-r--r--drivers/char/agp/generic.c35
-rw-r--r--drivers/char/agp/hp-agp.c6
-rw-r--r--drivers/char/agp/i460-agp.c2
-rw-r--r--drivers/char/agp/intel-agp.c239
-rw-r--r--drivers/char/agp/nvidia-agp.c4
-rw-r--r--drivers/char/agp/parisc-agp.c6
-rw-r--r--drivers/char/agp/sgi-agp.c8
-rw-r--r--drivers/char/agp/sworks-agp.c6
-rw-r--r--drivers/char/agp/uninorth-agp.c10
-rw-r--r--drivers/char/agp/via-agp.c13
-rw-r--r--drivers/char/drm/ati_pcigart.c8
-rw-r--r--drivers/char/drm/drm.h2
-rw-r--r--drivers/char/drm/drm_drv.c7
-rw-r--r--drivers/char/drm/drm_pciids.h17
-rw-r--r--drivers/char/drm/i915_drv.c1
-rw-r--r--drivers/char/drm/i915_drv.h11
-rw-r--r--drivers/char/drm/r300_cmdbuf.c117
-rw-r--r--drivers/char/drm/r300_reg.h242
-rw-r--r--drivers/char/drm/radeon_cp.c1148
-rw-r--r--drivers/char/drm/radeon_drm.h8
-rw-r--r--drivers/char/drm/radeon_drv.h251
-rw-r--r--drivers/char/drm/radeon_irq.c2
-rw-r--r--drivers/char/drm/radeon_microcode.h1844
-rw-r--r--drivers/char/drm/radeon_state.c17
-rw-r--r--drivers/char/tty_ioctl.c7
-rw-r--r--drivers/firewire/Kconfig32
-rw-r--r--drivers/firewire/fw-cdev.c9
-rw-r--r--drivers/firewire/fw-ohci.c110
-rw-r--r--drivers/firewire/fw-transaction.c52
-rw-r--r--drivers/hwmon/abituguru3.c18
-rw-r--r--drivers/hwmon/adt7473.c3
-rw-r--r--drivers/hwmon/lm75.c20
-rw-r--r--drivers/hwmon/lm85.c25
-rw-r--r--drivers/ide/Kconfig7
-rw-r--r--drivers/ide/arm/Makefile1
-rw-r--r--drivers/ide/arm/bast-ide.c90
-rw-r--r--drivers/ide/arm/palm_bk3710.c22
-rw-r--r--drivers/ide/ide-taskfile.c6
-rw-r--r--drivers/ide/legacy/ide-cs.c3
-rw-r--r--drivers/ieee1394/Kconfig118
-rw-r--r--drivers/infiniband/core/uverbs_main.c2
-rw-r--r--drivers/infiniband/hw/mthca/mthca_memfree.c6
-rw-r--r--drivers/infiniband/hw/nes/nes_verbs.c4
-rw-r--r--drivers/input/misc/Kconfig1
-rw-r--r--drivers/input/mouse/appletouch.c49
-rw-r--r--drivers/input/serio/i8042-x86ia64io.h7
-rw-r--r--drivers/input/serio/i8042.c8
-rw-r--r--drivers/lguest/x86/core.c15
-rw-r--r--drivers/macintosh/mediabay.c4
-rw-r--r--drivers/macintosh/smu.c5
-rw-r--r--drivers/macintosh/therm_adt746x.c13
-rw-r--r--drivers/net/atlx/atl1.c1
-rw-r--r--drivers/net/enc28j60.c87
-rw-r--r--drivers/net/ibm_newemac/Kconfig1
-rw-r--r--drivers/net/netxen/netxen_nic.h18
-rw-r--r--drivers/net/netxen/netxen_nic_ethtool.c6
-rw-r--r--drivers/net/netxen/netxen_nic_hw.c112
-rw-r--r--drivers/net/netxen/netxen_nic_init.c46
-rw-r--r--drivers/net/netxen/netxen_nic_isr.c4
-rw-r--r--drivers/net/netxen/netxen_nic_main.c133
-rw-r--r--drivers/net/netxen/netxen_nic_niu.c22
-rw-r--r--drivers/net/pppoe.c2
-rw-r--r--drivers/net/sky2.c1
-rw-r--r--drivers/net/tun.c15
-rw-r--r--drivers/net/wireless/b43/b43.h1
-rw-r--r--drivers/net/wireless/b43/dma.c65
-rw-r--r--drivers/net/wireless/b43/main.c16
-rw-r--r--drivers/net/wireless/rt2x00/Kconfig19
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00pci.c3
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00usb.c6
-rw-r--r--drivers/net/wireless/rt2x00/rt73usb.c1
-rw-r--r--drivers/scsi/dpt/dptsig.h3
-rw-r--r--drivers/scsi/hosts.c9
-rw-r--r--drivers/scsi/sr.c3
-rw-r--r--drivers/serial/bfin_5xx.c40
-rw-r--r--drivers/ssb/main.c12
-rw-r--r--drivers/usb/core/quirks.c3
-rw-r--r--drivers/watchdog/hpwdt.c182
-rw-r--r--drivers/xen/events.c2
101 files changed, 3669 insertions, 1990 deletions
diff --git a/drivers/acpi/ac.c b/drivers/acpi/ac.c
index 5b73f6a2cd8..831883b7d6c 100644
--- a/drivers/acpi/ac.c
+++ b/drivers/acpi/ac.c
@@ -233,6 +233,9 @@ static void acpi_ac_notify(acpi_handle handle, u32 event, void *data)
233 233
234 device = ac->device; 234 device = ac->device;
235 switch (event) { 235 switch (event) {
236 default:
237 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
238 "Unsupported event [0x%x]\n", event));
236 case ACPI_AC_NOTIFY_STATUS: 239 case ACPI_AC_NOTIFY_STATUS:
237 case ACPI_NOTIFY_BUS_CHECK: 240 case ACPI_NOTIFY_BUS_CHECK:
238 case ACPI_NOTIFY_DEVICE_CHECK: 241 case ACPI_NOTIFY_DEVICE_CHECK:
@@ -244,11 +247,6 @@ static void acpi_ac_notify(acpi_handle handle, u32 event, void *data)
244#ifdef CONFIG_ACPI_SYSFS_POWER 247#ifdef CONFIG_ACPI_SYSFS_POWER
245 kobject_uevent(&ac->charger.dev->kobj, KOBJ_CHANGE); 248 kobject_uevent(&ac->charger.dev->kobj, KOBJ_CHANGE);
246#endif 249#endif
247 break;
248 default:
249 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
250 "Unsupported event [0x%x]\n", event));
251 break;
252 } 250 }
253 251
254 return; 252 return;
diff --git a/drivers/acpi/video.c b/drivers/acpi/video.c
index 5e5dda3a302..d089c4519d4 100644
--- a/drivers/acpi/video.c
+++ b/drivers/acpi/video.c
@@ -1713,7 +1713,8 @@ acpi_video_bus_get_devices(struct acpi_video_bus *video,
1713 1713
1714 status = acpi_video_bus_get_one_device(dev, video); 1714 status = acpi_video_bus_get_one_device(dev, video);
1715 if (ACPI_FAILURE(status)) { 1715 if (ACPI_FAILURE(status)) {
1716 ACPI_EXCEPTION((AE_INFO, status, "Cant attach device")); 1716 ACPI_DEBUG_PRINT((ACPI_DB_WARN,
1717 "Cant attach device"));
1717 continue; 1718 continue;
1718 } 1719 }
1719 } 1720 }
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 9bf2986a278..ae8494944c4 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -651,9 +651,17 @@ config PATA_WINBOND_VLB
651 Support for the Winbond W83759A controller on Vesa Local Bus 651 Support for the Winbond W83759A controller on Vesa Local Bus
652 systems. 652 systems.
653 653
654config HAVE_PATA_PLATFORM
655 bool
656 help
657 This is an internal configuration node for any machine that
658 uses pata-platform driver to enable the relevant driver in the
659 configuration structure without having to submit endless patches
660 to update the PATA_PLATFORM entry.
661
654config PATA_PLATFORM 662config PATA_PLATFORM
655 tristate "Generic platform device PATA support" 663 tristate "Generic platform device PATA support"
656 depends on EMBEDDED || ARCH_RPC || PPC 664 depends on EMBEDDED || ARCH_RPC || PPC || HAVE_PATA_PLATFORM
657 help 665 help
658 This option enables support for generic directly connected ATA 666 This option enables support for generic directly connected ATA
659 devices commonly found on embedded systems. 667 devices commonly found on embedded systems.
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 966ab401e52..6a4a2a25d97 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -90,6 +90,7 @@ enum {
90 board_ahci_mv = 4, 90 board_ahci_mv = 4,
91 board_ahci_sb700 = 5, 91 board_ahci_sb700 = 5,
92 board_ahci_mcp65 = 6, 92 board_ahci_mcp65 = 6,
93 board_ahci_nopmp = 7,
93 94
94 /* global controller registers */ 95 /* global controller registers */
95 HOST_CAP = 0x00, /* host capabilities */ 96 HOST_CAP = 0x00, /* host capabilities */
@@ -401,6 +402,14 @@ static const struct ata_port_info ahci_port_info[] = {
401 .udma_mask = ATA_UDMA6, 402 .udma_mask = ATA_UDMA6,
402 .port_ops = &ahci_ops, 403 .port_ops = &ahci_ops,
403 }, 404 },
405 /* board_ahci_nopmp */
406 {
407 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP),
408 .flags = AHCI_FLAG_COMMON,
409 .pio_mask = 0x1f, /* pio0-4 */
410 .udma_mask = ATA_UDMA6,
411 .port_ops = &ahci_ops,
412 },
404}; 413};
405 414
406static const struct pci_device_id ahci_pci_tbl[] = { 415static const struct pci_device_id ahci_pci_tbl[] = {
@@ -525,9 +534,9 @@ static const struct pci_device_id ahci_pci_tbl[] = {
525 { PCI_VDEVICE(NVIDIA, 0x0bc7), board_ahci }, /* MCP7B */ 534 { PCI_VDEVICE(NVIDIA, 0x0bc7), board_ahci }, /* MCP7B */
526 535
527 /* SiS */ 536 /* SiS */
528 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ 537 { PCI_VDEVICE(SI, 0x1184), board_ahci_nopmp }, /* SiS 966 */
529 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */ 538 { PCI_VDEVICE(SI, 0x1185), board_ahci_nopmp }, /* SiS 968 */
530 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ 539 { PCI_VDEVICE(SI, 0x0186), board_ahci_nopmp }, /* SiS 968 */
531 540
532 /* Marvell */ 541 /* Marvell */
533 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ 542 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
@@ -653,6 +662,14 @@ static void ahci_save_initial_config(struct pci_dev *pdev,
653 cap &= ~HOST_CAP_PMP; 662 cap &= ~HOST_CAP_PMP;
654 } 663 }
655 664
665 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 &&
666 port_map != 1) {
667 dev_printk(KERN_INFO, &pdev->dev,
668 "JMB361 has only one port, port_map 0x%x -> 0x%x\n",
669 port_map, 1);
670 port_map = 1;
671 }
672
656 /* 673 /*
657 * Temporary Marvell 6145 hack: PATA port presence 674 * Temporary Marvell 6145 hack: PATA port presence
658 * is asserted through the standard AHCI port 675 * is asserted through the standard AHCI port
diff --git a/drivers/ata/ata_piix.c b/drivers/ata/ata_piix.c
index 81b7ae37695..a90ae03f56b 100644
--- a/drivers/ata/ata_piix.c
+++ b/drivers/ata/ata_piix.c
@@ -1043,6 +1043,13 @@ static int piix_broken_suspend(void)
1043 }, 1043 },
1044 }, 1044 },
1045 { 1045 {
1046 .ident = "TECRA M4",
1047 .matches = {
1048 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1049 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"),
1050 },
1051 },
1052 {
1046 .ident = "TECRA M5", 1053 .ident = "TECRA M5",
1047 .matches = { 1054 .matches = {
1048 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1055 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c
index cc816ca623d..303fc0d2b97 100644
--- a/drivers/ata/libata-core.c
+++ b/drivers/ata/libata-core.c
@@ -4297,7 +4297,7 @@ void ata_sg_clean(struct ata_queued_cmd *qc)
4297} 4297}
4298 4298
4299/** 4299/**
4300 * ata_check_atapi_dma - Check whether ATAPI DMA can be supported 4300 * atapi_check_dma - Check whether ATAPI DMA can be supported
4301 * @qc: Metadata associated with taskfile to check 4301 * @qc: Metadata associated with taskfile to check
4302 * 4302 *
4303 * Allow low-level driver to filter ATA PACKET commands, returning 4303 * Allow low-level driver to filter ATA PACKET commands, returning
@@ -4310,7 +4310,7 @@ void ata_sg_clean(struct ata_queued_cmd *qc)
4310 * RETURNS: 0 when ATAPI DMA can be used 4310 * RETURNS: 0 when ATAPI DMA can be used
4311 * nonzero otherwise 4311 * nonzero otherwise
4312 */ 4312 */
4313int ata_check_atapi_dma(struct ata_queued_cmd *qc) 4313int atapi_check_dma(struct ata_queued_cmd *qc)
4314{ 4314{
4315 struct ata_port *ap = qc->ap; 4315 struct ata_port *ap = qc->ap;
4316 4316
diff --git a/drivers/ata/libata-scsi.c b/drivers/ata/libata-scsi.c
index 2e6e1622dc6..57a43649a46 100644
--- a/drivers/ata/libata-scsi.c
+++ b/drivers/ata/libata-scsi.c
@@ -2343,8 +2343,8 @@ static unsigned int atapi_xlat(struct ata_queued_cmd *qc)
2343{ 2343{
2344 struct scsi_cmnd *scmd = qc->scsicmd; 2344 struct scsi_cmnd *scmd = qc->scsicmd;
2345 struct ata_device *dev = qc->dev; 2345 struct ata_device *dev = qc->dev;
2346 int using_pio = (dev->flags & ATA_DFLAG_PIO);
2347 int nodata = (scmd->sc_data_direction == DMA_NONE); 2346 int nodata = (scmd->sc_data_direction == DMA_NONE);
2347 int using_pio = !nodata && (dev->flags & ATA_DFLAG_PIO);
2348 unsigned int nbytes; 2348 unsigned int nbytes;
2349 2349
2350 memset(qc->cdb, 0, dev->cdb_len); 2350 memset(qc->cdb, 0, dev->cdb_len);
@@ -2362,7 +2362,7 @@ static unsigned int atapi_xlat(struct ata_queued_cmd *qc)
2362 ata_qc_set_pc_nbytes(qc); 2362 ata_qc_set_pc_nbytes(qc);
2363 2363
2364 /* check whether ATAPI DMA is safe */ 2364 /* check whether ATAPI DMA is safe */
2365 if (!using_pio && ata_check_atapi_dma(qc)) 2365 if (!nodata && !using_pio && atapi_check_dma(qc))
2366 using_pio = 1; 2366 using_pio = 1;
2367 2367
2368 /* Some controller variants snoop this value for Packet 2368 /* Some controller variants snoop this value for Packet
@@ -2402,13 +2402,11 @@ static unsigned int atapi_xlat(struct ata_queued_cmd *qc)
2402 qc->tf.lbam = (nbytes & 0xFF); 2402 qc->tf.lbam = (nbytes & 0xFF);
2403 qc->tf.lbah = (nbytes >> 8); 2403 qc->tf.lbah = (nbytes >> 8);
2404 2404
2405 if (using_pio || nodata) { 2405 if (nodata)
2406 /* no data, or PIO data xfer */ 2406 qc->tf.protocol = ATAPI_PROT_NODATA;
2407 if (nodata) 2407 else if (using_pio)
2408 qc->tf.protocol = ATAPI_PROT_NODATA; 2408 qc->tf.protocol = ATAPI_PROT_PIO;
2409 else 2409 else {
2410 qc->tf.protocol = ATAPI_PROT_PIO;
2411 } else {
2412 /* DMA data xfer */ 2410 /* DMA data xfer */
2413 qc->tf.protocol = ATAPI_PROT_DMA; 2411 qc->tf.protocol = ATAPI_PROT_DMA;
2414 qc->tf.feature |= ATAPI_PKT_DMA; 2412 qc->tf.feature |= ATAPI_PKT_DMA;
diff --git a/drivers/ata/libata.h b/drivers/ata/libata.h
index 4514283937e..1cf803adbc9 100644
--- a/drivers/ata/libata.h
+++ b/drivers/ata/libata.h
@@ -106,7 +106,7 @@ extern void ata_sg_clean(struct ata_queued_cmd *qc);
106extern void ata_qc_free(struct ata_queued_cmd *qc); 106extern void ata_qc_free(struct ata_queued_cmd *qc);
107extern void ata_qc_issue(struct ata_queued_cmd *qc); 107extern void ata_qc_issue(struct ata_queued_cmd *qc);
108extern void __ata_qc_complete(struct ata_queued_cmd *qc); 108extern void __ata_qc_complete(struct ata_queued_cmd *qc);
109extern int ata_check_atapi_dma(struct ata_queued_cmd *qc); 109extern int atapi_check_dma(struct ata_queued_cmd *qc);
110extern void swap_buf_le16(u16 *buf, unsigned int buf_words); 110extern void swap_buf_le16(u16 *buf, unsigned int buf_words);
111extern void ata_dev_init(struct ata_device *dev); 111extern void ata_dev_init(struct ata_device *dev);
112extern void ata_link_init(struct ata_port *ap, struct ata_link *link, int pmp); 112extern void ata_link_init(struct ata_port *ap, struct ata_link *link, int pmp);
diff --git a/drivers/ata/pata_pcmcia.c b/drivers/ata/pata_pcmcia.c
index 3d39f9dfec5..41b4361bbf6 100644
--- a/drivers/ata/pata_pcmcia.c
+++ b/drivers/ata/pata_pcmcia.c
@@ -414,6 +414,7 @@ static struct pcmcia_device_id pcmcia_devices[] = {
414 PCMCIA_DEVICE_PROD_ID12("IO DATA", "PCIDE", 0x547e66dc, 0x5c5ab149), 414 PCMCIA_DEVICE_PROD_ID12("IO DATA", "PCIDE", 0x547e66dc, 0x5c5ab149),
415 PCMCIA_DEVICE_PROD_ID12("IO DATA", "PCIDEII", 0x547e66dc, 0xb3662674), 415 PCMCIA_DEVICE_PROD_ID12("IO DATA", "PCIDEII", 0x547e66dc, 0xb3662674),
416 PCMCIA_DEVICE_PROD_ID12("LOOKMEET", "CBIDE2 ", 0xe37be2b5, 0x8671043b), 416 PCMCIA_DEVICE_PROD_ID12("LOOKMEET", "CBIDE2 ", 0xe37be2b5, 0x8671043b),
417 PCMCIA_DEVICE_PROD_ID12("M-Systems", "CF300", 0x7ed2ad87, 0x7e9e78ee),
417 PCMCIA_DEVICE_PROD_ID12("M-Systems", "CF500", 0x7ed2ad87, 0x7a13045c), 418 PCMCIA_DEVICE_PROD_ID12("M-Systems", "CF500", 0x7ed2ad87, 0x7a13045c),
418 PCMCIA_DEVICE_PROD_ID2("NinjaATA-", 0xebe0bd79), 419 PCMCIA_DEVICE_PROD_ID2("NinjaATA-", 0xebe0bd79),
419 PCMCIA_DEVICE_PROD_ID12("PCMCIA", "CD-ROM", 0x281f1c5d, 0x66536591), 420 PCMCIA_DEVICE_PROD_ID12("PCMCIA", "CD-ROM", 0x281f1c5d, 0x66536591),
@@ -424,6 +425,7 @@ static struct pcmcia_device_id pcmcia_devices[] = {
424 PCMCIA_DEVICE_PROD_ID12("SMI VENDOR", "SMI PRODUCT", 0x30896c92, 0x703cc5f6), 425 PCMCIA_DEVICE_PROD_ID12("SMI VENDOR", "SMI PRODUCT", 0x30896c92, 0x703cc5f6),
425 PCMCIA_DEVICE_PROD_ID12("TOSHIBA", "MK2001MPL", 0xb4585a1a, 0x3489e003), 426 PCMCIA_DEVICE_PROD_ID12("TOSHIBA", "MK2001MPL", 0xb4585a1a, 0x3489e003),
426 PCMCIA_DEVICE_PROD_ID1("TRANSCEND 512M ", 0xd0909443), 427 PCMCIA_DEVICE_PROD_ID1("TRANSCEND 512M ", 0xd0909443),
428 PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS1GCF45", 0x709b1bf1, 0xf68b6f32),
427 PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS1GCF80", 0x709b1bf1, 0x2a54d4b1), 429 PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS1GCF80", 0x709b1bf1, 0x2a54d4b1),
428 PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS2GCF120", 0x709b1bf1, 0x969aa4f2), 430 PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS2GCF120", 0x709b1bf1, 0x969aa4f2),
429 PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS4GCF120", 0x709b1bf1, 0xf54a91c8), 431 PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS4GCF120", 0x709b1bf1, 0xf54a91c8),
diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c
index 60391e9a84d..28092bc5014 100644
--- a/drivers/ata/sata_mv.c
+++ b/drivers/ata/sata_mv.c
@@ -1322,6 +1322,9 @@ static int mv_port_start(struct ata_port *ap)
1322 goto out_port_free_dma_mem; 1322 goto out_port_free_dma_mem;
1323 memset(pp->crpb, 0, MV_CRPB_Q_SZ); 1323 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
1324 1324
1325 /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
1326 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
1327 ap->flags |= ATA_FLAG_AN;
1325 /* 1328 /*
1326 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl. 1329 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1327 * For later hardware, we need one unique sg_tbl per NCQ tag. 1330 * For later hardware, we need one unique sg_tbl per NCQ tag.
@@ -1592,6 +1595,24 @@ static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
1592 1595
1593 if ((qc->tf.protocol != ATA_PROT_DMA) && 1596 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1594 (qc->tf.protocol != ATA_PROT_NCQ)) { 1597 (qc->tf.protocol != ATA_PROT_NCQ)) {
1598 static int limit_warnings = 10;
1599 /*
1600 * Errata SATA#16, SATA#24: warn if multiple DRQs expected.
1601 *
1602 * Someday, we might implement special polling workarounds
1603 * for these, but it all seems rather unnecessary since we
1604 * normally use only DMA for commands which transfer more
1605 * than a single block of data.
1606 *
1607 * Much of the time, this could just work regardless.
1608 * So for now, just log the incident, and allow the attempt.
1609 */
1610 if (limit_warnings && (qc->nbytes / qc->sect_size) > 1) {
1611 --limit_warnings;
1612 ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME
1613 ": attempting PIO w/multiple DRQ: "
1614 "this may fail due to h/w errata\n");
1615 }
1595 /* 1616 /*
1596 * We're about to send a non-EDMA capable command to the 1617 * We're about to send a non-EDMA capable command to the
1597 * port. Turn off EDMA so there won't be problems accessing 1618 * port. Turn off EDMA so there won't be problems accessing
diff --git a/drivers/atm/he.c b/drivers/atm/he.c
index ffc4a5a4194..ea495b21f91 100644
--- a/drivers/atm/he.c
+++ b/drivers/atm/he.c
@@ -1542,7 +1542,8 @@ he_start(struct atm_dev *dev)
1542 /* initialize framer */ 1542 /* initialize framer */
1543 1543
1544#ifdef CONFIG_ATM_HE_USE_SUNI 1544#ifdef CONFIG_ATM_HE_USE_SUNI
1545 suni_init(he_dev->atm_dev); 1545 if (he_isMM(he_dev))
1546 suni_init(he_dev->atm_dev);
1546 if (he_dev->atm_dev->phy && he_dev->atm_dev->phy->start) 1547 if (he_dev->atm_dev->phy && he_dev->atm_dev->phy->start)
1547 he_dev->atm_dev->phy->start(he_dev->atm_dev); 1548 he_dev->atm_dev->phy->start(he_dev->atm_dev);
1548#endif /* CONFIG_ATM_HE_USE_SUNI */ 1549#endif /* CONFIG_ATM_HE_USE_SUNI */
@@ -1554,6 +1555,7 @@ he_start(struct atm_dev *dev)
1554 val = he_phy_get(he_dev->atm_dev, SUNI_TPOP_APM); 1555 val = he_phy_get(he_dev->atm_dev, SUNI_TPOP_APM);
1555 val = (val & ~SUNI_TPOP_APM_S) | (SUNI_TPOP_S_SDH << SUNI_TPOP_APM_S_SHIFT); 1556 val = (val & ~SUNI_TPOP_APM_S) | (SUNI_TPOP_S_SDH << SUNI_TPOP_APM_S_SHIFT);
1556 he_phy_put(he_dev->atm_dev, val, SUNI_TPOP_APM); 1557 he_phy_put(he_dev->atm_dev, val, SUNI_TPOP_APM);
1558 he_phy_put(he_dev->atm_dev, SUNI_TACP_IUCHP_CLP, SUNI_TACP_IUCHP);
1557 } 1559 }
1558 1560
1559 /* 5.1.12 enable transmit and receive */ 1561 /* 5.1.12 enable transmit and receive */
@@ -2844,10 +2846,15 @@ he_ioctl(struct atm_dev *atm_dev, unsigned int cmd, void __user *arg)
2844 if (copy_from_user(&reg, arg, 2846 if (copy_from_user(&reg, arg,
2845 sizeof(struct he_ioctl_reg))) 2847 sizeof(struct he_ioctl_reg)))
2846 return -EFAULT; 2848 return -EFAULT;
2847 2849
2848 spin_lock_irqsave(&he_dev->global_lock, flags); 2850 spin_lock_irqsave(&he_dev->global_lock, flags);
2849 switch (reg.type) { 2851 switch (reg.type) {
2850 case HE_REGTYPE_PCI: 2852 case HE_REGTYPE_PCI:
2853 if (reg.addr < 0 || reg.addr >= HE_REGMAP_SIZE) {
2854 err = -EINVAL;
2855 break;
2856 }
2857
2851 reg.val = he_readl(he_dev, reg.addr); 2858 reg.val = he_readl(he_dev, reg.addr);
2852 break; 2859 break;
2853 case HE_REGTYPE_RCM: 2860 case HE_REGTYPE_RCM:
diff --git a/drivers/atm/he.h b/drivers/atm/he.h
index fe6cd15a78a..b87d6ccabac 100644
--- a/drivers/atm/he.h
+++ b/drivers/atm/he.h
@@ -267,13 +267,7 @@ struct he_dev {
267 267
268 char prod_id[30]; 268 char prod_id[30];
269 char mac_addr[6]; 269 char mac_addr[6];
270 int media; /* 270 int media;
271 * 0x26 = HE155 MM
272 * 0x27 = HE622 MM
273 * 0x46 = HE155 SM
274 * 0x47 = HE622 SM
275 */
276
277 271
278 unsigned int vcibits, vpibits; 272 unsigned int vcibits, vpibits;
279 unsigned int cells_per_row; 273 unsigned int cells_per_row;
@@ -392,6 +386,7 @@ struct he_vcc
392#define HE_DEV(dev) ((struct he_dev *) (dev)->dev_data) 386#define HE_DEV(dev) ((struct he_dev *) (dev)->dev_data)
393 387
394#define he_is622(dev) ((dev)->media & 0x1) 388#define he_is622(dev) ((dev)->media & 0x1)
389#define he_isMM(dev) ((dev)->media & 0x20)
395 390
396#define HE_REGMAP_SIZE 0x100000 391#define HE_REGMAP_SIZE 0x100000
397 392
@@ -876,8 +871,8 @@ struct he_vcc
876#define M_SN 0x3a /* integer */ 871#define M_SN 0x3a /* integer */
877#define MEDIA 0x3e /* integer */ 872#define MEDIA 0x3e /* integer */
878#define HE155MM 0x26 873#define HE155MM 0x26
879#define HE155SM 0x27 874#define HE622MM 0x27
880#define HE622MM 0x46 875#define HE155SM 0x46
881#define HE622SM 0x47 876#define HE622SM 0x47
882#define MAC_ADDR 0x42 /* char[] */ 877#define MAC_ADDR 0x42 /* char[] */
883 878
diff --git a/drivers/atm/iphase.c b/drivers/atm/iphase.c
index 5c28ca7380f..139fce6968a 100644
--- a/drivers/atm/iphase.c
+++ b/drivers/atm/iphase.c
@@ -2562,17 +2562,11 @@ static int __devinit ia_start(struct atm_dev *dev)
2562 error = suni_init(dev); 2562 error = suni_init(dev);
2563 if (error) 2563 if (error)
2564 goto err_free_rx; 2564 goto err_free_rx;
2565 /* 2565 if (dev->phy->start) {
2566 * Enable interrupt on loss of signal 2566 error = dev->phy->start(dev);
2567 * SUNI_RSOP_CIE - 0x10 2567 if (error)
2568 * SUNI_RSOP_CIE_LOSE - 0x04 2568 goto err_free_rx;
2569 */ 2569 }
2570 ia_phy_put(dev, ia_phy_get(dev, 0x10) | 0x04, 0x10);
2571#ifndef MODULE
2572 error = dev->phy->start(dev);
2573 if (error)
2574 goto err_free_rx;
2575#endif
2576 /* Get iadev->carrier_detect status */ 2570 /* Get iadev->carrier_detect status */
2577 IaFrontEndIntr(iadev); 2571 IaFrontEndIntr(iadev);
2578 } 2572 }
@@ -3198,6 +3192,8 @@ static int __devinit ia_init_one(struct pci_dev *pdev,
3198 IF_INIT(printk("dev_id = 0x%x iadev->LineRate = %d \n", (u32)dev, 3192 IF_INIT(printk("dev_id = 0x%x iadev->LineRate = %d \n", (u32)dev,
3199 iadev->LineRate);) 3193 iadev->LineRate);)
3200 3194
3195 pci_set_drvdata(pdev, dev);
3196
3201 ia_dev[iadev_count] = iadev; 3197 ia_dev[iadev_count] = iadev;
3202 _ia_dev[iadev_count] = dev; 3198 _ia_dev[iadev_count] = dev;
3203 iadev_count++; 3199 iadev_count++;
@@ -3219,8 +3215,6 @@ static int __devinit ia_init_one(struct pci_dev *pdev,
3219 iadev->next_board = ia_boards; 3215 iadev->next_board = ia_boards;
3220 ia_boards = dev; 3216 ia_boards = dev;
3221 3217
3222 pci_set_drvdata(pdev, dev);
3223
3224 return 0; 3218 return 0;
3225 3219
3226err_out_deregister_dev: 3220err_out_deregister_dev:
@@ -3238,9 +3232,14 @@ static void __devexit ia_remove_one(struct pci_dev *pdev)
3238 struct atm_dev *dev = pci_get_drvdata(pdev); 3232 struct atm_dev *dev = pci_get_drvdata(pdev);
3239 IADEV *iadev = INPH_IA_DEV(dev); 3233 IADEV *iadev = INPH_IA_DEV(dev);
3240 3234
3241 ia_phy_put(dev, ia_phy_get(dev,0x10) & ~(0x4), 0x10); 3235 /* Disable phy interrupts */
3236 ia_phy_put(dev, ia_phy_get(dev, SUNI_RSOP_CIE) & ~(SUNI_RSOP_CIE_LOSE),
3237 SUNI_RSOP_CIE);
3242 udelay(1); 3238 udelay(1);
3243 3239
3240 if (dev->phy && dev->phy->stop)
3241 dev->phy->stop(dev);
3242
3244 /* De-register device */ 3243 /* De-register device */
3245 free_irq(iadev->irq, dev); 3244 free_irq(iadev->irq, dev);
3246 iadev_count--; 3245 iadev_count--;
diff --git a/drivers/char/agp/agp.h b/drivers/char/agp/agp.h
index 99e6a406efb..81e14bea54b 100644
--- a/drivers/char/agp/agp.h
+++ b/drivers/char/agp/agp.h
@@ -99,8 +99,8 @@ struct agp_bridge_driver {
99 const void *aperture_sizes; 99 const void *aperture_sizes;
100 int num_aperture_sizes; 100 int num_aperture_sizes;
101 enum aper_size_type size_type; 101 enum aper_size_type size_type;
102 int cant_use_aperture; 102 bool cant_use_aperture;
103 int needs_scratch_page; 103 bool needs_scratch_page;
104 const struct gatt_mask *masks; 104 const struct gatt_mask *masks;
105 int (*fetch_size)(void); 105 int (*fetch_size)(void);
106 int (*configure)(void); 106 int (*configure)(void);
@@ -278,7 +278,7 @@ void agp_generic_destroy_page(void *addr, int flags);
278void agp_free_key(int key); 278void agp_free_key(int key);
279int agp_num_entries(void); 279int agp_num_entries(void);
280u32 agp_collect_device_status(struct agp_bridge_data *bridge, u32 mode, u32 command); 280u32 agp_collect_device_status(struct agp_bridge_data *bridge, u32 mode, u32 command);
281void agp_device_command(u32 command, int agp_v3); 281void agp_device_command(u32 command, bool agp_v3);
282int agp_3_5_enable(struct agp_bridge_data *bridge); 282int agp_3_5_enable(struct agp_bridge_data *bridge);
283void global_cache_flush(void); 283void global_cache_flush(void);
284void get_agp_version(struct agp_bridge_data *bridge); 284void get_agp_version(struct agp_bridge_data *bridge);
diff --git a/drivers/char/agp/alpha-agp.c b/drivers/char/agp/alpha-agp.c
index e77c17838c8..5da89f6c6c2 100644
--- a/drivers/char/agp/alpha-agp.c
+++ b/drivers/char/agp/alpha-agp.c
@@ -80,7 +80,7 @@ static void alpha_core_agp_enable(struct agp_bridge_data *bridge, u32 mode)
80 agp->mode.bits.enable = 1; 80 agp->mode.bits.enable = 1;
81 agp->ops->configure(agp); 81 agp->ops->configure(agp);
82 82
83 agp_device_command(agp->mode.lw, 0); 83 agp_device_command(agp->mode.lw, false);
84} 84}
85 85
86static int alpha_core_agp_insert_memory(struct agp_memory *mem, off_t pg_start, 86static int alpha_core_agp_insert_memory(struct agp_memory *mem, off_t pg_start,
@@ -126,7 +126,7 @@ struct agp_bridge_driver alpha_core_agp_driver = {
126 .aperture_sizes = alpha_core_agp_sizes, 126 .aperture_sizes = alpha_core_agp_sizes,
127 .num_aperture_sizes = 1, 127 .num_aperture_sizes = 1,
128 .size_type = FIXED_APER_SIZE, 128 .size_type = FIXED_APER_SIZE,
129 .cant_use_aperture = 1, 129 .cant_use_aperture = true,
130 .masks = NULL, 130 .masks = NULL,
131 131
132 .fetch_size = alpha_core_agp_fetch_size, 132 .fetch_size = alpha_core_agp_fetch_size,
diff --git a/drivers/char/agp/amd-k7-agp.c b/drivers/char/agp/amd-k7-agp.c
index 96bdb9296b0..39a0718bc61 100644
--- a/drivers/char/agp/amd-k7-agp.c
+++ b/drivers/char/agp/amd-k7-agp.c
@@ -314,9 +314,9 @@ static int amd_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
314 j++; 314 j++;
315 } 315 }
316 316
317 if (mem->is_flushed == FALSE) { 317 if (!mem->is_flushed) {
318 global_cache_flush(); 318 global_cache_flush();
319 mem->is_flushed = TRUE; 319 mem->is_flushed = true;
320 } 320 }
321 321
322 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 322 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
diff --git a/drivers/char/agp/amd64-agp.c b/drivers/char/agp/amd64-agp.c
index d8200ac8f8c..13665db363d 100644
--- a/drivers/char/agp/amd64-agp.c
+++ b/drivers/char/agp/amd64-agp.c
@@ -90,9 +90,9 @@ static int amd64_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
90 j++; 90 j++;
91 } 91 }
92 92
93 if (mem->is_flushed == FALSE) { 93 if (!mem->is_flushed) {
94 global_cache_flush(); 94 global_cache_flush();
95 mem->is_flushed = TRUE; 95 mem->is_flushed = true;
96 } 96 }
97 97
98 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 98 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
diff --git a/drivers/char/agp/ati-agp.c b/drivers/char/agp/ati-agp.c
index 07b4d8ff56e..3a4566c0d84 100644
--- a/drivers/char/agp/ati-agp.c
+++ b/drivers/char/agp/ati-agp.c
@@ -287,10 +287,10 @@ static int ati_insert_memory(struct agp_memory * mem,
287 j++; 287 j++;
288 } 288 }
289 289
290 if (mem->is_flushed == FALSE) { 290 if (!mem->is_flushed) {
291 /*CACHE_FLUSH(); */ 291 /*CACHE_FLUSH(); */
292 global_cache_flush(); 292 global_cache_flush();
293 mem->is_flushed = TRUE; 293 mem->is_flushed = true;
294 } 294 }
295 295
296 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 296 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
diff --git a/drivers/char/agp/backend.c b/drivers/char/agp/backend.c
index b1bdd015165..1ec87104e68 100644
--- a/drivers/char/agp/backend.c
+++ b/drivers/char/agp/backend.c
@@ -188,10 +188,10 @@ static int agp_backend_initialize(struct agp_bridge_data *bridge)
188 188
189err_out: 189err_out:
190 if (bridge->driver->needs_scratch_page) { 190 if (bridge->driver->needs_scratch_page) {
191 bridge->driver->agp_destroy_page(gart_to_virt(bridge->scratch_page_real), 191 void *va = gart_to_virt(bridge->scratch_page_real);
192 AGP_PAGE_DESTROY_UNMAP); 192
193 bridge->driver->agp_destroy_page(gart_to_virt(bridge->scratch_page_real), 193 bridge->driver->agp_destroy_page(va, AGP_PAGE_DESTROY_UNMAP);
194 AGP_PAGE_DESTROY_FREE); 194 bridge->driver->agp_destroy_page(va, AGP_PAGE_DESTROY_FREE);
195 } 195 }
196 if (got_gatt) 196 if (got_gatt)
197 bridge->driver->free_gatt_table(bridge); 197 bridge->driver->free_gatt_table(bridge);
@@ -215,10 +215,10 @@ static void agp_backend_cleanup(struct agp_bridge_data *bridge)
215 215
216 if (bridge->driver->agp_destroy_page && 216 if (bridge->driver->agp_destroy_page &&
217 bridge->driver->needs_scratch_page) { 217 bridge->driver->needs_scratch_page) {
218 bridge->driver->agp_destroy_page(gart_to_virt(bridge->scratch_page_real), 218 void *va = gart_to_virt(bridge->scratch_page_real);
219 AGP_PAGE_DESTROY_UNMAP); 219
220 bridge->driver->agp_destroy_page(gart_to_virt(bridge->scratch_page_real), 220 bridge->driver->agp_destroy_page(va, AGP_PAGE_DESTROY_UNMAP);
221 AGP_PAGE_DESTROY_FREE); 221 bridge->driver->agp_destroy_page(va, AGP_PAGE_DESTROY_FREE);
222 } 222 }
223} 223}
224 224
diff --git a/drivers/char/agp/compat_ioctl.c b/drivers/char/agp/compat_ioctl.c
index 39275794fe6..58c57cb2518 100644
--- a/drivers/char/agp/compat_ioctl.c
+++ b/drivers/char/agp/compat_ioctl.c
@@ -214,7 +214,7 @@ long compat_agp_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
214 ret_val = -EINVAL; 214 ret_val = -EINVAL;
215 goto ioctl_out; 215 goto ioctl_out;
216 } 216 }
217 if ((agp_fe.backend_acquired != TRUE) && 217 if ((agp_fe.backend_acquired != true) &&
218 (cmd != AGPIOC_ACQUIRE32)) { 218 (cmd != AGPIOC_ACQUIRE32)) {
219 ret_val = -EBUSY; 219 ret_val = -EBUSY;
220 goto ioctl_out; 220 goto ioctl_out;
diff --git a/drivers/char/agp/efficeon-agp.c b/drivers/char/agp/efficeon-agp.c
index cac0009cebc..8ca6f262ef8 100644
--- a/drivers/char/agp/efficeon-agp.c
+++ b/drivers/char/agp/efficeon-agp.c
@@ -249,9 +249,9 @@ static int efficeon_insert_memory(struct agp_memory * mem, off_t pg_start, int t
249 if (type != 0 || mem->type != 0) 249 if (type != 0 || mem->type != 0)
250 return -EINVAL; 250 return -EINVAL;
251 251
252 if (mem->is_flushed == FALSE) { 252 if (!mem->is_flushed) {
253 global_cache_flush(); 253 global_cache_flush();
254 mem->is_flushed = TRUE; 254 mem->is_flushed = true;
255 } 255 }
256 256
257 last_page = NULL; 257 last_page = NULL;
@@ -329,7 +329,7 @@ static const struct agp_bridge_driver efficeon_driver = {
329 .free_gatt_table = efficeon_free_gatt_table, 329 .free_gatt_table = efficeon_free_gatt_table,
330 .insert_memory = efficeon_insert_memory, 330 .insert_memory = efficeon_insert_memory,
331 .remove_memory = efficeon_remove_memory, 331 .remove_memory = efficeon_remove_memory,
332 .cant_use_aperture = 0, // 1 might be faster? 332 .cant_use_aperture = false, // true might be faster?
333 333
334 // Generic 334 // Generic
335 .alloc_by_type = agp_generic_alloc_by_type, 335 .alloc_by_type = agp_generic_alloc_by_type,
diff --git a/drivers/char/agp/frontend.c b/drivers/char/agp/frontend.c
index 857b26227d8..e6cb1ab03e0 100644
--- a/drivers/char/agp/frontend.c
+++ b/drivers/char/agp/frontend.c
@@ -395,7 +395,7 @@ static int agp_remove_controller(struct agp_controller *controller)
395 395
396 if (agp_fe.current_controller == controller) { 396 if (agp_fe.current_controller == controller) {
397 agp_fe.current_controller = NULL; 397 agp_fe.current_controller = NULL;
398 agp_fe.backend_acquired = FALSE; 398 agp_fe.backend_acquired = false;
399 agp_backend_release(agp_bridge); 399 agp_backend_release(agp_bridge);
400 } 400 }
401 kfree(controller); 401 kfree(controller);
@@ -443,7 +443,7 @@ static void agp_controller_release_current(struct agp_controller *controller,
443 } 443 }
444 444
445 agp_fe.current_controller = NULL; 445 agp_fe.current_controller = NULL;
446 agp_fe.used_by_controller = FALSE; 446 agp_fe.used_by_controller = false;
447 agp_backend_release(agp_bridge); 447 agp_backend_release(agp_bridge);
448} 448}
449 449
@@ -573,7 +573,7 @@ static int agp_mmap(struct file *file, struct vm_area_struct *vma)
573 573
574 mutex_lock(&(agp_fe.agp_mutex)); 574 mutex_lock(&(agp_fe.agp_mutex));
575 575
576 if (agp_fe.backend_acquired != TRUE) 576 if (agp_fe.backend_acquired != true)
577 goto out_eperm; 577 goto out_eperm;
578 578
579 if (!(test_bit(AGP_FF_IS_VALID, &priv->access_flags))) 579 if (!(test_bit(AGP_FF_IS_VALID, &priv->access_flags)))
@@ -768,7 +768,7 @@ int agpioc_acquire_wrap(struct agp_file_private *priv)
768 768
769 atomic_inc(&agp_bridge->agp_in_use); 769 atomic_inc(&agp_bridge->agp_in_use);
770 770
771 agp_fe.backend_acquired = TRUE; 771 agp_fe.backend_acquired = true;
772 772
773 controller = agp_find_controller_by_pid(priv->my_pid); 773 controller = agp_find_controller_by_pid(priv->my_pid);
774 774
@@ -778,7 +778,7 @@ int agpioc_acquire_wrap(struct agp_file_private *priv)
778 controller = agp_create_controller(priv->my_pid); 778 controller = agp_create_controller(priv->my_pid);
779 779
780 if (controller == NULL) { 780 if (controller == NULL) {
781 agp_fe.backend_acquired = FALSE; 781 agp_fe.backend_acquired = false;
782 agp_backend_release(agp_bridge); 782 agp_backend_release(agp_bridge);
783 return -ENOMEM; 783 return -ENOMEM;
784 } 784 }
@@ -981,7 +981,7 @@ static long agp_ioctl(struct file *file,
981 ret_val = -EINVAL; 981 ret_val = -EINVAL;
982 goto ioctl_out; 982 goto ioctl_out;
983 } 983 }
984 if ((agp_fe.backend_acquired != TRUE) && 984 if ((agp_fe.backend_acquired != true) &&
985 (cmd != AGPIOC_ACQUIRE)) { 985 (cmd != AGPIOC_ACQUIRE)) {
986 ret_val = -EBUSY; 986 ret_val = -EBUSY;
987 goto ioctl_out; 987 goto ioctl_out;
diff --git a/drivers/char/agp/generic.c b/drivers/char/agp/generic.c
index 7fc0c99a3a5..564daaa6c7d 100644
--- a/drivers/char/agp/generic.c
+++ b/drivers/char/agp/generic.c
@@ -96,13 +96,13 @@ EXPORT_SYMBOL(agp_flush_chipset);
96void agp_alloc_page_array(size_t size, struct agp_memory *mem) 96void agp_alloc_page_array(size_t size, struct agp_memory *mem)
97{ 97{
98 mem->memory = NULL; 98 mem->memory = NULL;
99 mem->vmalloc_flag = 0; 99 mem->vmalloc_flag = false;
100 100
101 if (size <= 2*PAGE_SIZE) 101 if (size <= 2*PAGE_SIZE)
102 mem->memory = kmalloc(size, GFP_KERNEL | __GFP_NORETRY); 102 mem->memory = kmalloc(size, GFP_KERNEL | __GFP_NORETRY);
103 if (mem->memory == NULL) { 103 if (mem->memory == NULL) {
104 mem->memory = vmalloc(size); 104 mem->memory = vmalloc(size);
105 mem->vmalloc_flag = 1; 105 mem->vmalloc_flag = true;
106 } 106 }
107} 107}
108EXPORT_SYMBOL(agp_alloc_page_array); 108EXPORT_SYMBOL(agp_alloc_page_array);
@@ -188,7 +188,7 @@ void agp_free_memory(struct agp_memory *curr)
188 if (curr == NULL) 188 if (curr == NULL)
189 return; 189 return;
190 190
191 if (curr->is_bound == TRUE) 191 if (curr->is_bound)
192 agp_unbind_memory(curr); 192 agp_unbind_memory(curr);
193 193
194 if (curr->type >= AGP_USER_TYPES) { 194 if (curr->type >= AGP_USER_TYPES) {
@@ -202,10 +202,13 @@ void agp_free_memory(struct agp_memory *curr)
202 } 202 }
203 if (curr->page_count != 0) { 203 if (curr->page_count != 0) {
204 for (i = 0; i < curr->page_count; i++) { 204 for (i = 0; i < curr->page_count; i++) {
205 curr->bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[i]), AGP_PAGE_DESTROY_UNMAP); 205 curr->memory[i] = (unsigned long)gart_to_virt(curr->memory[i]);
206 curr->bridge->driver->agp_destroy_page((void *)curr->memory[i],
207 AGP_PAGE_DESTROY_UNMAP);
206 } 208 }
207 for (i = 0; i < curr->page_count; i++) { 209 for (i = 0; i < curr->page_count; i++) {
208 curr->bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[i]), AGP_PAGE_DESTROY_FREE); 210 curr->bridge->driver->agp_destroy_page((void *)curr->memory[i],
211 AGP_PAGE_DESTROY_FREE);
209 } 212 }
210 } 213 }
211 agp_free_key(curr->key); 214 agp_free_key(curr->key);
@@ -411,20 +414,20 @@ int agp_bind_memory(struct agp_memory *curr, off_t pg_start)
411 if (curr == NULL) 414 if (curr == NULL)
412 return -EINVAL; 415 return -EINVAL;
413 416
414 if (curr->is_bound == TRUE) { 417 if (curr->is_bound) {
415 printk(KERN_INFO PFX "memory %p is already bound!\n", curr); 418 printk(KERN_INFO PFX "memory %p is already bound!\n", curr);
416 return -EINVAL; 419 return -EINVAL;
417 } 420 }
418 if (curr->is_flushed == FALSE) { 421 if (!curr->is_flushed) {
419 curr->bridge->driver->cache_flush(); 422 curr->bridge->driver->cache_flush();
420 curr->is_flushed = TRUE; 423 curr->is_flushed = true;
421 } 424 }
422 ret_val = curr->bridge->driver->insert_memory(curr, pg_start, curr->type); 425 ret_val = curr->bridge->driver->insert_memory(curr, pg_start, curr->type);
423 426
424 if (ret_val != 0) 427 if (ret_val != 0)
425 return ret_val; 428 return ret_val;
426 429
427 curr->is_bound = TRUE; 430 curr->is_bound = true;
428 curr->pg_start = pg_start; 431 curr->pg_start = pg_start;
429 return 0; 432 return 0;
430} 433}
@@ -446,7 +449,7 @@ int agp_unbind_memory(struct agp_memory *curr)
446 if (curr == NULL) 449 if (curr == NULL)
447 return -EINVAL; 450 return -EINVAL;
448 451
449 if (curr->is_bound != TRUE) { 452 if (!curr->is_bound) {
450 printk(KERN_INFO PFX "memory %p was not bound!\n", curr); 453 printk(KERN_INFO PFX "memory %p was not bound!\n", curr);
451 return -EINVAL; 454 return -EINVAL;
452 } 455 }
@@ -456,7 +459,7 @@ int agp_unbind_memory(struct agp_memory *curr)
456 if (ret_val != 0) 459 if (ret_val != 0)
457 return ret_val; 460 return ret_val;
458 461
459 curr->is_bound = FALSE; 462 curr->is_bound = false;
460 curr->pg_start = 0; 463 curr->pg_start = 0;
461 return 0; 464 return 0;
462} 465}
@@ -754,7 +757,7 @@ u32 agp_collect_device_status(struct agp_bridge_data *bridge, u32 requested_mode
754EXPORT_SYMBOL(agp_collect_device_status); 757EXPORT_SYMBOL(agp_collect_device_status);
755 758
756 759
757void agp_device_command(u32 bridge_agpstat, int agp_v3) 760void agp_device_command(u32 bridge_agpstat, bool agp_v3)
758{ 761{
759 struct pci_dev *device = NULL; 762 struct pci_dev *device = NULL;
760 int mode; 763 int mode;
@@ -818,7 +821,7 @@ void agp_generic_enable(struct agp_bridge_data *bridge, u32 requested_mode)
818 /* If we have 3.5, we can do the isoch stuff. */ 821 /* If we have 3.5, we can do the isoch stuff. */
819 if (bridge->minor_version >= 5) 822 if (bridge->minor_version >= 5)
820 agp_3_5_enable(bridge); 823 agp_3_5_enable(bridge);
821 agp_device_command(bridge_agpstat, TRUE); 824 agp_device_command(bridge_agpstat, true);
822 return; 825 return;
823 } else { 826 } else {
824 /* Disable calibration cycle in RX91<1> when not in AGP3.0 mode of operation.*/ 827 /* Disable calibration cycle in RX91<1> when not in AGP3.0 mode of operation.*/
@@ -835,7 +838,7 @@ void agp_generic_enable(struct agp_bridge_data *bridge, u32 requested_mode)
835 } 838 }
836 839
837 /* AGP v<3 */ 840 /* AGP v<3 */
838 agp_device_command(bridge_agpstat, FALSE); 841 agp_device_command(bridge_agpstat, false);
839} 842}
840EXPORT_SYMBOL(agp_generic_enable); 843EXPORT_SYMBOL(agp_generic_enable);
841 844
@@ -1083,9 +1086,9 @@ int agp_generic_insert_memory(struct agp_memory * mem, off_t pg_start, int type)
1083 j++; 1086 j++;
1084 } 1087 }
1085 1088
1086 if (mem->is_flushed == FALSE) { 1089 if (!mem->is_flushed) {
1087 bridge->driver->cache_flush(); 1090 bridge->driver->cache_flush();
1088 mem->is_flushed = TRUE; 1091 mem->is_flushed = true;
1089 } 1092 }
1090 1093
1091 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 1094 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
diff --git a/drivers/char/agp/hp-agp.c b/drivers/char/agp/hp-agp.c
index cbb0444467b..80d7317f85c 100644
--- a/drivers/char/agp/hp-agp.c
+++ b/drivers/char/agp/hp-agp.c
@@ -353,9 +353,9 @@ hp_zx1_insert_memory (struct agp_memory *mem, off_t pg_start, int type)
353 j++; 353 j++;
354 } 354 }
355 355
356 if (mem->is_flushed == FALSE) { 356 if (!mem->is_flushed) {
357 global_cache_flush(); 357 global_cache_flush();
358 mem->is_flushed = TRUE; 358 mem->is_flushed = true;
359 } 359 }
360 360
361 for (i = 0, j = io_pg_start; i < mem->page_count; i++) { 361 for (i = 0, j = io_pg_start; i < mem->page_count; i++) {
@@ -437,7 +437,7 @@ const struct agp_bridge_driver hp_zx1_driver = {
437 .agp_alloc_page = agp_generic_alloc_page, 437 .agp_alloc_page = agp_generic_alloc_page,
438 .agp_destroy_page = agp_generic_destroy_page, 438 .agp_destroy_page = agp_generic_destroy_page,
439 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 439 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
440 .cant_use_aperture = 1, 440 .cant_use_aperture = true,
441}; 441};
442 442
443static int __init 443static int __init
diff --git a/drivers/char/agp/i460-agp.c b/drivers/char/agp/i460-agp.c
index 76f581c85a7..e587eebebc6 100644
--- a/drivers/char/agp/i460-agp.c
+++ b/drivers/char/agp/i460-agp.c
@@ -580,7 +580,7 @@ const struct agp_bridge_driver intel_i460_driver = {
580 .alloc_by_type = agp_generic_alloc_by_type, 580 .alloc_by_type = agp_generic_alloc_by_type,
581 .free_by_type = agp_generic_free_by_type, 581 .free_by_type = agp_generic_free_by_type,
582 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 582 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
583 .cant_use_aperture = 1, 583 .cant_use_aperture = true,
584}; 584};
585 585
586static int __devinit agp_intel_i460_probe(struct pci_dev *pdev, 586static int __devinit agp_intel_i460_probe(struct pci_dev *pdev,
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index eeea50a1d22..df702642ab8 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -34,6 +34,12 @@
34#define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2 34#define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2
35#define PCI_DEVICE_ID_INTEL_IGD_HB 0x2A40 35#define PCI_DEVICE_ID_INTEL_IGD_HB 0x2A40
36#define PCI_DEVICE_ID_INTEL_IGD_IG 0x2A42 36#define PCI_DEVICE_ID_INTEL_IGD_IG 0x2A42
37#define PCI_DEVICE_ID_INTEL_IGD_E_HB 0x2E00
38#define PCI_DEVICE_ID_INTEL_IGD_E_IG 0x2E02
39#define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10
40#define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12
41#define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20
42#define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22
37 43
38/* cover 915 and 945 variants */ 44/* cover 915 and 945 variants */
39#define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \ 45#define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
@@ -55,6 +61,10 @@
55 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \ 61 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
56 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB) 62 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB)
57 63
64#define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_E_HB || \
65 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
66 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB)
67
58extern int agp_memory_reserved; 68extern int agp_memory_reserved;
59 69
60 70
@@ -80,8 +90,13 @@ extern int agp_memory_reserved;
80#define I915_PTEADDR 0x1C 90#define I915_PTEADDR 0x1C
81#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) 91#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
82#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) 92#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
83#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4) 93#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
84#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4) 94#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
95#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
96#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
97#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
98#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
99
85#define I915_IFPADDR 0x60 100#define I915_IFPADDR 0x60
86 101
87/* Intel 965G registers */ 102/* Intel 965G registers */
@@ -325,7 +340,7 @@ static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
325out: 340out:
326 ret = 0; 341 ret = 0;
327out_err: 342out_err:
328 mem->is_flushed = 1; 343 mem->is_flushed = true;
329 return ret; 344 return ret;
330} 345}
331 346
@@ -418,9 +433,11 @@ static void intel_i810_free_by_type(struct agp_memory *curr)
418 if (curr->page_count == 4) 433 if (curr->page_count == 4)
419 i8xx_destroy_pages(gart_to_virt(curr->memory[0])); 434 i8xx_destroy_pages(gart_to_virt(curr->memory[0]));
420 else { 435 else {
421 agp_bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[0]), 436 void *va = gart_to_virt(curr->memory[0]);
437
438 agp_bridge->driver->agp_destroy_page(va,
422 AGP_PAGE_DESTROY_UNMAP); 439 AGP_PAGE_DESTROY_UNMAP);
423 agp_bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[0]), 440 agp_bridge->driver->agp_destroy_page(va,
424 AGP_PAGE_DESTROY_FREE); 441 AGP_PAGE_DESTROY_FREE);
425 } 442 }
426 agp_free_page_array(curr); 443 agp_free_page_array(curr);
@@ -504,6 +521,10 @@ static void intel_i830_init_gtt_entries(void)
504 size = 512; 521 size = 512;
505 } 522 }
506 size += 4; 523 size += 4;
524 } else if (IS_G4X) {
525 /* On 4 series hardware, GTT stolen is separate from graphics
526 * stolen, ignore it in stolen gtt entries counting */
527 size = 0;
507 } else { 528 } else {
508 /* On previous hardware, the GTT size was just what was 529 /* On previous hardware, the GTT size was just what was
509 * required to map the aperture. 530 * required to map the aperture.
@@ -552,30 +573,54 @@ static void intel_i830_init_gtt_entries(void)
552 break; 573 break;
553 case I915_GMCH_GMS_STOLEN_48M: 574 case I915_GMCH_GMS_STOLEN_48M:
554 /* Check it's really I915G */ 575 /* Check it's really I915G */
555 if (IS_I915 || IS_I965 || IS_G33) 576 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
556 gtt_entries = MB(48) - KB(size); 577 gtt_entries = MB(48) - KB(size);
557 else 578 else
558 gtt_entries = 0; 579 gtt_entries = 0;
559 break; 580 break;
560 case I915_GMCH_GMS_STOLEN_64M: 581 case I915_GMCH_GMS_STOLEN_64M:
561 /* Check it's really I915G */ 582 /* Check it's really I915G */
562 if (IS_I915 || IS_I965 || IS_G33) 583 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
563 gtt_entries = MB(64) - KB(size); 584 gtt_entries = MB(64) - KB(size);
564 else 585 else
565 gtt_entries = 0; 586 gtt_entries = 0;
566 break; 587 break;
567 case G33_GMCH_GMS_STOLEN_128M: 588 case G33_GMCH_GMS_STOLEN_128M:
568 if (IS_G33) 589 if (IS_G33 || IS_I965 || IS_G4X)
569 gtt_entries = MB(128) - KB(size); 590 gtt_entries = MB(128) - KB(size);
570 else 591 else
571 gtt_entries = 0; 592 gtt_entries = 0;
572 break; 593 break;
573 case G33_GMCH_GMS_STOLEN_256M: 594 case G33_GMCH_GMS_STOLEN_256M:
574 if (IS_G33) 595 if (IS_G33 || IS_I965 || IS_G4X)
575 gtt_entries = MB(256) - KB(size); 596 gtt_entries = MB(256) - KB(size);
576 else 597 else
577 gtt_entries = 0; 598 gtt_entries = 0;
578 break; 599 break;
600 case INTEL_GMCH_GMS_STOLEN_96M:
601 if (IS_I965 || IS_G4X)
602 gtt_entries = MB(96) - KB(size);
603 else
604 gtt_entries = 0;
605 break;
606 case INTEL_GMCH_GMS_STOLEN_160M:
607 if (IS_I965 || IS_G4X)
608 gtt_entries = MB(160) - KB(size);
609 else
610 gtt_entries = 0;
611 break;
612 case INTEL_GMCH_GMS_STOLEN_224M:
613 if (IS_I965 || IS_G4X)
614 gtt_entries = MB(224) - KB(size);
615 else
616 gtt_entries = 0;
617 break;
618 case INTEL_GMCH_GMS_STOLEN_352M:
619 if (IS_I965 || IS_G4X)
620 gtt_entries = MB(352) - KB(size);
621 else
622 gtt_entries = 0;
623 break;
579 default: 624 default:
580 gtt_entries = 0; 625 gtt_entries = 0;
581 break; 626 break;
@@ -793,7 +838,7 @@ static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start,
793out: 838out:
794 ret = 0; 839 ret = 0;
795out_err: 840out_err:
796 mem->is_flushed = 1; 841 mem->is_flushed = true;
797 return ret; 842 return ret;
798} 843}
799 844
@@ -903,7 +948,7 @@ static void intel_i9xx_setup_flush(void)
903 intel_private.ifp_resource.flags = IORESOURCE_MEM; 948 intel_private.ifp_resource.flags = IORESOURCE_MEM;
904 949
905 /* Setup chipset flush for 915 */ 950 /* Setup chipset flush for 915 */
906 if (IS_I965 || IS_G33) { 951 if (IS_I965 || IS_G33 || IS_G4X) {
907 intel_i965_g33_setup_chipset_flush(); 952 intel_i965_g33_setup_chipset_flush();
908 } else { 953 } else {
909 intel_i915_setup_chipset_flush(); 954 intel_i915_setup_chipset_flush();
@@ -1020,7 +1065,7 @@ static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
1020 out: 1065 out:
1021 ret = 0; 1066 ret = 0;
1022 out_err: 1067 out_err:
1023 mem->is_flushed = 1; 1068 mem->is_flushed = true;
1024 return ret; 1069 return ret;
1025} 1070}
1026 1071
@@ -1134,53 +1179,64 @@ static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1134 return addr | bridge->driver->masks[type].mask; 1179 return addr | bridge->driver->masks[type].mask;
1135} 1180}
1136 1181
1182static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
1183{
1184 switch (agp_bridge->dev->device) {
1185 case PCI_DEVICE_ID_INTEL_IGD_HB:
1186 case PCI_DEVICE_ID_INTEL_IGD_E_HB:
1187 case PCI_DEVICE_ID_INTEL_Q45_HB:
1188 case PCI_DEVICE_ID_INTEL_G45_HB:
1189 *gtt_offset = *gtt_size = MB(2);
1190 break;
1191 default:
1192 *gtt_offset = *gtt_size = KB(512);
1193 }
1194}
1195
1137/* The intel i965 automatically initializes the agp aperture during POST. 1196/* The intel i965 automatically initializes the agp aperture during POST.
1138 * Use the memory already set aside for in the GTT. 1197 * Use the memory already set aside for in the GTT.
1139 */ 1198 */
1140static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge) 1199static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
1141{ 1200{
1142 int page_order; 1201 int page_order;
1143 struct aper_size_info_fixed *size; 1202 struct aper_size_info_fixed *size;
1144 int num_entries; 1203 int num_entries;
1145 u32 temp; 1204 u32 temp;
1146 int gtt_offset, gtt_size; 1205 int gtt_offset, gtt_size;
1147 1206
1148 size = agp_bridge->current_size; 1207 size = agp_bridge->current_size;
1149 page_order = size->page_order; 1208 page_order = size->page_order;
1150 num_entries = size->num_entries; 1209 num_entries = size->num_entries;
1151 agp_bridge->gatt_table_real = NULL; 1210 agp_bridge->gatt_table_real = NULL;
1152 1211
1153 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); 1212 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1154 1213
1155 temp &= 0xfff00000; 1214 temp &= 0xfff00000;
1156 1215
1157 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_HB) 1216 intel_i965_get_gtt_range(&gtt_offset, &gtt_size);
1158 gtt_offset = gtt_size = MB(2);
1159 else
1160 gtt_offset = gtt_size = KB(512);
1161 1217
1162 intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size); 1218 intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
1163 1219
1164 if (!intel_private.gtt) 1220 if (!intel_private.gtt)
1165 return -ENOMEM; 1221 return -ENOMEM;
1166 1222
1167 intel_private.registers = ioremap(temp, 128 * 4096); 1223 intel_private.registers = ioremap(temp, 128 * 4096);
1168 if (!intel_private.registers) { 1224 if (!intel_private.registers) {
1169 iounmap(intel_private.gtt); 1225 iounmap(intel_private.gtt);
1170 return -ENOMEM; 1226 return -ENOMEM;
1171 } 1227 }
1172 1228
1173 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; 1229 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1174 global_cache_flush(); /* FIXME: ? */ 1230 global_cache_flush(); /* FIXME: ? */
1175 1231
1176 /* we have to call this as early as possible after the MMIO base address is known */ 1232 /* we have to call this as early as possible after the MMIO base address is known */
1177 intel_i830_init_gtt_entries(); 1233 intel_i830_init_gtt_entries();
1178 1234
1179 agp_bridge->gatt_table = NULL; 1235 agp_bridge->gatt_table = NULL;
1180 1236
1181 agp_bridge->gatt_bus_addr = temp; 1237 agp_bridge->gatt_bus_addr = temp;
1182 1238
1183 return 0; 1239 return 0;
1184} 1240}
1185 1241
1186 1242
@@ -1656,7 +1712,7 @@ static const struct agp_bridge_driver intel_810_driver = {
1656 .aperture_sizes = intel_i810_sizes, 1712 .aperture_sizes = intel_i810_sizes,
1657 .size_type = FIXED_APER_SIZE, 1713 .size_type = FIXED_APER_SIZE,
1658 .num_aperture_sizes = 2, 1714 .num_aperture_sizes = 2,
1659 .needs_scratch_page = TRUE, 1715 .needs_scratch_page = true,
1660 .configure = intel_i810_configure, 1716 .configure = intel_i810_configure,
1661 .fetch_size = intel_i810_fetch_size, 1717 .fetch_size = intel_i810_fetch_size,
1662 .cleanup = intel_i810_cleanup, 1718 .cleanup = intel_i810_cleanup,
@@ -1697,7 +1753,7 @@ static const struct agp_bridge_driver intel_815_driver = {
1697 .free_by_type = agp_generic_free_by_type, 1753 .free_by_type = agp_generic_free_by_type,
1698 .agp_alloc_page = agp_generic_alloc_page, 1754 .agp_alloc_page = agp_generic_alloc_page,
1699 .agp_destroy_page = agp_generic_destroy_page, 1755 .agp_destroy_page = agp_generic_destroy_page,
1700 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1756 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1701}; 1757};
1702 1758
1703static const struct agp_bridge_driver intel_830_driver = { 1759static const struct agp_bridge_driver intel_830_driver = {
@@ -1705,7 +1761,7 @@ static const struct agp_bridge_driver intel_830_driver = {
1705 .aperture_sizes = intel_i830_sizes, 1761 .aperture_sizes = intel_i830_sizes,
1706 .size_type = FIXED_APER_SIZE, 1762 .size_type = FIXED_APER_SIZE,
1707 .num_aperture_sizes = 4, 1763 .num_aperture_sizes = 4,
1708 .needs_scratch_page = TRUE, 1764 .needs_scratch_page = true,
1709 .configure = intel_i830_configure, 1765 .configure = intel_i830_configure,
1710 .fetch_size = intel_i830_fetch_size, 1766 .fetch_size = intel_i830_fetch_size,
1711 .cleanup = intel_i830_cleanup, 1767 .cleanup = intel_i830_cleanup,
@@ -1876,7 +1932,7 @@ static const struct agp_bridge_driver intel_915_driver = {
1876 .aperture_sizes = intel_i830_sizes, 1932 .aperture_sizes = intel_i830_sizes,
1877 .size_type = FIXED_APER_SIZE, 1933 .size_type = FIXED_APER_SIZE,
1878 .num_aperture_sizes = 4, 1934 .num_aperture_sizes = 4,
1879 .needs_scratch_page = TRUE, 1935 .needs_scratch_page = true,
1880 .configure = intel_i915_configure, 1936 .configure = intel_i915_configure,
1881 .fetch_size = intel_i9xx_fetch_size, 1937 .fetch_size = intel_i9xx_fetch_size,
1882 .cleanup = intel_i915_cleanup, 1938 .cleanup = intel_i915_cleanup,
@@ -1898,28 +1954,28 @@ static const struct agp_bridge_driver intel_915_driver = {
1898}; 1954};
1899 1955
1900static const struct agp_bridge_driver intel_i965_driver = { 1956static const struct agp_bridge_driver intel_i965_driver = {
1901 .owner = THIS_MODULE, 1957 .owner = THIS_MODULE,
1902 .aperture_sizes = intel_i830_sizes, 1958 .aperture_sizes = intel_i830_sizes,
1903 .size_type = FIXED_APER_SIZE, 1959 .size_type = FIXED_APER_SIZE,
1904 .num_aperture_sizes = 4, 1960 .num_aperture_sizes = 4,
1905 .needs_scratch_page = TRUE, 1961 .needs_scratch_page = true,
1906 .configure = intel_i915_configure, 1962 .configure = intel_i915_configure,
1907 .fetch_size = intel_i9xx_fetch_size, 1963 .fetch_size = intel_i9xx_fetch_size,
1908 .cleanup = intel_i915_cleanup, 1964 .cleanup = intel_i915_cleanup,
1909 .tlb_flush = intel_i810_tlbflush, 1965 .tlb_flush = intel_i810_tlbflush,
1910 .mask_memory = intel_i965_mask_memory, 1966 .mask_memory = intel_i965_mask_memory,
1911 .masks = intel_i810_masks, 1967 .masks = intel_i810_masks,
1912 .agp_enable = intel_i810_agp_enable, 1968 .agp_enable = intel_i810_agp_enable,
1913 .cache_flush = global_cache_flush, 1969 .cache_flush = global_cache_flush,
1914 .create_gatt_table = intel_i965_create_gatt_table, 1970 .create_gatt_table = intel_i965_create_gatt_table,
1915 .free_gatt_table = intel_i830_free_gatt_table, 1971 .free_gatt_table = intel_i830_free_gatt_table,
1916 .insert_memory = intel_i915_insert_entries, 1972 .insert_memory = intel_i915_insert_entries,
1917 .remove_memory = intel_i915_remove_entries, 1973 .remove_memory = intel_i915_remove_entries,
1918 .alloc_by_type = intel_i830_alloc_by_type, 1974 .alloc_by_type = intel_i830_alloc_by_type,
1919 .free_by_type = intel_i810_free_by_type, 1975 .free_by_type = intel_i810_free_by_type,
1920 .agp_alloc_page = agp_generic_alloc_page, 1976 .agp_alloc_page = agp_generic_alloc_page,
1921 .agp_destroy_page = agp_generic_destroy_page, 1977 .agp_destroy_page = agp_generic_destroy_page,
1922 .agp_type_to_mask_type = intel_i830_type_to_mask_type, 1978 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1923 .chipset_flush = intel_i915_chipset_flush, 1979 .chipset_flush = intel_i915_chipset_flush,
1924}; 1980};
1925 1981
@@ -1948,28 +2004,28 @@ static const struct agp_bridge_driver intel_7505_driver = {
1948}; 2004};
1949 2005
1950static const struct agp_bridge_driver intel_g33_driver = { 2006static const struct agp_bridge_driver intel_g33_driver = {
1951 .owner = THIS_MODULE, 2007 .owner = THIS_MODULE,
1952 .aperture_sizes = intel_i830_sizes, 2008 .aperture_sizes = intel_i830_sizes,
1953 .size_type = FIXED_APER_SIZE, 2009 .size_type = FIXED_APER_SIZE,
1954 .num_aperture_sizes = 4, 2010 .num_aperture_sizes = 4,
1955 .needs_scratch_page = TRUE, 2011 .needs_scratch_page = true,
1956 .configure = intel_i915_configure, 2012 .configure = intel_i915_configure,
1957 .fetch_size = intel_i9xx_fetch_size, 2013 .fetch_size = intel_i9xx_fetch_size,
1958 .cleanup = intel_i915_cleanup, 2014 .cleanup = intel_i915_cleanup,
1959 .tlb_flush = intel_i810_tlbflush, 2015 .tlb_flush = intel_i810_tlbflush,
1960 .mask_memory = intel_i965_mask_memory, 2016 .mask_memory = intel_i965_mask_memory,
1961 .masks = intel_i810_masks, 2017 .masks = intel_i810_masks,
1962 .agp_enable = intel_i810_agp_enable, 2018 .agp_enable = intel_i810_agp_enable,
1963 .cache_flush = global_cache_flush, 2019 .cache_flush = global_cache_flush,
1964 .create_gatt_table = intel_i915_create_gatt_table, 2020 .create_gatt_table = intel_i915_create_gatt_table,
1965 .free_gatt_table = intel_i830_free_gatt_table, 2021 .free_gatt_table = intel_i830_free_gatt_table,
1966 .insert_memory = intel_i915_insert_entries, 2022 .insert_memory = intel_i915_insert_entries,
1967 .remove_memory = intel_i915_remove_entries, 2023 .remove_memory = intel_i915_remove_entries,
1968 .alloc_by_type = intel_i830_alloc_by_type, 2024 .alloc_by_type = intel_i830_alloc_by_type,
1969 .free_by_type = intel_i810_free_by_type, 2025 .free_by_type = intel_i810_free_by_type,
1970 .agp_alloc_page = agp_generic_alloc_page, 2026 .agp_alloc_page = agp_generic_alloc_page,
1971 .agp_destroy_page = agp_generic_destroy_page, 2027 .agp_destroy_page = agp_generic_destroy_page,
1972 .agp_type_to_mask_type = intel_i830_type_to_mask_type, 2028 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1973 .chipset_flush = intel_i915_chipset_flush, 2029 .chipset_flush = intel_i915_chipset_flush,
1974}; 2030};
1975 2031
@@ -2063,6 +2119,12 @@ static const struct intel_driver_description {
2063 NULL, &intel_g33_driver }, 2119 NULL, &intel_g33_driver },
2064 { PCI_DEVICE_ID_INTEL_IGD_HB, PCI_DEVICE_ID_INTEL_IGD_IG, 0, 2120 { PCI_DEVICE_ID_INTEL_IGD_HB, PCI_DEVICE_ID_INTEL_IGD_IG, 0,
2065 "Intel Integrated Graphics Device", NULL, &intel_i965_driver }, 2121 "Intel Integrated Graphics Device", NULL, &intel_i965_driver },
2122 { PCI_DEVICE_ID_INTEL_IGD_E_HB, PCI_DEVICE_ID_INTEL_IGD_E_IG, 0,
2123 "Intel Integrated Graphics Device", NULL, &intel_i965_driver },
2124 { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0,
2125 "Q45/Q43", NULL, &intel_i965_driver },
2126 { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0,
2127 "G45/G43", NULL, &intel_i965_driver },
2066 { 0, 0, 0, NULL, NULL, NULL } 2128 { 0, 0, 0, NULL, NULL, NULL }
2067}; 2129};
2068 2130
@@ -2254,6 +2316,9 @@ static struct pci_device_id agp_intel_pci_table[] = {
2254 ID(PCI_DEVICE_ID_INTEL_Q35_HB), 2316 ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2255 ID(PCI_DEVICE_ID_INTEL_Q33_HB), 2317 ID(PCI_DEVICE_ID_INTEL_Q33_HB),
2256 ID(PCI_DEVICE_ID_INTEL_IGD_HB), 2318 ID(PCI_DEVICE_ID_INTEL_IGD_HB),
2319 ID(PCI_DEVICE_ID_INTEL_IGD_E_HB),
2320 ID(PCI_DEVICE_ID_INTEL_Q45_HB),
2321 ID(PCI_DEVICE_ID_INTEL_G45_HB),
2257 { } 2322 { }
2258}; 2323};
2259 2324
diff --git a/drivers/char/agp/nvidia-agp.c b/drivers/char/agp/nvidia-agp.c
index 225ed2a53d4..eaceb61ba2d 100644
--- a/drivers/char/agp/nvidia-agp.c
+++ b/drivers/char/agp/nvidia-agp.c
@@ -214,9 +214,9 @@ static int nvidia_insert_memory(struct agp_memory *mem, off_t pg_start, int type
214 return -EBUSY; 214 return -EBUSY;
215 } 215 }
216 216
217 if (mem->is_flushed == FALSE) { 217 if (!mem->is_flushed) {
218 global_cache_flush(); 218 global_cache_flush();
219 mem->is_flushed = TRUE; 219 mem->is_flushed = true;
220 } 220 }
221 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 221 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
222 writel(agp_bridge->driver->mask_memory(agp_bridge, 222 writel(agp_bridge->driver->mask_memory(agp_bridge,
diff --git a/drivers/char/agp/parisc-agp.c b/drivers/char/agp/parisc-agp.c
index 2939e3570f9..8c42dcc5958 100644
--- a/drivers/char/agp/parisc-agp.c
+++ b/drivers/char/agp/parisc-agp.c
@@ -141,9 +141,9 @@ parisc_agp_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
141 j++; 141 j++;
142 } 142 }
143 143
144 if (mem->is_flushed == FALSE) { 144 if (!mem->is_flushed) {
145 global_cache_flush(); 145 global_cache_flush();
146 mem->is_flushed = TRUE; 146 mem->is_flushed = true;
147 } 147 }
148 148
149 for (i = 0, j = io_pg_start; i < mem->page_count; i++) { 149 for (i = 0, j = io_pg_start; i < mem->page_count; i++) {
@@ -226,7 +226,7 @@ static const struct agp_bridge_driver parisc_agp_driver = {
226 .agp_alloc_page = agp_generic_alloc_page, 226 .agp_alloc_page = agp_generic_alloc_page,
227 .agp_destroy_page = agp_generic_destroy_page, 227 .agp_destroy_page = agp_generic_destroy_page,
228 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 228 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
229 .cant_use_aperture = 1, 229 .cant_use_aperture = true,
230}; 230};
231 231
232static int __init 232static int __init
diff --git a/drivers/char/agp/sgi-agp.c b/drivers/char/agp/sgi-agp.c
index 98cf8abb3e5..b972d83bb1b 100644
--- a/drivers/char/agp/sgi-agp.c
+++ b/drivers/char/agp/sgi-agp.c
@@ -182,9 +182,9 @@ static int sgi_tioca_insert_memory(struct agp_memory *mem, off_t pg_start,
182 j++; 182 j++;
183 } 183 }
184 184
185 if (mem->is_flushed == FALSE) { 185 if (!mem->is_flushed) {
186 bridge->driver->cache_flush(); 186 bridge->driver->cache_flush();
187 mem->is_flushed = TRUE; 187 mem->is_flushed = true;
188 } 188 }
189 189
190 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 190 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
@@ -264,8 +264,8 @@ const struct agp_bridge_driver sgi_tioca_driver = {
264 .agp_alloc_page = sgi_tioca_alloc_page, 264 .agp_alloc_page = sgi_tioca_alloc_page,
265 .agp_destroy_page = agp_generic_destroy_page, 265 .agp_destroy_page = agp_generic_destroy_page,
266 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 266 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
267 .cant_use_aperture = 1, 267 .cant_use_aperture = true,
268 .needs_scratch_page = 0, 268 .needs_scratch_page = false,
269 .num_aperture_sizes = 1, 269 .num_aperture_sizes = 1,
270}; 270};
271 271
diff --git a/drivers/char/agp/sworks-agp.c b/drivers/char/agp/sworks-agp.c
index e08934e58f3..0e054c13449 100644
--- a/drivers/char/agp/sworks-agp.c
+++ b/drivers/char/agp/sworks-agp.c
@@ -339,9 +339,9 @@ static int serverworks_insert_memory(struct agp_memory *mem,
339 j++; 339 j++;
340 } 340 }
341 341
342 if (mem->is_flushed == FALSE) { 342 if (!mem->is_flushed) {
343 global_cache_flush(); 343 global_cache_flush();
344 mem->is_flushed = TRUE; 344 mem->is_flushed = true;
345 } 345 }
346 346
347 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 347 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
@@ -412,7 +412,7 @@ static void serverworks_agp_enable(struct agp_bridge_data *bridge, u32 mode)
412 bridge->capndx + PCI_AGP_COMMAND, 412 bridge->capndx + PCI_AGP_COMMAND,
413 command); 413 command);
414 414
415 agp_device_command(command, 0); 415 agp_device_command(command, false);
416} 416}
417 417
418static const struct agp_bridge_driver sworks_driver = { 418static const struct agp_bridge_driver sworks_driver = {
diff --git a/drivers/char/agp/uninorth-agp.c b/drivers/char/agp/uninorth-agp.c
index 42c0a600b1a..d2fa3cfca02 100644
--- a/drivers/char/agp/uninorth-agp.c
+++ b/drivers/char/agp/uninorth-agp.c
@@ -281,10 +281,10 @@ static void uninorth_agp_enable(struct agp_bridge_data *bridge, u32 mode)
281 281
282 if (uninorth_rev >= 0x30) { 282 if (uninorth_rev >= 0x30) {
283 /* This is an AGP V3 */ 283 /* This is an AGP V3 */
284 agp_device_command(command, (status & AGPSTAT_MODE_3_0)); 284 agp_device_command(command, (status & AGPSTAT_MODE_3_0) != 0);
285 } else { 285 } else {
286 /* AGP V2 */ 286 /* AGP V2 */
287 agp_device_command(command, 0); 287 agp_device_command(command, false);
288 } 288 }
289 289
290 uninorth_tlbflush(NULL); 290 uninorth_tlbflush(NULL);
@@ -511,7 +511,7 @@ const struct agp_bridge_driver uninorth_agp_driver = {
511 .agp_alloc_page = agp_generic_alloc_page, 511 .agp_alloc_page = agp_generic_alloc_page,
512 .agp_destroy_page = agp_generic_destroy_page, 512 .agp_destroy_page = agp_generic_destroy_page,
513 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 513 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
514 .cant_use_aperture = 1, 514 .cant_use_aperture = true,
515}; 515};
516 516
517const struct agp_bridge_driver u3_agp_driver = { 517const struct agp_bridge_driver u3_agp_driver = {
@@ -536,8 +536,8 @@ const struct agp_bridge_driver u3_agp_driver = {
536 .agp_alloc_page = agp_generic_alloc_page, 536 .agp_alloc_page = agp_generic_alloc_page,
537 .agp_destroy_page = agp_generic_destroy_page, 537 .agp_destroy_page = agp_generic_destroy_page,
538 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 538 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
539 .cant_use_aperture = 1, 539 .cant_use_aperture = true,
540 .needs_scratch_page = 1, 540 .needs_scratch_page = true,
541}; 541};
542 542
543static struct agp_device_ids uninorth_agp_device_ids[] __devinitdata = { 543static struct agp_device_ids uninorth_agp_device_ids[] __devinitdata = {
diff --git a/drivers/char/agp/via-agp.c b/drivers/char/agp/via-agp.c
index 0ecc54d327b..7b36476dff4 100644
--- a/drivers/char/agp/via-agp.c
+++ b/drivers/char/agp/via-agp.c
@@ -389,11 +389,20 @@ static struct agp_device_ids via_agp_device_ids[] __devinitdata =
389 .device_id = PCI_DEVICE_ID_VIA_VT3324, 389 .device_id = PCI_DEVICE_ID_VIA_VT3324,
390 .chipset_name = "CX700", 390 .chipset_name = "CX700",
391 }, 391 },
392 /* VT3336 */ 392 /* VT3336 - this is a chipset for AMD Athlon/K8 CPU. Due to K8's unique
393 * architecture, the AGP resource and behavior are different from
394 * the traditional AGP which resides only in chipset. AGP is used
395 * by 3D driver which wasn't available for the VT3336 and VT3364
396 * generation until now. Unfortunately, by testing, VT3364 works
397 * but VT3336 doesn't. - explaination from via, just leave this as
398 * as a placeholder to avoid future patches adding it back in.
399 */
400#if 0
393 { 401 {
394 .device_id = PCI_DEVICE_ID_VIA_VT3336, 402 .device_id = PCI_DEVICE_ID_VIA_VT3336,
395 .chipset_name = "VT3336", 403 .chipset_name = "VT3336",
396 }, 404 },
405#endif
397 /* P4M890 */ 406 /* P4M890 */
398 { 407 {
399 .device_id = PCI_DEVICE_ID_VIA_P4M890, 408 .device_id = PCI_DEVICE_ID_VIA_P4M890,
@@ -546,8 +555,8 @@ static const struct pci_device_id agp_via_pci_table[] = {
546 ID(PCI_DEVICE_ID_VIA_3296_0), 555 ID(PCI_DEVICE_ID_VIA_3296_0),
547 ID(PCI_DEVICE_ID_VIA_P4M800CE), 556 ID(PCI_DEVICE_ID_VIA_P4M800CE),
548 ID(PCI_DEVICE_ID_VIA_VT3324), 557 ID(PCI_DEVICE_ID_VIA_VT3324),
549 ID(PCI_DEVICE_ID_VIA_VT3336),
550 ID(PCI_DEVICE_ID_VIA_P4M890), 558 ID(PCI_DEVICE_ID_VIA_P4M890),
559 ID(PCI_DEVICE_ID_VIA_VT3364),
551 { } 560 { }
552}; 561};
553 562
diff --git a/drivers/char/drm/ati_pcigart.c b/drivers/char/drm/ati_pcigart.c
index b710426bab3..c533d0c9ec6 100644
--- a/drivers/char/drm/ati_pcigart.c
+++ b/drivers/char/drm/ati_pcigart.c
@@ -76,7 +76,7 @@ int drm_ati_pcigart_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info
76 for (i = 0; i < pages; i++) { 76 for (i = 0; i < pages; i++) {
77 if (!entry->busaddr[i]) 77 if (!entry->busaddr[i])
78 break; 78 break;
79 pci_unmap_single(dev->pdev, entry->busaddr[i], 79 pci_unmap_page(dev->pdev, entry->busaddr[i],
80 PAGE_SIZE, PCI_DMA_TODEVICE); 80 PAGE_SIZE, PCI_DMA_TODEVICE);
81 } 81 }
82 82
@@ -137,10 +137,8 @@ int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *ga
137 137
138 for (i = 0; i < pages; i++) { 138 for (i = 0; i < pages; i++) {
139 /* we need to support large memory configurations */ 139 /* we need to support large memory configurations */
140 entry->busaddr[i] = pci_map_single(dev->pdev, 140 entry->busaddr[i] = pci_map_page(dev->pdev, entry->pagelist[i],
141 page_address(entry-> 141 0, PAGE_SIZE, PCI_DMA_TODEVICE);
142 pagelist[i]),
143 PAGE_SIZE, PCI_DMA_TODEVICE);
144 if (entry->busaddr[i] == 0) { 142 if (entry->busaddr[i] == 0) {
145 DRM_ERROR("unable to map PCIGART pages!\n"); 143 DRM_ERROR("unable to map PCIGART pages!\n");
146 drm_ati_pcigart_cleanup(dev, gart_info); 144 drm_ati_pcigart_cleanup(dev, gart_info);
diff --git a/drivers/char/drm/drm.h b/drivers/char/drm/drm.h
index 3a05c6d5ebe..38d3c6b8276 100644
--- a/drivers/char/drm/drm.h
+++ b/drivers/char/drm/drm.h
@@ -628,7 +628,7 @@ struct drm_set_version {
628#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding) 628#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding)
629#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding) 629#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding)
630 630
631#define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, struct drm_scatter_gather) 631#define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather)
632#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather) 632#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather)
633 633
634#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank) 634#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank)
diff --git a/drivers/char/drm/drm_drv.c b/drivers/char/drm/drm_drv.c
index fc54140551a..564138714bb 100644
--- a/drivers/char/drm/drm_drv.c
+++ b/drivers/char/drm/drm_drv.c
@@ -470,17 +470,18 @@ int drm_ioctl(struct inode *inode, struct file *filp,
470 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) && 470 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) &&
471 (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) 471 (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls))
472 ioctl = &dev->driver->ioctls[nr - DRM_COMMAND_BASE]; 472 ioctl = &dev->driver->ioctls[nr - DRM_COMMAND_BASE];
473 else if ((nr >= DRM_COMMAND_END) || (nr < DRM_COMMAND_BASE)) 473 else if ((nr >= DRM_COMMAND_END) || (nr < DRM_COMMAND_BASE)) {
474 ioctl = &drm_ioctls[nr]; 474 ioctl = &drm_ioctls[nr];
475 else 475 cmd = ioctl->cmd;
476 } else
476 goto err_i1; 477 goto err_i1;
477 478
479 /* Do not trust userspace, use our own definition */
478 func = ioctl->func; 480 func = ioctl->func;
479 /* is there a local override? */ 481 /* is there a local override? */
480 if ((nr == DRM_IOCTL_NR(DRM_IOCTL_DMA)) && dev->driver->dma_ioctl) 482 if ((nr == DRM_IOCTL_NR(DRM_IOCTL_DMA)) && dev->driver->dma_ioctl)
481 func = dev->driver->dma_ioctl; 483 func = dev->driver->dma_ioctl;
482 484
483
484 if (!func) { 485 if (!func) {
485 DRM_DEBUG("no function\n"); 486 DRM_DEBUG("no function\n");
486 retcode = -EINVAL; 487 retcode = -EINVAL;
diff --git a/drivers/char/drm/drm_pciids.h b/drivers/char/drm/drm_pciids.h
index a6a499f97e2..135bd19499f 100644
--- a/drivers/char/drm/drm_pciids.h
+++ b/drivers/char/drm/drm_pciids.h
@@ -103,20 +103,18 @@
103 {0x1002, 0x5653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 103 {0x1002, 0x5653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
104 {0x1002, 0x5834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP}, \ 104 {0x1002, 0x5834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP}, \
105 {0x1002, 0x5835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \ 105 {0x1002, 0x5835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \
106 {0x1002, 0x5954, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ 106 {0x1002, 0x5954, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
107 {0x1002, 0x5955, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ 107 {0x1002, 0x5955, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
108 {0x1002, 0x5974, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ 108 {0x1002, 0x5974, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
109 {0x1002, 0x5975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ 109 {0x1002, 0x5975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
110 {0x1002, 0x5960, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ 110 {0x1002, 0x5960, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
111 {0x1002, 0x5961, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ 111 {0x1002, 0x5961, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
112 {0x1002, 0x5962, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ 112 {0x1002, 0x5962, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
113 {0x1002, 0x5964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ 113 {0x1002, 0x5964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
114 {0x1002, 0x5965, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ 114 {0x1002, 0x5965, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
115 {0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \ 115 {0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
116 {0x1002, 0x5a41, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ 116 {0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
117 {0x1002, 0x5a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ 117 {0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
118 {0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
119 {0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
120 {0x1002, 0x5b60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ 118 {0x1002, 0x5b60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
121 {0x1002, 0x5b62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ 119 {0x1002, 0x5b62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
122 {0x1002, 0x5b63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ 120 {0x1002, 0x5b63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
@@ -411,4 +409,7 @@
411 {0x8086, 0x2a02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ 409 {0x8086, 0x2a02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
412 {0x8086, 0x2a12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ 410 {0x8086, 0x2a12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
413 {0x8086, 0x2a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ 411 {0x8086, 0x2a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
412 {0x8086, 0x2e02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
413 {0x8086, 0x2e12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
414 {0x8086, 0x2e22, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
414 {0, 0, 0} 415 {0, 0, 0}
diff --git a/drivers/char/drm/i915_drv.c b/drivers/char/drm/i915_drv.c
index e8f3d682e3b..93aed1c38bd 100644
--- a/drivers/char/drm/i915_drv.c
+++ b/drivers/char/drm/i915_drv.c
@@ -389,6 +389,7 @@ static int i915_resume(struct drm_device *dev)
389 pci_restore_state(dev->pdev); 389 pci_restore_state(dev->pdev);
390 if (pci_enable_device(dev->pdev)) 390 if (pci_enable_device(dev->pdev))
391 return -1; 391 return -1;
392 pci_set_master(dev->pdev);
392 393
393 pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB); 394 pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
394 395
diff --git a/drivers/char/drm/i915_drv.h b/drivers/char/drm/i915_drv.h
index 1b20f7c0639..d7326d92a23 100644
--- a/drivers/char/drm/i915_drv.h
+++ b/drivers/char/drm/i915_drv.h
@@ -1112,12 +1112,19 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
1112 (dev)->pci_device == 0x29A2 || \ 1112 (dev)->pci_device == 0x29A2 || \
1113 (dev)->pci_device == 0x2A02 || \ 1113 (dev)->pci_device == 0x2A02 || \
1114 (dev)->pci_device == 0x2A12 || \ 1114 (dev)->pci_device == 0x2A12 || \
1115 (dev)->pci_device == 0x2A42) 1115 (dev)->pci_device == 0x2A42 || \
1116 (dev)->pci_device == 0x2E02 || \
1117 (dev)->pci_device == 0x2E12 || \
1118 (dev)->pci_device == 0x2E22)
1116 1119
1117#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02) 1120#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
1118 1121
1119#define IS_IGD_GM(dev) ((dev)->pci_device == 0x2A42) 1122#define IS_IGD_GM(dev) ((dev)->pci_device == 0x2A42)
1120 1123
1124#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
1125 (dev)->pci_device == 0x2E12 || \
1126 (dev)->pci_device == 0x2E22)
1127
1121#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \ 1128#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
1122 (dev)->pci_device == 0x29B2 || \ 1129 (dev)->pci_device == 0x29B2 || \
1123 (dev)->pci_device == 0x29D2) 1130 (dev)->pci_device == 0x29D2)
@@ -1128,7 +1135,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
1128#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \ 1135#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
1129 IS_I945GM(dev) || IS_I965GM(dev) || IS_IGD_GM(dev)) 1136 IS_I945GM(dev) || IS_I965GM(dev) || IS_IGD_GM(dev))
1130 1137
1131#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_IGD_GM(dev)) 1138#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_IGD_GM(dev) || IS_G4X(dev))
1132 1139
1133#define PRIMARY_RINGBUFFER_SIZE (128*1024) 1140#define PRIMARY_RINGBUFFER_SIZE (128*1024)
1134 1141
diff --git a/drivers/char/drm/r300_cmdbuf.c b/drivers/char/drm/r300_cmdbuf.c
index f535812e405..702df45320f 100644
--- a/drivers/char/drm/r300_cmdbuf.c
+++ b/drivers/char/drm/r300_cmdbuf.c
@@ -189,18 +189,12 @@ void r300_init_reg_flags(struct drm_device *dev)
189 ADD_RANGE(R300_RE_CULL_CNTL, 1); 189 ADD_RANGE(R300_RE_CULL_CNTL, 1);
190 ADD_RANGE(0x42C0, 2); 190 ADD_RANGE(0x42C0, 2);
191 ADD_RANGE(R300_RS_CNTL_0, 2); 191 ADD_RANGE(R300_RS_CNTL_0, 2);
192 ADD_RANGE(R300_RS_INTERP_0, 8); 192
193 ADD_RANGE(R300_RS_ROUTE_0, 8); 193 ADD_RANGE(R300_SC_HYPERZ, 2);
194 ADD_RANGE(0x43A4, 2);
195 ADD_RANGE(0x43E8, 1); 194 ADD_RANGE(0x43E8, 1);
196 ADD_RANGE(R300_PFS_CNTL_0, 3); 195
197 ADD_RANGE(R300_PFS_NODE_0, 4);
198 ADD_RANGE(R300_PFS_TEXI_0, 64);
199 ADD_RANGE(0x46A4, 5); 196 ADD_RANGE(0x46A4, 5);
200 ADD_RANGE(R300_PFS_INSTR0_0, 64); 197
201 ADD_RANGE(R300_PFS_INSTR1_0, 64);
202 ADD_RANGE(R300_PFS_INSTR2_0, 64);
203 ADD_RANGE(R300_PFS_INSTR3_0, 64);
204 ADD_RANGE(R300_RE_FOG_STATE, 1); 198 ADD_RANGE(R300_RE_FOG_STATE, 1);
205 ADD_RANGE(R300_FOG_COLOR_R, 3); 199 ADD_RANGE(R300_FOG_COLOR_R, 3);
206 ADD_RANGE(R300_PP_ALPHA_TEST, 2); 200 ADD_RANGE(R300_PP_ALPHA_TEST, 2);
@@ -215,14 +209,12 @@ void r300_init_reg_flags(struct drm_device *dev)
215 ADD_RANGE(0x4E50, 9); 209 ADD_RANGE(0x4E50, 9);
216 ADD_RANGE(0x4E88, 1); 210 ADD_RANGE(0x4E88, 1);
217 ADD_RANGE(0x4EA0, 2); 211 ADD_RANGE(0x4EA0, 2);
218 ADD_RANGE(R300_RB3D_ZSTENCIL_CNTL_0, 3); 212 ADD_RANGE(R300_ZB_CNTL, 3);
219 ADD_RANGE(R300_RB3D_ZSTENCIL_FORMAT, 4); 213 ADD_RANGE(R300_ZB_FORMAT, 4);
220 ADD_RANGE_MARK(R300_RB3D_DEPTHOFFSET, 1, MARK_CHECK_OFFSET); /* check offset */ 214 ADD_RANGE_MARK(R300_ZB_DEPTHOFFSET, 1, MARK_CHECK_OFFSET); /* check offset */
221 ADD_RANGE(R300_RB3D_DEPTHPITCH, 1); 215 ADD_RANGE(R300_ZB_DEPTHPITCH, 1);
222 ADD_RANGE(0x4F28, 1); 216 ADD_RANGE(R300_ZB_DEPTHCLEARVALUE, 1);
223 ADD_RANGE(0x4F30, 2); 217 ADD_RANGE(R300_ZB_ZMASK_OFFSET, 13);
224 ADD_RANGE(0x4F44, 1);
225 ADD_RANGE(0x4F54, 1);
226 218
227 ADD_RANGE(R300_TX_FILTER_0, 16); 219 ADD_RANGE(R300_TX_FILTER_0, 16);
228 ADD_RANGE(R300_TX_FILTER1_0, 16); 220 ADD_RANGE(R300_TX_FILTER1_0, 16);
@@ -235,13 +227,32 @@ void r300_init_reg_flags(struct drm_device *dev)
235 ADD_RANGE(R300_TX_BORDER_COLOR_0, 16); 227 ADD_RANGE(R300_TX_BORDER_COLOR_0, 16);
236 228
237 /* Sporadic registers used as primitives are emitted */ 229 /* Sporadic registers used as primitives are emitted */
238 ADD_RANGE(R300_RB3D_ZCACHE_CTLSTAT, 1); 230 ADD_RANGE(R300_ZB_ZCACHE_CTLSTAT, 1);
239 ADD_RANGE(R300_RB3D_DSTCACHE_CTLSTAT, 1); 231 ADD_RANGE(R300_RB3D_DSTCACHE_CTLSTAT, 1);
240 ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0, 8); 232 ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0, 8);
241 ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8); 233 ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8);
242 234
243 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) { 235 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
244 ADD_RANGE(0x4074, 16); 236 ADD_RANGE(R500_VAP_INDEX_OFFSET, 1);
237 ADD_RANGE(R500_US_CONFIG, 2);
238 ADD_RANGE(R500_US_CODE_ADDR, 3);
239 ADD_RANGE(R500_US_FC_CTRL, 1);
240 ADD_RANGE(R500_RS_IP_0, 16);
241 ADD_RANGE(R500_RS_INST_0, 16);
242 ADD_RANGE(R500_RB3D_COLOR_CLEAR_VALUE_AR, 2);
243 ADD_RANGE(R500_RB3D_CONSTANT_COLOR_AR, 2);
244 ADD_RANGE(R500_ZB_FIFO_SIZE, 2);
245 } else {
246 ADD_RANGE(R300_PFS_CNTL_0, 3);
247 ADD_RANGE(R300_PFS_NODE_0, 4);
248 ADD_RANGE(R300_PFS_TEXI_0, 64);
249 ADD_RANGE(R300_PFS_INSTR0_0, 64);
250 ADD_RANGE(R300_PFS_INSTR1_0, 64);
251 ADD_RANGE(R300_PFS_INSTR2_0, 64);
252 ADD_RANGE(R300_PFS_INSTR3_0, 64);
253 ADD_RANGE(R300_RS_INTERP_0, 8);
254 ADD_RANGE(R300_RS_ROUTE_0, 8);
255
245 } 256 }
246} 257}
247 258
@@ -707,8 +718,9 @@ static __inline__ void r300_pacify(drm_radeon_private_t *dev_priv)
707 BEGIN_RING(6); 718 BEGIN_RING(6);
708 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 719 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
709 OUT_RING(R300_RB3D_DSTCACHE_UNKNOWN_0A); 720 OUT_RING(R300_RB3D_DSTCACHE_UNKNOWN_0A);
710 OUT_RING(CP_PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 721 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0));
711 OUT_RING(R300_RB3D_ZCACHE_UNKNOWN_03); 722 OUT_RING(R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE|
723 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
712 OUT_RING(CP_PACKET3(RADEON_CP_NOP, 0)); 724 OUT_RING(CP_PACKET3(RADEON_CP_NOP, 0));
713 OUT_RING(0x0); 725 OUT_RING(0x0);
714 ADVANCE_RING(); 726 ADVANCE_RING();
@@ -829,6 +841,54 @@ static int r300_scratch(drm_radeon_private_t *dev_priv,
829} 841}
830 842
831/** 843/**
844 * Uploads user-supplied vertex program instructions or parameters onto
845 * the graphics card.
846 * Called by r300_do_cp_cmdbuf.
847 */
848static inline int r300_emit_r500fp(drm_radeon_private_t *dev_priv,
849 drm_radeon_kcmd_buffer_t *cmdbuf,
850 drm_r300_cmd_header_t header)
851{
852 int sz;
853 int addr;
854 int type;
855 int clamp;
856 int stride;
857 RING_LOCALS;
858
859 sz = header.r500fp.count;
860 /* address is 9 bits 0 - 8, bit 1 of flags is part of address */
861 addr = ((header.r500fp.adrhi_flags & 1) << 8) | header.r500fp.adrlo;
862
863 type = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE);
864 clamp = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP);
865
866 addr |= (type << 16);
867 addr |= (clamp << 17);
868
869 stride = type ? 4 : 6;
870
871 DRM_DEBUG("r500fp %d %d type: %d\n", sz, addr, type);
872 if (!sz)
873 return 0;
874 if (sz * stride * 4 > cmdbuf->bufsz)
875 return -EINVAL;
876
877 BEGIN_RING(3 + sz * stride);
878 OUT_RING_REG(R500_GA_US_VECTOR_INDEX, addr);
879 OUT_RING(CP_PACKET0_TABLE(R500_GA_US_VECTOR_DATA, sz * stride - 1));
880 OUT_RING_TABLE((int *)cmdbuf->buf, sz * stride);
881
882 ADVANCE_RING();
883
884 cmdbuf->buf += sz * stride * 4;
885 cmdbuf->bufsz -= sz * stride * 4;
886
887 return 0;
888}
889
890
891/**
832 * Parses and validates a user-supplied command buffer and emits appropriate 892 * Parses and validates a user-supplied command buffer and emits appropriate
833 * commands on the DMA ring buffer. 893 * commands on the DMA ring buffer.
834 * Called by the ioctl handler function radeon_cp_cmdbuf. 894 * Called by the ioctl handler function radeon_cp_cmdbuf.
@@ -963,6 +1023,19 @@ int r300_do_cp_cmdbuf(struct drm_device *dev,
963 } 1023 }
964 break; 1024 break;
965 1025
1026 case R300_CMD_R500FP:
1027 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) {
1028 DRM_ERROR("Calling r500 command on r300 card\n");
1029 ret = -EINVAL;
1030 goto cleanup;
1031 }
1032 DRM_DEBUG("R300_CMD_R500FP\n");
1033 ret = r300_emit_r500fp(dev_priv, cmdbuf, header);
1034 if (ret) {
1035 DRM_ERROR("r300_emit_r500fp failed\n");
1036 goto cleanup;
1037 }
1038 break;
966 default: 1039 default:
967 DRM_ERROR("bad cmd_type %i at %p\n", 1040 DRM_ERROR("bad cmd_type %i at %p\n",
968 header.header.cmd_type, 1041 header.header.cmd_type,
diff --git a/drivers/char/drm/r300_reg.h b/drivers/char/drm/r300_reg.h
index 8f664af9c4a..a6802f26afc 100644
--- a/drivers/char/drm/r300_reg.h
+++ b/drivers/char/drm/r300_reg.h
@@ -702,6 +702,27 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
702# define R300_RS_ROUTE_1_UNKNOWN11 (1 << 11) 702# define R300_RS_ROUTE_1_UNKNOWN11 (1 << 11)
703/* END: Rasterization / Interpolators - many guesses */ 703/* END: Rasterization / Interpolators - many guesses */
704 704
705/* Hierarchical Z Enable */
706#define R300_SC_HYPERZ 0x43a4
707# define R300_SC_HYPERZ_DISABLE (0 << 0)
708# define R300_SC_HYPERZ_ENABLE (1 << 0)
709# define R300_SC_HYPERZ_MIN (0 << 1)
710# define R300_SC_HYPERZ_MAX (1 << 1)
711# define R300_SC_HYPERZ_ADJ_256 (0 << 2)
712# define R300_SC_HYPERZ_ADJ_128 (1 << 2)
713# define R300_SC_HYPERZ_ADJ_64 (2 << 2)
714# define R300_SC_HYPERZ_ADJ_32 (3 << 2)
715# define R300_SC_HYPERZ_ADJ_16 (4 << 2)
716# define R300_SC_HYPERZ_ADJ_8 (5 << 2)
717# define R300_SC_HYPERZ_ADJ_4 (6 << 2)
718# define R300_SC_HYPERZ_ADJ_2 (7 << 2)
719# define R300_SC_HYPERZ_HZ_Z0MIN_NO (0 << 5)
720# define R300_SC_HYPERZ_HZ_Z0MIN (1 << 5)
721# define R300_SC_HYPERZ_HZ_Z0MAX_NO (0 << 6)
722# define R300_SC_HYPERZ_HZ_Z0MAX (1 << 6)
723
724#define R300_SC_EDGERULE 0x43a8
725
705/* BEGIN: Scissors and cliprects */ 726/* BEGIN: Scissors and cliprects */
706 727
707/* There are four clipping rectangles. Their corner coordinates are inclusive. 728/* There are four clipping rectangles. Their corner coordinates are inclusive.
@@ -1346,7 +1367,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
1346/* Guess by Vladimir. 1367/* Guess by Vladimir.
1347 * Set to 0A before 3D operations, set to 02 afterwards. 1368 * Set to 0A before 3D operations, set to 02 afterwards.
1348 */ 1369 */
1349#define R300_RB3D_DSTCACHE_CTLSTAT 0x4E4C 1370/*#define R300_RB3D_DSTCACHE_CTLSTAT 0x4E4C*/
1350# define R300_RB3D_DSTCACHE_UNKNOWN_02 0x00000002 1371# define R300_RB3D_DSTCACHE_UNKNOWN_02 0x00000002
1351# define R300_RB3D_DSTCACHE_UNKNOWN_0A 0x0000000A 1372# define R300_RB3D_DSTCACHE_UNKNOWN_0A 0x0000000A
1352 1373
@@ -1355,19 +1376,14 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
1355 * for this. 1376 * for this.
1356 * Bit (1<<8) is the "test" bit. so plain write is 6 - vd 1377 * Bit (1<<8) is the "test" bit. so plain write is 6 - vd
1357 */ 1378 */
1358#define R300_RB3D_ZSTENCIL_CNTL_0 0x4F00 1379#define R300_ZB_CNTL 0x4F00
1359# define R300_RB3D_Z_DISABLED_1 0x00000010 1380# define R300_STENCIL_ENABLE (1 << 0)
1360# define R300_RB3D_Z_DISABLED_2 0x00000014 1381# define R300_Z_ENABLE (1 << 1)
1361# define R300_RB3D_Z_TEST 0x00000012 1382# define R300_Z_WRITE_ENABLE (1 << 2)
1362# define R300_RB3D_Z_TEST_AND_WRITE 0x00000016 1383# define R300_Z_SIGNED_COMPARE (1 << 3)
1363# define R300_RB3D_Z_WRITE_ONLY 0x00000006 1384# define R300_STENCIL_FRONT_BACK (1 << 4)
1364 1385
1365# define R300_RB3D_Z_TEST 0x00000012 1386#define R300_ZB_ZSTENCILCNTL 0x4f04
1366# define R300_RB3D_Z_TEST_AND_WRITE 0x00000016
1367# define R300_RB3D_Z_WRITE_ONLY 0x00000006
1368# define R300_RB3D_STENCIL_ENABLE 0x00000001
1369
1370#define R300_RB3D_ZSTENCIL_CNTL_1 0x4F04
1371 /* functions */ 1387 /* functions */
1372# define R300_ZS_NEVER 0 1388# define R300_ZS_NEVER 0
1373# define R300_ZS_LESS 1 1389# define R300_ZS_LESS 1
@@ -1387,52 +1403,166 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
1387# define R300_ZS_INVERT 5 1403# define R300_ZS_INVERT 5
1388# define R300_ZS_INCR_WRAP 6 1404# define R300_ZS_INCR_WRAP 6
1389# define R300_ZS_DECR_WRAP 7 1405# define R300_ZS_DECR_WRAP 7
1406# define R300_Z_FUNC_SHIFT 0
1390 /* front and back refer to operations done for front 1407 /* front and back refer to operations done for front
1391 and back faces, i.e. separate stencil function support */ 1408 and back faces, i.e. separate stencil function support */
1392# define R300_RB3D_ZS1_DEPTH_FUNC_SHIFT 0 1409# define R300_S_FRONT_FUNC_SHIFT 3
1393# define R300_RB3D_ZS1_FRONT_FUNC_SHIFT 3 1410# define R300_S_FRONT_SFAIL_OP_SHIFT 6
1394# define R300_RB3D_ZS1_FRONT_FAIL_OP_SHIFT 6 1411# define R300_S_FRONT_ZPASS_OP_SHIFT 9
1395# define R300_RB3D_ZS1_FRONT_ZPASS_OP_SHIFT 9 1412# define R300_S_FRONT_ZFAIL_OP_SHIFT 12
1396# define R300_RB3D_ZS1_FRONT_ZFAIL_OP_SHIFT 12 1413# define R300_S_BACK_FUNC_SHIFT 15
1397# define R300_RB3D_ZS1_BACK_FUNC_SHIFT 15 1414# define R300_S_BACK_SFAIL_OP_SHIFT 18
1398# define R300_RB3D_ZS1_BACK_FAIL_OP_SHIFT 18 1415# define R300_S_BACK_ZPASS_OP_SHIFT 21
1399# define R300_RB3D_ZS1_BACK_ZPASS_OP_SHIFT 21 1416# define R300_S_BACK_ZFAIL_OP_SHIFT 24
1400# define R300_RB3D_ZS1_BACK_ZFAIL_OP_SHIFT 24 1417
1401 1418#define R300_ZB_STENCILREFMASK 0x4f08
1402#define R300_RB3D_ZSTENCIL_CNTL_2 0x4F08 1419# define R300_STENCILREF_SHIFT 0
1403# define R300_RB3D_ZS2_STENCIL_REF_SHIFT 0 1420# define R300_STENCILREF_MASK 0x000000ff
1404# define R300_RB3D_ZS2_STENCIL_MASK 0xFF 1421# define R300_STENCILMASK_SHIFT 8
1405# define R300_RB3D_ZS2_STENCIL_MASK_SHIFT 8 1422# define R300_STENCILMASK_MASK 0x0000ff00
1406# define R300_RB3D_ZS2_STENCIL_WRITE_MASK_SHIFT 16 1423# define R300_STENCILWRITEMASK_SHIFT 16
1424# define R300_STENCILWRITEMASK_MASK 0x00ff0000
1407 1425
1408/* gap */ 1426/* gap */
1409 1427
1410#define R300_RB3D_ZSTENCIL_FORMAT 0x4F10 1428#define R300_ZB_FORMAT 0x4f10
1411# define R300_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) 1429# define R300_DEPTHFORMAT_16BIT_INT_Z (0 << 0)
1412# define R300_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) 1430# define R300_DEPTHFORMAT_16BIT_13E3 (1 << 0)
1413 /* 16 bit format or some aditional bit ? */ 1431# define R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL (2 << 0)
1414# define R300_DEPTH_FORMAT_UNK32 (32 << 0) 1432/* reserved up to (15 << 0) */
1433# define R300_INVERT_13E3_LEADING_ONES (0 << 4)
1434# define R300_INVERT_13E3_LEADING_ZEROS (1 << 4)
1415 1435
1416#define R300_RB3D_EARLY_Z 0x4F14 1436#define R300_ZB_ZTOP 0x4F14
1417# define R300_EARLY_Z_DISABLE (0 << 0) 1437# define R300_ZTOP_DISABLE (0 << 0)
1418# define R300_EARLY_Z_ENABLE (1 << 0) 1438# define R300_ZTOP_ENABLE (1 << 0)
1419 1439
1420/* gap */ 1440/* gap */
1421 1441
1422#define R300_RB3D_ZCACHE_CTLSTAT 0x4F18 /* GUESS */ 1442#define R300_ZB_ZCACHE_CTLSTAT 0x4f18
1423# define R300_RB3D_ZCACHE_UNKNOWN_01 0x1 1443# define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_NO_EFFECT (0 << 0)
1424# define R300_RB3D_ZCACHE_UNKNOWN_03 0x3 1444# define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE (1 << 0)
1445# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT (0 << 1)
1446# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE (1 << 1)
1447# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE (0 << 31)
1448# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1 << 31)
1449
1450#define R300_ZB_BW_CNTL 0x4f1c
1451# define R300_HIZ_DISABLE (0 << 0)
1452# define R300_HIZ_ENABLE (1 << 0)
1453# define R300_HIZ_MIN (0 << 1)
1454# define R300_HIZ_MAX (1 << 1)
1455# define R300_FAST_FILL_DISABLE (0 << 2)
1456# define R300_FAST_FILL_ENABLE (1 << 2)
1457# define R300_RD_COMP_DISABLE (0 << 3)
1458# define R300_RD_COMP_ENABLE (1 << 3)
1459# define R300_WR_COMP_DISABLE (0 << 4)
1460# define R300_WR_COMP_ENABLE (1 << 4)
1461# define R300_ZB_CB_CLEAR_RMW (0 << 5)
1462# define R300_ZB_CB_CLEAR_CACHE_LINEAR (1 << 5)
1463# define R300_FORCE_COMPRESSED_STENCIL_VALUE_DISABLE (0 << 6)
1464# define R300_FORCE_COMPRESSED_STENCIL_VALUE_ENABLE (1 << 6)
1465
1466# define R500_ZEQUAL_OPTIMIZE_ENABLE (0 << 7)
1467# define R500_ZEQUAL_OPTIMIZE_DISABLE (1 << 7)
1468# define R500_SEQUAL_OPTIMIZE_ENABLE (0 << 8)
1469# define R500_SEQUAL_OPTIMIZE_DISABLE (1 << 8)
1470
1471# define R500_BMASK_ENABLE (0 << 10)
1472# define R500_BMASK_DISABLE (1 << 10)
1473# define R500_HIZ_EQUAL_REJECT_DISABLE (0 << 11)
1474# define R500_HIZ_EQUAL_REJECT_ENABLE (1 << 11)
1475# define R500_HIZ_FP_EXP_BITS_DISABLE (0 << 12)
1476# define R500_HIZ_FP_EXP_BITS_1 (1 << 12)
1477# define R500_HIZ_FP_EXP_BITS_2 (2 << 12)
1478# define R500_HIZ_FP_EXP_BITS_3 (3 << 12)
1479# define R500_HIZ_FP_EXP_BITS_4 (4 << 12)
1480# define R500_HIZ_FP_EXP_BITS_5 (5 << 12)
1481# define R500_HIZ_FP_INVERT_LEADING_ONES (0 << 15)
1482# define R500_HIZ_FP_INVERT_LEADING_ZEROS (1 << 15)
1483# define R500_TILE_OVERWRITE_RECOMPRESSION_ENABLE (0 << 16)
1484# define R500_TILE_OVERWRITE_RECOMPRESSION_DISABLE (1 << 16)
1485# define R500_CONTIGUOUS_6XAA_SAMPLES_ENABLE (0 << 17)
1486# define R500_CONTIGUOUS_6XAA_SAMPLES_DISABLE (1 << 17)
1487# define R500_PEQ_PACKING_DISABLE (0 << 18)
1488# define R500_PEQ_PACKING_ENABLE (1 << 18)
1489# define R500_COVERED_PTR_MASKING_DISABLE (0 << 18)
1490# define R500_COVERED_PTR_MASKING_ENABLE (1 << 18)
1491
1425 1492
1426/* gap */ 1493/* gap */
1427 1494
1428#define R300_RB3D_DEPTHOFFSET 0x4F20 1495/* Z Buffer Address Offset.
1429#define R300_RB3D_DEPTHPITCH 0x4F24 1496 * Bits 31 to 5 are used for aligned Z buffer address offset for macro tiles.
1430# define R300_DEPTHPITCH_MASK 0x00001FF8 /* GUESS */ 1497 */
1431# define R300_DEPTH_TILE_ENABLE (1 << 16) /* GUESS */ 1498#define R300_ZB_DEPTHOFFSET 0x4f20
1432# define R300_DEPTH_MICROTILE_ENABLE (1 << 17) /* GUESS */ 1499
1433# define R300_DEPTH_ENDIAN_NO_SWAP (0 << 18) /* GUESS */ 1500/* Z Buffer Pitch and Endian Control */
1434# define R300_DEPTH_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */ 1501#define R300_ZB_DEPTHPITCH 0x4f24
1435# define R300_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */ 1502# define R300_DEPTHPITCH_MASK 0x00003FFC
1503# define R300_DEPTHMACROTILE_DISABLE (0 << 16)
1504# define R300_DEPTHMACROTILE_ENABLE (1 << 16)
1505# define R300_DEPTHMICROTILE_LINEAR (0 << 17)
1506# define R300_DEPTHMICROTILE_TILED (1 << 17)
1507# define R300_DEPTHMICROTILE_TILED_SQUARE (2 << 17)
1508# define R300_DEPTHENDIAN_NO_SWAP (0 << 18)
1509# define R300_DEPTHENDIAN_WORD_SWAP (1 << 18)
1510# define R300_DEPTHENDIAN_DWORD_SWAP (2 << 18)
1511# define R300_DEPTHENDIAN_HALF_DWORD_SWAP (3 << 18)
1512
1513/* Z Buffer Clear Value */
1514#define R300_ZB_DEPTHCLEARVALUE 0x4f28
1515
1516#define R300_ZB_ZMASK_OFFSET 0x4f30
1517#define R300_ZB_ZMASK_PITCH 0x4f34
1518#define R300_ZB_ZMASK_WRINDEX 0x4f38
1519#define R300_ZB_ZMASK_DWORD 0x4f3c
1520#define R300_ZB_ZMASK_RDINDEX 0x4f40
1521
1522/* Hierarchical Z Memory Offset */
1523#define R300_ZB_HIZ_OFFSET 0x4f44
1524
1525/* Hierarchical Z Write Index */
1526#define R300_ZB_HIZ_WRINDEX 0x4f48
1527
1528/* Hierarchical Z Data */
1529#define R300_ZB_HIZ_DWORD 0x4f4c
1530
1531/* Hierarchical Z Read Index */
1532#define R300_ZB_HIZ_RDINDEX 0x4f50
1533
1534/* Hierarchical Z Pitch */
1535#define R300_ZB_HIZ_PITCH 0x4f54
1536
1537/* Z Buffer Z Pass Counter Data */
1538#define R300_ZB_ZPASS_DATA 0x4f58
1539
1540/* Z Buffer Z Pass Counter Address */
1541#define R300_ZB_ZPASS_ADDR 0x4f5c
1542
1543/* Depth buffer X and Y coordinate offset */
1544#define R300_ZB_DEPTHXY_OFFSET 0x4f60
1545# define R300_DEPTHX_OFFSET_SHIFT 1
1546# define R300_DEPTHX_OFFSET_MASK 0x000007FE
1547# define R300_DEPTHY_OFFSET_SHIFT 17
1548# define R300_DEPTHY_OFFSET_MASK 0x07FE0000
1549
1550/* Sets the fifo sizes */
1551#define R500_ZB_FIFO_SIZE 0x4fd0
1552# define R500_OP_FIFO_SIZE_FULL (0 << 0)
1553# define R500_OP_FIFO_SIZE_HALF (1 << 0)
1554# define R500_OP_FIFO_SIZE_QUATER (2 << 0)
1555# define R500_OP_FIFO_SIZE_EIGTHS (4 << 0)
1556
1557/* Stencil Reference Value and Mask for backfacing quads */
1558/* R300_ZB_STENCILREFMASK handles front face */
1559#define R500_ZB_STENCILREFMASK_BF 0x4fd4
1560# define R500_STENCILREF_SHIFT 0
1561# define R500_STENCILREF_MASK 0x000000ff
1562# define R500_STENCILMASK_SHIFT 8
1563# define R500_STENCILMASK_MASK 0x0000ff00
1564# define R500_STENCILWRITEMASK_SHIFT 16
1565# define R500_STENCILWRITEMASK_MASK 0x00ff0000
1436 1566
1437/* BEGIN: Vertex program instruction set */ 1567/* BEGIN: Vertex program instruction set */
1438 1568
@@ -1623,4 +1753,20 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
1623 */ 1753 */
1624#define R300_CP_CMD_BITBLT_MULTI 0xC0009B00 1754#define R300_CP_CMD_BITBLT_MULTI 0xC0009B00
1625 1755
1756#define R500_VAP_INDEX_OFFSET 0x208c
1757
1758#define R500_GA_US_VECTOR_INDEX 0x4250
1759#define R500_GA_US_VECTOR_DATA 0x4254
1760
1761#define R500_RS_IP_0 0x4074
1762#define R500_RS_INST_0 0x4320
1763
1764#define R500_US_CONFIG 0x4600
1765
1766#define R500_US_FC_CTRL 0x4624
1767#define R500_US_CODE_ADDR 0x4630
1768
1769#define R500_RB3D_COLOR_CLEAR_VALUE_AR 0x46c0
1770#define R500_RB3D_CONSTANT_COLOR_AR 0x4ef8
1771
1626#endif /* _R300_REG_H */ 1772#endif /* _R300_REG_H */
diff --git a/drivers/char/drm/radeon_cp.c b/drivers/char/drm/radeon_cp.c
index f6f6c92bf77..e53158f0ecb 100644
--- a/drivers/char/drm/radeon_cp.c
+++ b/drivers/char/drm/radeon_cp.c
@@ -2,6 +2,7 @@
2/* 2/*
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2007 Advanced Micro Devices, Inc.
5 * All Rights Reserved. 6 * All Rights Reserved.
6 * 7 *
7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * Permission is hereby granted, free of charge, to any person obtaining a
@@ -34,789 +35,13 @@
34#include "radeon_drv.h" 35#include "radeon_drv.h"
35#include "r300_reg.h" 36#include "r300_reg.h"
36 37
38#include "radeon_microcode.h"
39
37#define RADEON_FIFO_DEBUG 0 40#define RADEON_FIFO_DEBUG 0
38 41
39static int radeon_do_cleanup_cp(struct drm_device * dev); 42static int radeon_do_cleanup_cp(struct drm_device * dev);
40 43
41/* CP microcode (from ATI) */ 44static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
42static const u32 R200_cp_microcode[][2] = {
43 {0x21007000, 0000000000},
44 {0x20007000, 0000000000},
45 {0x000000ab, 0x00000004},
46 {0x000000af, 0x00000004},
47 {0x66544a49, 0000000000},
48 {0x49494174, 0000000000},
49 {0x54517d83, 0000000000},
50 {0x498d8b64, 0000000000},
51 {0x49494949, 0000000000},
52 {0x49da493c, 0000000000},
53 {0x49989898, 0000000000},
54 {0xd34949d5, 0000000000},
55 {0x9dc90e11, 0000000000},
56 {0xce9b9b9b, 0000000000},
57 {0x000f0000, 0x00000016},
58 {0x352e232c, 0000000000},
59 {0x00000013, 0x00000004},
60 {0x000f0000, 0x00000016},
61 {0x352e272c, 0000000000},
62 {0x000f0001, 0x00000016},
63 {0x3239362f, 0000000000},
64 {0x000077ef, 0x00000002},
65 {0x00061000, 0x00000002},
66 {0x00000020, 0x0000001a},
67 {0x00004000, 0x0000001e},
68 {0x00061000, 0x00000002},
69 {0x00000020, 0x0000001a},
70 {0x00004000, 0x0000001e},
71 {0x00061000, 0x00000002},
72 {0x00000020, 0x0000001a},
73 {0x00004000, 0x0000001e},
74 {0x00000016, 0x00000004},
75 {0x0003802a, 0x00000002},
76 {0x040067e0, 0x00000002},
77 {0x00000016, 0x00000004},
78 {0x000077e0, 0x00000002},
79 {0x00065000, 0x00000002},
80 {0x000037e1, 0x00000002},
81 {0x040067e1, 0x00000006},
82 {0x000077e0, 0x00000002},
83 {0x000077e1, 0x00000002},
84 {0x000077e1, 0x00000006},
85 {0xffffffff, 0000000000},
86 {0x10000000, 0000000000},
87 {0x0003802a, 0x00000002},
88 {0x040067e0, 0x00000006},
89 {0x00007675, 0x00000002},
90 {0x00007676, 0x00000002},
91 {0x00007677, 0x00000002},
92 {0x00007678, 0x00000006},
93 {0x0003802b, 0x00000002},
94 {0x04002676, 0x00000002},
95 {0x00007677, 0x00000002},
96 {0x00007678, 0x00000006},
97 {0x0000002e, 0x00000018},
98 {0x0000002e, 0x00000018},
99 {0000000000, 0x00000006},
100 {0x0000002f, 0x00000018},
101 {0x0000002f, 0x00000018},
102 {0000000000, 0x00000006},
103 {0x01605000, 0x00000002},
104 {0x00065000, 0x00000002},
105 {0x00098000, 0x00000002},
106 {0x00061000, 0x00000002},
107 {0x64c0603d, 0x00000004},
108 {0x00080000, 0x00000016},
109 {0000000000, 0000000000},
110 {0x0400251d, 0x00000002},
111 {0x00007580, 0x00000002},
112 {0x00067581, 0x00000002},
113 {0x04002580, 0x00000002},
114 {0x00067581, 0x00000002},
115 {0x00000046, 0x00000004},
116 {0x00005000, 0000000000},
117 {0x00061000, 0x00000002},
118 {0x0000750e, 0x00000002},
119 {0x00019000, 0x00000002},
120 {0x00011055, 0x00000014},
121 {0x00000055, 0x00000012},
122 {0x0400250f, 0x00000002},
123 {0x0000504a, 0x00000004},
124 {0x00007565, 0x00000002},
125 {0x00007566, 0x00000002},
126 {0x00000051, 0x00000004},
127 {0x01e655b4, 0x00000002},
128 {0x4401b0dc, 0x00000002},
129 {0x01c110dc, 0x00000002},
130 {0x2666705d, 0x00000018},
131 {0x040c2565, 0x00000002},
132 {0x0000005d, 0x00000018},
133 {0x04002564, 0x00000002},
134 {0x00007566, 0x00000002},
135 {0x00000054, 0x00000004},
136 {0x00401060, 0x00000008},
137 {0x00101000, 0x00000002},
138 {0x000d80ff, 0x00000002},
139 {0x00800063, 0x00000008},
140 {0x000f9000, 0x00000002},
141 {0x000e00ff, 0x00000002},
142 {0000000000, 0x00000006},
143 {0x00000080, 0x00000018},
144 {0x00000054, 0x00000004},
145 {0x00007576, 0x00000002},
146 {0x00065000, 0x00000002},
147 {0x00009000, 0x00000002},
148 {0x00041000, 0x00000002},
149 {0x0c00350e, 0x00000002},
150 {0x00049000, 0x00000002},
151 {0x00051000, 0x00000002},
152 {0x01e785f8, 0x00000002},
153 {0x00200000, 0x00000002},
154 {0x00600073, 0x0000000c},
155 {0x00007563, 0x00000002},
156 {0x006075f0, 0x00000021},
157 {0x20007068, 0x00000004},
158 {0x00005068, 0x00000004},
159 {0x00007576, 0x00000002},
160 {0x00007577, 0x00000002},
161 {0x0000750e, 0x00000002},
162 {0x0000750f, 0x00000002},
163 {0x00a05000, 0x00000002},
164 {0x00600076, 0x0000000c},
165 {0x006075f0, 0x00000021},
166 {0x000075f8, 0x00000002},
167 {0x00000076, 0x00000004},
168 {0x000a750e, 0x00000002},
169 {0x0020750f, 0x00000002},
170 {0x00600079, 0x00000004},
171 {0x00007570, 0x00000002},
172 {0x00007571, 0x00000002},
173 {0x00007572, 0x00000006},
174 {0x00005000, 0x00000002},
175 {0x00a05000, 0x00000002},
176 {0x00007568, 0x00000002},
177 {0x00061000, 0x00000002},
178 {0x00000084, 0x0000000c},
179 {0x00058000, 0x00000002},
180 {0x0c607562, 0x00000002},
181 {0x00000086, 0x00000004},
182 {0x00600085, 0x00000004},
183 {0x400070dd, 0000000000},
184 {0x000380dd, 0x00000002},
185 {0x00000093, 0x0000001c},
186 {0x00065095, 0x00000018},
187 {0x040025bb, 0x00000002},
188 {0x00061096, 0x00000018},
189 {0x040075bc, 0000000000},
190 {0x000075bb, 0x00000002},
191 {0x000075bc, 0000000000},
192 {0x00090000, 0x00000006},
193 {0x00090000, 0x00000002},
194 {0x000d8002, 0x00000006},
195 {0x00005000, 0x00000002},
196 {0x00007821, 0x00000002},
197 {0x00007800, 0000000000},
198 {0x00007821, 0x00000002},
199 {0x00007800, 0000000000},
200 {0x01665000, 0x00000002},
201 {0x000a0000, 0x00000002},
202 {0x000671cc, 0x00000002},
203 {0x0286f1cd, 0x00000002},
204 {0x000000a3, 0x00000010},
205 {0x21007000, 0000000000},
206 {0x000000aa, 0x0000001c},
207 {0x00065000, 0x00000002},
208 {0x000a0000, 0x00000002},
209 {0x00061000, 0x00000002},
210 {0x000b0000, 0x00000002},
211 {0x38067000, 0x00000002},
212 {0x000a00a6, 0x00000004},
213 {0x20007000, 0000000000},
214 {0x01200000, 0x00000002},
215 {0x20077000, 0x00000002},
216 {0x01200000, 0x00000002},
217 {0x20007000, 0000000000},
218 {0x00061000, 0x00000002},
219 {0x0120751b, 0x00000002},
220 {0x8040750a, 0x00000002},
221 {0x8040750b, 0x00000002},
222 {0x00110000, 0x00000002},
223 {0x000380dd, 0x00000002},
224 {0x000000bd, 0x0000001c},
225 {0x00061096, 0x00000018},
226 {0x844075bd, 0x00000002},
227 {0x00061095, 0x00000018},
228 {0x840075bb, 0x00000002},
229 {0x00061096, 0x00000018},
230 {0x844075bc, 0x00000002},
231 {0x000000c0, 0x00000004},
232 {0x804075bd, 0x00000002},
233 {0x800075bb, 0x00000002},
234 {0x804075bc, 0x00000002},
235 {0x00108000, 0x00000002},
236 {0x01400000, 0x00000002},
237 {0x006000c4, 0x0000000c},
238 {0x20c07000, 0x00000020},
239 {0x000000c6, 0x00000012},
240 {0x00800000, 0x00000006},
241 {0x0080751d, 0x00000006},
242 {0x000025bb, 0x00000002},
243 {0x000040c0, 0x00000004},
244 {0x0000775c, 0x00000002},
245 {0x00a05000, 0x00000002},
246 {0x00661000, 0x00000002},
247 {0x0460275d, 0x00000020},
248 {0x00004000, 0000000000},
249 {0x00007999, 0x00000002},
250 {0x00a05000, 0x00000002},
251 {0x00661000, 0x00000002},
252 {0x0460299b, 0x00000020},
253 {0x00004000, 0000000000},
254 {0x01e00830, 0x00000002},
255 {0x21007000, 0000000000},
256 {0x00005000, 0x00000002},
257 {0x00038042, 0x00000002},
258 {0x040025e0, 0x00000002},
259 {0x000075e1, 0000000000},
260 {0x00000001, 0000000000},
261 {0x000380d9, 0x00000002},
262 {0x04007394, 0000000000},
263 {0000000000, 0000000000},
264 {0000000000, 0000000000},
265 {0000000000, 0000000000},
266 {0000000000, 0000000000},
267 {0000000000, 0000000000},
268 {0000000000, 0000000000},
269 {0000000000, 0000000000},
270 {0000000000, 0000000000},
271 {0000000000, 0000000000},
272 {0000000000, 0000000000},
273 {0000000000, 0000000000},
274 {0000000000, 0000000000},
275 {0000000000, 0000000000},
276 {0000000000, 0000000000},
277 {0000000000, 0000000000},
278 {0000000000, 0000000000},
279 {0000000000, 0000000000},
280 {0000000000, 0000000000},
281 {0000000000, 0000000000},
282 {0000000000, 0000000000},
283 {0000000000, 0000000000},
284 {0000000000, 0000000000},
285 {0000000000, 0000000000},
286 {0000000000, 0000000000},
287 {0000000000, 0000000000},
288 {0000000000, 0000000000},
289 {0000000000, 0000000000},
290 {0000000000, 0000000000},
291 {0000000000, 0000000000},
292 {0000000000, 0000000000},
293 {0000000000, 0000000000},
294 {0000000000, 0000000000},
295 {0000000000, 0000000000},
296 {0000000000, 0000000000},
297 {0000000000, 0000000000},
298 {0000000000, 0000000000},
299};
300
301static const u32 radeon_cp_microcode[][2] = {
302 {0x21007000, 0000000000},
303 {0x20007000, 0000000000},
304 {0x000000b4, 0x00000004},
305 {0x000000b8, 0x00000004},
306 {0x6f5b4d4c, 0000000000},
307 {0x4c4c427f, 0000000000},
308 {0x5b568a92, 0000000000},
309 {0x4ca09c6d, 0000000000},
310 {0xad4c4c4c, 0000000000},
311 {0x4ce1af3d, 0000000000},
312 {0xd8afafaf, 0000000000},
313 {0xd64c4cdc, 0000000000},
314 {0x4cd10d10, 0000000000},
315 {0x000f0000, 0x00000016},
316 {0x362f242d, 0000000000},
317 {0x00000012, 0x00000004},
318 {0x000f0000, 0x00000016},
319 {0x362f282d, 0000000000},
320 {0x000380e7, 0x00000002},
321 {0x04002c97, 0x00000002},
322 {0x000f0001, 0x00000016},
323 {0x333a3730, 0000000000},
324 {0x000077ef, 0x00000002},
325 {0x00061000, 0x00000002},
326 {0x00000021, 0x0000001a},
327 {0x00004000, 0x0000001e},
328 {0x00061000, 0x00000002},
329 {0x00000021, 0x0000001a},
330 {0x00004000, 0x0000001e},
331 {0x00061000, 0x00000002},
332 {0x00000021, 0x0000001a},
333 {0x00004000, 0x0000001e},
334 {0x00000017, 0x00000004},
335 {0x0003802b, 0x00000002},
336 {0x040067e0, 0x00000002},
337 {0x00000017, 0x00000004},
338 {0x000077e0, 0x00000002},
339 {0x00065000, 0x00000002},
340 {0x000037e1, 0x00000002},
341 {0x040067e1, 0x00000006},
342 {0x000077e0, 0x00000002},
343 {0x000077e1, 0x00000002},
344 {0x000077e1, 0x00000006},
345 {0xffffffff, 0000000000},
346 {0x10000000, 0000000000},
347 {0x0003802b, 0x00000002},
348 {0x040067e0, 0x00000006},
349 {0x00007675, 0x00000002},
350 {0x00007676, 0x00000002},
351 {0x00007677, 0x00000002},
352 {0x00007678, 0x00000006},
353 {0x0003802c, 0x00000002},
354 {0x04002676, 0x00000002},
355 {0x00007677, 0x00000002},
356 {0x00007678, 0x00000006},
357 {0x0000002f, 0x00000018},
358 {0x0000002f, 0x00000018},
359 {0000000000, 0x00000006},
360 {0x00000030, 0x00000018},
361 {0x00000030, 0x00000018},
362 {0000000000, 0x00000006},
363 {0x01605000, 0x00000002},
364 {0x00065000, 0x00000002},
365 {0x00098000, 0x00000002},
366 {0x00061000, 0x00000002},
367 {0x64c0603e, 0x00000004},
368 {0x000380e6, 0x00000002},
369 {0x040025c5, 0x00000002},
370 {0x00080000, 0x00000016},
371 {0000000000, 0000000000},
372 {0x0400251d, 0x00000002},
373 {0x00007580, 0x00000002},
374 {0x00067581, 0x00000002},
375 {0x04002580, 0x00000002},
376 {0x00067581, 0x00000002},
377 {0x00000049, 0x00000004},
378 {0x00005000, 0000000000},
379 {0x000380e6, 0x00000002},
380 {0x040025c5, 0x00000002},
381 {0x00061000, 0x00000002},
382 {0x0000750e, 0x00000002},
383 {0x00019000, 0x00000002},
384 {0x00011055, 0x00000014},
385 {0x00000055, 0x00000012},
386 {0x0400250f, 0x00000002},
387 {0x0000504f, 0x00000004},
388 {0x000380e6, 0x00000002},
389 {0x040025c5, 0x00000002},
390 {0x00007565, 0x00000002},
391 {0x00007566, 0x00000002},
392 {0x00000058, 0x00000004},
393 {0x000380e6, 0x00000002},
394 {0x040025c5, 0x00000002},
395 {0x01e655b4, 0x00000002},
396 {0x4401b0e4, 0x00000002},
397 {0x01c110e4, 0x00000002},
398 {0x26667066, 0x00000018},
399 {0x040c2565, 0x00000002},
400 {0x00000066, 0x00000018},
401 {0x04002564, 0x00000002},
402 {0x00007566, 0x00000002},
403 {0x0000005d, 0x00000004},
404 {0x00401069, 0x00000008},
405 {0x00101000, 0x00000002},
406 {0x000d80ff, 0x00000002},
407 {0x0080006c, 0x00000008},
408 {0x000f9000, 0x00000002},
409 {0x000e00ff, 0x00000002},
410 {0000000000, 0x00000006},
411 {0x0000008f, 0x00000018},
412 {0x0000005b, 0x00000004},
413 {0x000380e6, 0x00000002},
414 {0x040025c5, 0x00000002},
415 {0x00007576, 0x00000002},
416 {0x00065000, 0x00000002},
417 {0x00009000, 0x00000002},
418 {0x00041000, 0x00000002},
419 {0x0c00350e, 0x00000002},
420 {0x00049000, 0x00000002},
421 {0x00051000, 0x00000002},
422 {0x01e785f8, 0x00000002},
423 {0x00200000, 0x00000002},
424 {0x0060007e, 0x0000000c},
425 {0x00007563, 0x00000002},
426 {0x006075f0, 0x00000021},
427 {0x20007073, 0x00000004},
428 {0x00005073, 0x00000004},
429 {0x000380e6, 0x00000002},
430 {0x040025c5, 0x00000002},
431 {0x00007576, 0x00000002},
432 {0x00007577, 0x00000002},
433 {0x0000750e, 0x00000002},
434 {0x0000750f, 0x00000002},
435 {0x00a05000, 0x00000002},
436 {0x00600083, 0x0000000c},
437 {0x006075f0, 0x00000021},
438 {0x000075f8, 0x00000002},
439 {0x00000083, 0x00000004},
440 {0x000a750e, 0x00000002},
441 {0x000380e6, 0x00000002},
442 {0x040025c5, 0x00000002},
443 {0x0020750f, 0x00000002},
444 {0x00600086, 0x00000004},
445 {0x00007570, 0x00000002},
446 {0x00007571, 0x00000002},
447 {0x00007572, 0x00000006},
448 {0x000380e6, 0x00000002},
449 {0x040025c5, 0x00000002},
450 {0x00005000, 0x00000002},
451 {0x00a05000, 0x00000002},
452 {0x00007568, 0x00000002},
453 {0x00061000, 0x00000002},
454 {0x00000095, 0x0000000c},
455 {0x00058000, 0x00000002},
456 {0x0c607562, 0x00000002},
457 {0x00000097, 0x00000004},
458 {0x000380e6, 0x00000002},
459 {0x040025c5, 0x00000002},
460 {0x00600096, 0x00000004},
461 {0x400070e5, 0000000000},
462 {0x000380e6, 0x00000002},
463 {0x040025c5, 0x00000002},
464 {0x000380e5, 0x00000002},
465 {0x000000a8, 0x0000001c},
466 {0x000650aa, 0x00000018},
467 {0x040025bb, 0x00000002},
468 {0x000610ab, 0x00000018},
469 {0x040075bc, 0000000000},
470 {0x000075bb, 0x00000002},
471 {0x000075bc, 0000000000},
472 {0x00090000, 0x00000006},
473 {0x00090000, 0x00000002},
474 {0x000d8002, 0x00000006},
475 {0x00007832, 0x00000002},
476 {0x00005000, 0x00000002},
477 {0x000380e7, 0x00000002},
478 {0x04002c97, 0x00000002},
479 {0x00007820, 0x00000002},
480 {0x00007821, 0x00000002},
481 {0x00007800, 0000000000},
482 {0x01200000, 0x00000002},
483 {0x20077000, 0x00000002},
484 {0x01200000, 0x00000002},
485 {0x20007000, 0x00000002},
486 {0x00061000, 0x00000002},
487 {0x0120751b, 0x00000002},
488 {0x8040750a, 0x00000002},
489 {0x8040750b, 0x00000002},
490 {0x00110000, 0x00000002},
491 {0x000380e5, 0x00000002},
492 {0x000000c6, 0x0000001c},
493 {0x000610ab, 0x00000018},
494 {0x844075bd, 0x00000002},
495 {0x000610aa, 0x00000018},
496 {0x840075bb, 0x00000002},
497 {0x000610ab, 0x00000018},
498 {0x844075bc, 0x00000002},
499 {0x000000c9, 0x00000004},
500 {0x804075bd, 0x00000002},
501 {0x800075bb, 0x00000002},
502 {0x804075bc, 0x00000002},
503 {0x00108000, 0x00000002},
504 {0x01400000, 0x00000002},
505 {0x006000cd, 0x0000000c},
506 {0x20c07000, 0x00000020},
507 {0x000000cf, 0x00000012},
508 {0x00800000, 0x00000006},
509 {0x0080751d, 0x00000006},
510 {0000000000, 0000000000},
511 {0x0000775c, 0x00000002},
512 {0x00a05000, 0x00000002},
513 {0x00661000, 0x00000002},
514 {0x0460275d, 0x00000020},
515 {0x00004000, 0000000000},
516 {0x01e00830, 0x00000002},
517 {0x21007000, 0000000000},
518 {0x6464614d, 0000000000},
519 {0x69687420, 0000000000},
520 {0x00000073, 0000000000},
521 {0000000000, 0000000000},
522 {0x00005000, 0x00000002},
523 {0x000380d0, 0x00000002},
524 {0x040025e0, 0x00000002},
525 {0x000075e1, 0000000000},
526 {0x00000001, 0000000000},
527 {0x000380e0, 0x00000002},
528 {0x04002394, 0x00000002},
529 {0x00005000, 0000000000},
530 {0000000000, 0000000000},
531 {0000000000, 0000000000},
532 {0x00000008, 0000000000},
533 {0x00000004, 0000000000},
534 {0000000000, 0000000000},
535 {0000000000, 0000000000},
536 {0000000000, 0000000000},
537 {0000000000, 0000000000},
538 {0000000000, 0000000000},
539 {0000000000, 0000000000},
540 {0000000000, 0000000000},
541 {0000000000, 0000000000},
542 {0000000000, 0000000000},
543 {0000000000, 0000000000},
544 {0000000000, 0000000000},
545 {0000000000, 0000000000},
546 {0000000000, 0000000000},
547 {0000000000, 0000000000},
548 {0000000000, 0000000000},
549 {0000000000, 0000000000},
550 {0000000000, 0000000000},
551 {0000000000, 0000000000},
552 {0000000000, 0000000000},
553 {0000000000, 0000000000},
554 {0000000000, 0000000000},
555 {0000000000, 0000000000},
556 {0000000000, 0000000000},
557 {0000000000, 0000000000},
558};
559
560static const u32 R300_cp_microcode[][2] = {
561 {0x4200e000, 0000000000},
562 {0x4000e000, 0000000000},
563 {0x000000af, 0x00000008},
564 {0x000000b3, 0x00000008},
565 {0x6c5a504f, 0000000000},
566 {0x4f4f497a, 0000000000},
567 {0x5a578288, 0000000000},
568 {0x4f91906a, 0000000000},
569 {0x4f4f4f4f, 0000000000},
570 {0x4fe24f44, 0000000000},
571 {0x4f9c9c9c, 0000000000},
572 {0xdc4f4fde, 0000000000},
573 {0xa1cd4f4f, 0000000000},
574 {0xd29d9d9d, 0000000000},
575 {0x4f0f9fd7, 0000000000},
576 {0x000ca000, 0x00000004},
577 {0x000d0012, 0x00000038},
578 {0x0000e8b4, 0x00000004},
579 {0x000d0014, 0x00000038},
580 {0x0000e8b6, 0x00000004},
581 {0x000d0016, 0x00000038},
582 {0x0000e854, 0x00000004},
583 {0x000d0018, 0x00000038},
584 {0x0000e855, 0x00000004},
585 {0x000d001a, 0x00000038},
586 {0x0000e856, 0x00000004},
587 {0x000d001c, 0x00000038},
588 {0x0000e857, 0x00000004},
589 {0x000d001e, 0x00000038},
590 {0x0000e824, 0x00000004},
591 {0x000d0020, 0x00000038},
592 {0x0000e825, 0x00000004},
593 {0x000d0022, 0x00000038},
594 {0x0000e830, 0x00000004},
595 {0x000d0024, 0x00000038},
596 {0x0000f0c0, 0x00000004},
597 {0x000d0026, 0x00000038},
598 {0x0000f0c1, 0x00000004},
599 {0x000d0028, 0x00000038},
600 {0x0000f041, 0x00000004},
601 {0x000d002a, 0x00000038},
602 {0x0000f184, 0x00000004},
603 {0x000d002c, 0x00000038},
604 {0x0000f185, 0x00000004},
605 {0x000d002e, 0x00000038},
606 {0x0000f186, 0x00000004},
607 {0x000d0030, 0x00000038},
608 {0x0000f187, 0x00000004},
609 {0x000d0032, 0x00000038},
610 {0x0000f180, 0x00000004},
611 {0x000d0034, 0x00000038},
612 {0x0000f393, 0x00000004},
613 {0x000d0036, 0x00000038},
614 {0x0000f38a, 0x00000004},
615 {0x000d0038, 0x00000038},
616 {0x0000f38e, 0x00000004},
617 {0x0000e821, 0x00000004},
618 {0x0140a000, 0x00000004},
619 {0x00000043, 0x00000018},
620 {0x00cce800, 0x00000004},
621 {0x001b0001, 0x00000004},
622 {0x08004800, 0x00000004},
623 {0x001b0001, 0x00000004},
624 {0x08004800, 0x00000004},
625 {0x001b0001, 0x00000004},
626 {0x08004800, 0x00000004},
627 {0x0000003a, 0x00000008},
628 {0x0000a000, 0000000000},
629 {0x02c0a000, 0x00000004},
630 {0x000ca000, 0x00000004},
631 {0x00130000, 0x00000004},
632 {0x000c2000, 0x00000004},
633 {0xc980c045, 0x00000008},
634 {0x2000451d, 0x00000004},
635 {0x0000e580, 0x00000004},
636 {0x000ce581, 0x00000004},
637 {0x08004580, 0x00000004},
638 {0x000ce581, 0x00000004},
639 {0x0000004c, 0x00000008},
640 {0x0000a000, 0000000000},
641 {0x000c2000, 0x00000004},
642 {0x0000e50e, 0x00000004},
643 {0x00032000, 0x00000004},
644 {0x00022056, 0x00000028},
645 {0x00000056, 0x00000024},
646 {0x0800450f, 0x00000004},
647 {0x0000a050, 0x00000008},
648 {0x0000e565, 0x00000004},
649 {0x0000e566, 0x00000004},
650 {0x00000057, 0x00000008},
651 {0x03cca5b4, 0x00000004},
652 {0x05432000, 0x00000004},
653 {0x00022000, 0x00000004},
654 {0x4ccce063, 0x00000030},
655 {0x08274565, 0x00000004},
656 {0x00000063, 0x00000030},
657 {0x08004564, 0x00000004},
658 {0x0000e566, 0x00000004},
659 {0x0000005a, 0x00000008},
660 {0x00802066, 0x00000010},
661 {0x00202000, 0x00000004},
662 {0x001b00ff, 0x00000004},
663 {0x01000069, 0x00000010},
664 {0x001f2000, 0x00000004},
665 {0x001c00ff, 0x00000004},
666 {0000000000, 0x0000000c},
667 {0x00000085, 0x00000030},
668 {0x0000005a, 0x00000008},
669 {0x0000e576, 0x00000004},
670 {0x000ca000, 0x00000004},
671 {0x00012000, 0x00000004},
672 {0x00082000, 0x00000004},
673 {0x1800650e, 0x00000004},
674 {0x00092000, 0x00000004},
675 {0x000a2000, 0x00000004},
676 {0x000f0000, 0x00000004},
677 {0x00400000, 0x00000004},
678 {0x00000079, 0x00000018},
679 {0x0000e563, 0x00000004},
680 {0x00c0e5f9, 0x000000c2},
681 {0x0000006e, 0x00000008},
682 {0x0000a06e, 0x00000008},
683 {0x0000e576, 0x00000004},
684 {0x0000e577, 0x00000004},
685 {0x0000e50e, 0x00000004},
686 {0x0000e50f, 0x00000004},
687 {0x0140a000, 0x00000004},
688 {0x0000007c, 0x00000018},
689 {0x00c0e5f9, 0x000000c2},
690 {0x0000007c, 0x00000008},
691 {0x0014e50e, 0x00000004},
692 {0x0040e50f, 0x00000004},
693 {0x00c0007f, 0x00000008},
694 {0x0000e570, 0x00000004},
695 {0x0000e571, 0x00000004},
696 {0x0000e572, 0x0000000c},
697 {0x0000a000, 0x00000004},
698 {0x0140a000, 0x00000004},
699 {0x0000e568, 0x00000004},
700 {0x000c2000, 0x00000004},
701 {0x00000089, 0x00000018},
702 {0x000b0000, 0x00000004},
703 {0x18c0e562, 0x00000004},
704 {0x0000008b, 0x00000008},
705 {0x00c0008a, 0x00000008},
706 {0x000700e4, 0x00000004},
707 {0x00000097, 0x00000038},
708 {0x000ca099, 0x00000030},
709 {0x080045bb, 0x00000004},
710 {0x000c209a, 0x00000030},
711 {0x0800e5bc, 0000000000},
712 {0x0000e5bb, 0x00000004},
713 {0x0000e5bc, 0000000000},
714 {0x00120000, 0x0000000c},
715 {0x00120000, 0x00000004},
716 {0x001b0002, 0x0000000c},
717 {0x0000a000, 0x00000004},
718 {0x0000e821, 0x00000004},
719 {0x0000e800, 0000000000},
720 {0x0000e821, 0x00000004},
721 {0x0000e82e, 0000000000},
722 {0x02cca000, 0x00000004},
723 {0x00140000, 0x00000004},
724 {0x000ce1cc, 0x00000004},
725 {0x050de1cd, 0x00000004},
726 {0x000000a7, 0x00000020},
727 {0x4200e000, 0000000000},
728 {0x000000ae, 0x00000038},
729 {0x000ca000, 0x00000004},
730 {0x00140000, 0x00000004},
731 {0x000c2000, 0x00000004},
732 {0x00160000, 0x00000004},
733 {0x700ce000, 0x00000004},
734 {0x001400aa, 0x00000008},
735 {0x4000e000, 0000000000},
736 {0x02400000, 0x00000004},
737 {0x400ee000, 0x00000004},
738 {0x02400000, 0x00000004},
739 {0x4000e000, 0000000000},
740 {0x000c2000, 0x00000004},
741 {0x0240e51b, 0x00000004},
742 {0x0080e50a, 0x00000005},
743 {0x0080e50b, 0x00000005},
744 {0x00220000, 0x00000004},
745 {0x000700e4, 0x00000004},
746 {0x000000c1, 0x00000038},
747 {0x000c209a, 0x00000030},
748 {0x0880e5bd, 0x00000005},
749 {0x000c2099, 0x00000030},
750 {0x0800e5bb, 0x00000005},
751 {0x000c209a, 0x00000030},
752 {0x0880e5bc, 0x00000005},
753 {0x000000c4, 0x00000008},
754 {0x0080e5bd, 0x00000005},
755 {0x0000e5bb, 0x00000005},
756 {0x0080e5bc, 0x00000005},
757 {0x00210000, 0x00000004},
758 {0x02800000, 0x00000004},
759 {0x00c000c8, 0x00000018},
760 {0x4180e000, 0x00000040},
761 {0x000000ca, 0x00000024},
762 {0x01000000, 0x0000000c},
763 {0x0100e51d, 0x0000000c},
764 {0x000045bb, 0x00000004},
765 {0x000080c4, 0x00000008},
766 {0x0000f3ce, 0x00000004},
767 {0x0140a000, 0x00000004},
768 {0x00cc2000, 0x00000004},
769 {0x08c053cf, 0x00000040},
770 {0x00008000, 0000000000},
771 {0x0000f3d2, 0x00000004},
772 {0x0140a000, 0x00000004},
773 {0x00cc2000, 0x00000004},
774 {0x08c053d3, 0x00000040},
775 {0x00008000, 0000000000},
776 {0x0000f39d, 0x00000004},
777 {0x0140a000, 0x00000004},
778 {0x00cc2000, 0x00000004},
779 {0x08c0539e, 0x00000040},
780 {0x00008000, 0000000000},
781 {0x03c00830, 0x00000004},
782 {0x4200e000, 0000000000},
783 {0x0000a000, 0x00000004},
784 {0x200045e0, 0x00000004},
785 {0x0000e5e1, 0000000000},
786 {0x00000001, 0000000000},
787 {0x000700e1, 0x00000004},
788 {0x0800e394, 0000000000},
789 {0000000000, 0000000000},
790 {0000000000, 0000000000},
791 {0000000000, 0000000000},
792 {0000000000, 0000000000},
793 {0000000000, 0000000000},
794 {0000000000, 0000000000},
795 {0000000000, 0000000000},
796 {0000000000, 0000000000},
797 {0000000000, 0000000000},
798 {0000000000, 0000000000},
799 {0000000000, 0000000000},
800 {0000000000, 0000000000},
801 {0000000000, 0000000000},
802 {0000000000, 0000000000},
803 {0000000000, 0000000000},
804 {0000000000, 0000000000},
805 {0000000000, 0000000000},
806 {0000000000, 0000000000},
807 {0000000000, 0000000000},
808 {0000000000, 0000000000},
809 {0000000000, 0000000000},
810 {0000000000, 0000000000},
811 {0000000000, 0000000000},
812 {0000000000, 0000000000},
813 {0000000000, 0000000000},
814 {0000000000, 0000000000},
815 {0000000000, 0000000000},
816 {0000000000, 0000000000},
817};
818
819static u32 RADEON_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
820{ 45{
821 u32 ret; 46 u32 ret;
822 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff)); 47 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
@@ -825,21 +50,41 @@ static u32 RADEON_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
825 return ret; 50 return ret;
826} 51}
827 52
53static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
54{
55 u32 ret;
56 RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
57 ret = RADEON_READ(RS480_NB_MC_DATA);
58 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
59 return ret;
60}
61
828static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) 62static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
829{ 63{
64 u32 ret;
830 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK)); 65 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
831 return RADEON_READ(RS690_MC_DATA); 66 ret = RADEON_READ(RS690_MC_DATA);
67 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
68 return ret;
69}
70
71static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
72{
73 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
74 return RS690_READ_MCIND(dev_priv, addr);
75 else
76 return RS480_READ_MCIND(dev_priv, addr);
832} 77}
833 78
834u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv) 79u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
835{ 80{
836 81
837 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) 82 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
838 return RADEON_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION); 83 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
839 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) 84 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
840 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION); 85 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
841 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) 86 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
842 return RADEON_READ_MCIND(dev_priv, R520_MC_FB_LOCATION); 87 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
843 else 88 else
844 return RADEON_READ(RADEON_MC_FB_LOCATION); 89 return RADEON_READ(RADEON_MC_FB_LOCATION);
845} 90}
@@ -847,11 +92,11 @@ u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
847static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc) 92static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
848{ 93{
849 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) 94 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
850 RADEON_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc); 95 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
851 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) 96 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
852 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc); 97 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
853 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) 98 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
854 RADEON_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc); 99 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
855 else 100 else
856 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc); 101 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
857} 102}
@@ -859,15 +104,39 @@ static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
859static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc) 104static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
860{ 105{
861 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) 106 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
862 RADEON_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc); 107 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
863 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) 108 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
864 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc); 109 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
865 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) 110 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
866 RADEON_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc); 111 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
867 else 112 else
868 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc); 113 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
869} 114}
870 115
116static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
117{
118 u32 agp_base_hi = upper_32_bits(agp_base);
119 u32 agp_base_lo = agp_base & 0xffffffff;
120
121 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
122 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
123 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
124 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
125 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
126 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
127 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
128 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
129 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
130 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480) {
131 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
132 RADEON_WRITE(RS480_AGP_BASE_2, 0);
133 } else {
134 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
135 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
136 RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
137 }
138}
139
871static int RADEON_READ_PLL(struct drm_device * dev, int addr) 140static int RADEON_READ_PLL(struct drm_device * dev, int addr)
872{ 141{
873 drm_radeon_private_t *dev_priv = dev->dev_private; 142 drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -882,15 +151,6 @@ static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
882 return RADEON_READ(RADEON_PCIE_DATA); 151 return RADEON_READ(RADEON_PCIE_DATA);
883} 152}
884 153
885static u32 RADEON_READ_IGPGART(drm_radeon_private_t *dev_priv, int addr)
886{
887 u32 ret;
888 RADEON_WRITE(RADEON_IGPGART_INDEX, addr & 0x7f);
889 ret = RADEON_READ(RADEON_IGPGART_DATA);
890 RADEON_WRITE(RADEON_IGPGART_INDEX, 0x7f);
891 return ret;
892}
893
894#if RADEON_FIFO_DEBUG 154#if RADEON_FIFO_DEBUG
895static void radeon_status(drm_radeon_private_t * dev_priv) 155static void radeon_status(drm_radeon_private_t * dev_priv)
896{ 156{
@@ -925,16 +185,36 @@ static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
925 185
926 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 186 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
927 187
928 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT); 188 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
929 tmp |= RADEON_RB3D_DC_FLUSH_ALL; 189 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
930 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp); 190 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
191 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
931 192
932 for (i = 0; i < dev_priv->usec_timeout; i++) { 193 for (i = 0; i < dev_priv->usec_timeout; i++) {
933 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT) 194 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
934 & RADEON_RB3D_DC_BUSY)) { 195 & RADEON_RB3D_DC_BUSY)) {
935 return 0; 196 return 0;
197 }
198 DRM_UDELAY(1);
199 }
200 } else {
201 /* 3D */
202 tmp = RADEON_READ(R300_RB3D_DSTCACHE_CTLSTAT);
203 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
204 RADEON_WRITE(R300_RB3D_DSTCACHE_CTLSTAT, tmp);
205
206 /* 2D */
207 tmp = RADEON_READ(R300_DSTCACHE_CTLSTAT);
208 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
209 RADEON_WRITE(R300_DSTCACHE_CTLSTAT, tmp);
210
211 for (i = 0; i < dev_priv->usec_timeout; i++) {
212 if (!(RADEON_READ(R300_DSTCACHE_CTLSTAT)
213 & RADEON_RB3D_DC_BUSY)) {
214 return 0;
215 }
216 DRM_UDELAY(1);
936 } 217 }
937 DRM_UDELAY(1);
938 } 218 }
939 219
940#if RADEON_FIFO_DEBUG 220#if RADEON_FIFO_DEBUG
@@ -991,6 +271,50 @@ static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
991 return -EBUSY; 271 return -EBUSY;
992} 272}
993 273
274static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
275{
276 uint32_t gb_tile_config, gb_pipe_sel = 0;
277
278 /* RS4xx/RS6xx/R4xx/R5xx */
279 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
280 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
281 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
282 } else {
283 /* R3xx */
284 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
285 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
286 dev_priv->num_gb_pipes = 2;
287 } else {
288 /* R3Vxx */
289 dev_priv->num_gb_pipes = 1;
290 }
291 }
292 DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
293
294 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
295
296 switch (dev_priv->num_gb_pipes) {
297 case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
298 case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
299 case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
300 default:
301 case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
302 }
303
304 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
305 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
306 RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
307 }
308 RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
309 radeon_do_wait_for_idle(dev_priv);
310 RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
311 RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
312 R300_DC_AUTOFLUSH_ENABLE |
313 R300_DC_DC_DISABLE_IGNORE_PE));
314
315
316}
317
994/* ================================================================ 318/* ================================================================
995 * CP control, initialization 319 * CP control, initialization
996 */ 320 */
@@ -1004,8 +328,22 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
1004 radeon_do_wait_for_idle(dev_priv); 328 radeon_do_wait_for_idle(dev_priv);
1005 329
1006 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0); 330 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
1007 331 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
1008 if (dev_priv->microcode_version == UCODE_R200) { 332 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
333 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
334 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
335 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
336 DRM_INFO("Loading R100 Microcode\n");
337 for (i = 0; i < 256; i++) {
338 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
339 R100_cp_microcode[i][1]);
340 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
341 R100_cp_microcode[i][0]);
342 }
343 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
344 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
345 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
346 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
1009 DRM_INFO("Loading R200 Microcode\n"); 347 DRM_INFO("Loading R200 Microcode\n");
1010 for (i = 0; i < 256; i++) { 348 for (i = 0; i < 256; i++) {
1011 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, 349 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
@@ -1013,7 +351,11 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
1013 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, 351 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
1014 R200_cp_microcode[i][0]); 352 R200_cp_microcode[i][0]);
1015 } 353 }
1016 } else if (dev_priv->microcode_version == UCODE_R300) { 354 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
355 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
356 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
357 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
358 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
1017 DRM_INFO("Loading R300 Microcode\n"); 359 DRM_INFO("Loading R300 Microcode\n");
1018 for (i = 0; i < 256; i++) { 360 for (i = 0; i < 256; i++) {
1019 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, 361 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
@@ -1021,12 +363,35 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
1021 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, 363 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
1022 R300_cp_microcode[i][0]); 364 R300_cp_microcode[i][0]);
1023 } 365 }
1024 } else { 366 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
367 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
368 DRM_INFO("Loading R400 Microcode\n");
1025 for (i = 0; i < 256; i++) { 369 for (i = 0; i < 256; i++) {
1026 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, 370 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
1027 radeon_cp_microcode[i][1]); 371 R420_cp_microcode[i][1]);
1028 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, 372 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
1029 radeon_cp_microcode[i][0]); 373 R420_cp_microcode[i][0]);
374 }
375 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
376 DRM_INFO("Loading RS690 Microcode\n");
377 for (i = 0; i < 256; i++) {
378 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
379 RS690_cp_microcode[i][1]);
380 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
381 RS690_cp_microcode[i][0]);
382 }
383 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
384 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
385 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
386 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
387 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
388 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
389 DRM_INFO("Loading R500 Microcode\n");
390 for (i = 0; i < 256; i++) {
391 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
392 R520_cp_microcode[i][1]);
393 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
394 R520_cp_microcode[i][0]);
1030 } 395 }
1031 } 396 }
1032} 397}
@@ -1121,12 +486,13 @@ static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
1121static int radeon_do_engine_reset(struct drm_device * dev) 486static int radeon_do_engine_reset(struct drm_device * dev)
1122{ 487{
1123 drm_radeon_private_t *dev_priv = dev->dev_private; 488 drm_radeon_private_t *dev_priv = dev->dev_private;
1124 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset; 489 u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
1125 DRM_DEBUG("\n"); 490 DRM_DEBUG("\n");
1126 491
1127 radeon_do_pixcache_flush(dev_priv); 492 radeon_do_pixcache_flush(dev_priv);
1128 493
1129 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) { 494 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
495 /* may need something similar for newer chips */
1130 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX); 496 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
1131 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL); 497 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
1132 498
@@ -1137,33 +503,39 @@ static int radeon_do_engine_reset(struct drm_device * dev)
1137 RADEON_FORCEON_YCLKB | 503 RADEON_FORCEON_YCLKB |
1138 RADEON_FORCEON_MC | 504 RADEON_FORCEON_MC |
1139 RADEON_FORCEON_AIC)); 505 RADEON_FORCEON_AIC));
506 }
1140 507
1141 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET); 508 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
1142 509
1143 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | 510 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
1144 RADEON_SOFT_RESET_CP | 511 RADEON_SOFT_RESET_CP |
1145 RADEON_SOFT_RESET_HI | 512 RADEON_SOFT_RESET_HI |
1146 RADEON_SOFT_RESET_SE | 513 RADEON_SOFT_RESET_SE |
1147 RADEON_SOFT_RESET_RE | 514 RADEON_SOFT_RESET_RE |
1148 RADEON_SOFT_RESET_PP | 515 RADEON_SOFT_RESET_PP |
1149 RADEON_SOFT_RESET_E2 | 516 RADEON_SOFT_RESET_E2 |
1150 RADEON_SOFT_RESET_RB)); 517 RADEON_SOFT_RESET_RB));
1151 RADEON_READ(RADEON_RBBM_SOFT_RESET); 518 RADEON_READ(RADEON_RBBM_SOFT_RESET);
1152 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & 519 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
1153 ~(RADEON_SOFT_RESET_CP | 520 ~(RADEON_SOFT_RESET_CP |
1154 RADEON_SOFT_RESET_HI | 521 RADEON_SOFT_RESET_HI |
1155 RADEON_SOFT_RESET_SE | 522 RADEON_SOFT_RESET_SE |
1156 RADEON_SOFT_RESET_RE | 523 RADEON_SOFT_RESET_RE |
1157 RADEON_SOFT_RESET_PP | 524 RADEON_SOFT_RESET_PP |
1158 RADEON_SOFT_RESET_E2 | 525 RADEON_SOFT_RESET_E2 |
1159 RADEON_SOFT_RESET_RB))); 526 RADEON_SOFT_RESET_RB)));
1160 RADEON_READ(RADEON_RBBM_SOFT_RESET); 527 RADEON_READ(RADEON_RBBM_SOFT_RESET);
1161 528
529 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
1162 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl); 530 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
1163 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); 531 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
1164 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); 532 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
1165 } 533 }
1166 534
535 /* setup the raster pipes */
536 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
537 radeon_init_pipes(dev_priv);
538
1167 /* Reset the CP ring */ 539 /* Reset the CP ring */
1168 radeon_do_cp_reset(dev_priv); 540 radeon_do_cp_reset(dev_priv);
1169 541
@@ -1194,7 +566,8 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
1194 566
1195#if __OS_HAS_AGP 567#if __OS_HAS_AGP
1196 if (dev_priv->flags & RADEON_IS_AGP) { 568 if (dev_priv->flags & RADEON_IS_AGP) {
1197 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base); 569 radeon_write_agp_base(dev_priv, dev->agp->base);
570
1198 radeon_write_agp_location(dev_priv, 571 radeon_write_agp_location(dev_priv,
1199 (((dev_priv->gart_vm_start - 1 + 572 (((dev_priv->gart_vm_start - 1 +
1200 dev_priv->gart_size) & 0xffff0000) | 573 dev_priv->gart_size) & 0xffff0000) |
@@ -1339,102 +712,70 @@ static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
1339/* Enable or disable IGP GART on the chip */ 712/* Enable or disable IGP GART on the chip */
1340static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on) 713static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
1341{ 714{
1342 u32 temp, tmp;
1343
1344 tmp = RADEON_READ(RADEON_AIC_CNTL);
1345 if (on) {
1346 DRM_DEBUG("programming igpgart %08X %08lX %08X\n",
1347 dev_priv->gart_vm_start,
1348 (long)dev_priv->gart_info.bus_addr,
1349 dev_priv->gart_size);
1350
1351 RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_18, 0x1000);
1352 RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, 0x1);
1353 RADEON_WRITE_IGPGART(RADEON_IGPGART_CTRL, 0x42040800);
1354 RADEON_WRITE_IGPGART(RADEON_IGPGART_BASE_ADDR,
1355 dev_priv->gart_info.bus_addr);
1356
1357 temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_39);
1358 RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_39, temp);
1359
1360 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start);
1361 dev_priv->gart_size = 32*1024*1024;
1362 radeon_write_agp_location(dev_priv,
1363 (((dev_priv->gart_vm_start - 1 +
1364 dev_priv->gart_size) & 0xffff0000) |
1365 (dev_priv->gart_vm_start >> 16)));
1366
1367 temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_ENABLE);
1368 RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, temp);
1369
1370 RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
1371 RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x1);
1372 RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
1373 RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x0);
1374 }
1375}
1376
1377/* Enable or disable RS690 GART on the chip */
1378static void radeon_set_rs690gart(drm_radeon_private_t *dev_priv, int on)
1379{
1380 u32 temp; 715 u32 temp;
1381 716
1382 if (on) { 717 if (on) {
1383 DRM_DEBUG("programming rs690 gart %08X %08lX %08X\n", 718 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
1384 dev_priv->gart_vm_start, 719 dev_priv->gart_vm_start,
1385 (long)dev_priv->gart_info.bus_addr, 720 (long)dev_priv->gart_info.bus_addr,
1386 dev_priv->gart_size); 721 dev_priv->gart_size);
1387 722
1388 temp = RS690_READ_MCIND(dev_priv, RS690_MC_MISC_CNTL); 723 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
1389 RS690_WRITE_MCIND(RS690_MC_MISC_CNTL, 0x5000); 724 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
725 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
726 RS690_BLOCK_GFX_D3_EN));
727 else
728 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
1390 729
1391 RS690_WRITE_MCIND(RS690_MC_AGP_SIZE, 730 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
1392 RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB); 731 RS480_VA_SIZE_32MB));
1393 732
1394 temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_FEATURE_ID); 733 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
1395 RS690_WRITE_MCIND(RS690_MC_GART_FEATURE_ID, 0x42040800); 734 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
735 RS480_TLB_ENABLE |
736 RS480_GTW_LAC_EN |
737 RS480_1LEVEL_GART));
1396 738
1397 RS690_WRITE_MCIND(RS690_MC_GART_BASE, 739 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
1398 dev_priv->gart_info.bus_addr); 740 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
741 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
1399 742
1400 temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_MODE_CONTROL); 743 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
1401 RS690_WRITE_MCIND(RS690_MC_AGP_MODE_CONTROL, 0x01400000); 744 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
745 RS480_REQ_TYPE_SNOOP_DIS));
1402 746
1403 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, 747 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
1404 (unsigned int)dev_priv->gart_vm_start);
1405 748
1406 dev_priv->gart_size = 32*1024*1024; 749 dev_priv->gart_size = 32*1024*1024;
1407 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) & 750 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
1408 0xffff0000) | (dev_priv->gart_vm_start >> 16)); 751 0xffff0000) | (dev_priv->gart_vm_start >> 16));
1409 752
1410 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, temp); 753 radeon_write_agp_location(dev_priv, temp);
1411 754
1412 temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_SIZE); 755 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
1413 RS690_WRITE_MCIND(RS690_MC_AGP_SIZE, 756 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
1414 RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB); 757 RS480_VA_SIZE_32MB));
1415 758
1416 do { 759 do {
1417 temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_CACHE_CNTL); 760 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
1418 if ((temp & RS690_MC_GART_CLEAR_STATUS) == 761 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
1419 RS690_MC_GART_CLEAR_DONE)
1420 break; 762 break;
1421 DRM_UDELAY(1); 763 DRM_UDELAY(1);
1422 } while (1); 764 } while (1);
1423 765
1424 RS690_WRITE_MCIND(RS690_MC_GART_CACHE_CNTL, 766 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
1425 RS690_MC_GART_CC_CLEAR); 767 RS480_GART_CACHE_INVALIDATE);
768
1426 do { 769 do {
1427 temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_CACHE_CNTL); 770 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
1428 if ((temp & RS690_MC_GART_CLEAR_STATUS) == 771 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
1429 RS690_MC_GART_CLEAR_DONE)
1430 break; 772 break;
1431 DRM_UDELAY(1); 773 DRM_UDELAY(1);
1432 } while (1); 774 } while (1);
1433 775
1434 RS690_WRITE_MCIND(RS690_MC_GART_CACHE_CNTL, 776 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
1435 RS690_MC_GART_CC_NO_CHANGE);
1436 } else { 777 } else {
1437 RS690_WRITE_MCIND(RS690_MC_AGP_SIZE, RS690_MC_GART_DIS); 778 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
1438 } 779 }
1439} 780}
1440 781
@@ -1472,12 +813,8 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1472{ 813{
1473 u32 tmp; 814 u32 tmp;
1474 815
1475 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) { 816 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
1476 radeon_set_rs690gart(dev_priv, on); 817 (dev_priv->flags & RADEON_IS_IGPGART)) {
1477 return;
1478 }
1479
1480 if (dev_priv->flags & RADEON_IS_IGPGART) {
1481 radeon_set_igpgart(dev_priv, on); 818 radeon_set_igpgart(dev_priv, on);
1482 return; 819 return;
1483 } 820 }
@@ -1951,6 +1288,7 @@ static int radeon_do_resume_cp(struct drm_device * dev)
1951 radeon_cp_init_ring_buffer(dev, dev_priv); 1288 radeon_cp_init_ring_buffer(dev, dev_priv);
1952 1289
1953 radeon_do_engine_reset(dev); 1290 radeon_do_engine_reset(dev);
1291 radeon_enable_interrupt(dev);
1954 1292
1955 DRM_DEBUG("radeon_do_resume_cp() complete\n"); 1293 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1956 1294
diff --git a/drivers/char/drm/radeon_drm.h b/drivers/char/drm/radeon_drm.h
index aab82e121e0..73ff51f1231 100644
--- a/drivers/char/drm/radeon_drm.h
+++ b/drivers/char/drm/radeon_drm.h
@@ -240,6 +240,7 @@ typedef union {
240# define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8 240# define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8
241 241
242#define R300_CMD_SCRATCH 8 242#define R300_CMD_SCRATCH 8
243#define R300_CMD_R500FP 9
243 244
244typedef union { 245typedef union {
245 unsigned int u; 246 unsigned int u;
@@ -268,6 +269,9 @@ typedef union {
268 struct { 269 struct {
269 unsigned char cmd_type, reg, n_bufs, flags; 270 unsigned char cmd_type, reg, n_bufs, flags;
270 } scratch; 271 } scratch;
272 struct {
273 unsigned char cmd_type, count, adrlo, adrhi_flags;
274 } r500fp;
271} drm_r300_cmd_header_t; 275} drm_r300_cmd_header_t;
272 276
273#define RADEON_FRONT 0x1 277#define RADEON_FRONT 0x1
@@ -278,6 +282,9 @@ typedef union {
278#define RADEON_USE_HIERZ 0x40000000 282#define RADEON_USE_HIERZ 0x40000000
279#define RADEON_USE_COMP_ZBUF 0x20000000 283#define RADEON_USE_COMP_ZBUF 0x20000000
280 284
285#define R500FP_CONSTANT_TYPE (1 << 1)
286#define R500FP_CONSTANT_CLAMP (1 << 2)
287
281/* Primitive types 288/* Primitive types
282 */ 289 */
283#define RADEON_POINTS 0x1 290#define RADEON_POINTS 0x1
@@ -669,6 +676,7 @@ typedef struct drm_radeon_indirect {
669#define RADEON_PARAM_CARD_TYPE 12 676#define RADEON_PARAM_CARD_TYPE 12
670#define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */ 677#define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */
671#define RADEON_PARAM_FB_LOCATION 14 /* FB location */ 678#define RADEON_PARAM_FB_LOCATION 14 /* FB location */
679#define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */
672 680
673typedef struct drm_radeon_getparam { 681typedef struct drm_radeon_getparam {
674 int param; 682 int param;
diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h
index 173ae620223..3f0eca957aa 100644
--- a/drivers/char/drm/radeon_drv.h
+++ b/drivers/char/drm/radeon_drv.h
@@ -38,7 +38,7 @@
38 38
39#define DRIVER_NAME "radeon" 39#define DRIVER_NAME "radeon"
40#define DRIVER_DESC "ATI Radeon" 40#define DRIVER_DESC "ATI Radeon"
41#define DRIVER_DATE "20060524" 41#define DRIVER_DATE "20080528"
42 42
43/* Interface history: 43/* Interface history:
44 * 44 *
@@ -98,9 +98,10 @@
98 * 1.26- Add support for variable size PCI(E) gart aperture 98 * 1.26- Add support for variable size PCI(E) gart aperture
99 * 1.27- Add support for IGP GART 99 * 1.27- Add support for IGP GART
100 * 1.28- Add support for VBL on CRTC2 100 * 1.28- Add support for VBL on CRTC2
101 * 1.29- R500 3D cmd buffer support
101 */ 102 */
102#define DRIVER_MAJOR 1 103#define DRIVER_MAJOR 1
103#define DRIVER_MINOR 28 104#define DRIVER_MINOR 29
104#define DRIVER_PATCHLEVEL 0 105#define DRIVER_PATCHLEVEL 0
105 106
106/* 107/*
@@ -122,7 +123,7 @@ enum radeon_family {
122 CHIP_RV380, 123 CHIP_RV380,
123 CHIP_R420, 124 CHIP_R420,
124 CHIP_RV410, 125 CHIP_RV410,
125 CHIP_RS400, 126 CHIP_RS480,
126 CHIP_RS690, 127 CHIP_RS690,
127 CHIP_RV515, 128 CHIP_RV515,
128 CHIP_R520, 129 CHIP_R520,
@@ -294,6 +295,7 @@ typedef struct drm_radeon_private {
294 int vblank_crtc; 295 int vblank_crtc;
295 uint32_t irq_enable_reg; 296 uint32_t irq_enable_reg;
296 int irq_enabled; 297 int irq_enabled;
298 uint32_t r500_disp_irq_reg;
297 299
298 struct radeon_surface surfaces[RADEON_MAX_SURFACES]; 300 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
299 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES]; 301 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
@@ -307,6 +309,8 @@ typedef struct drm_radeon_private {
307 /* starting from here on, data is preserved accross an open */ 309 /* starting from here on, data is preserved accross an open */
308 uint32_t flags; /* see radeon_chip_flags */ 310 uint32_t flags; /* see radeon_chip_flags */
309 unsigned long fb_aper_offset; 311 unsigned long fb_aper_offset;
312
313 int num_gb_pipes;
310} drm_radeon_private_t; 314} drm_radeon_private_t;
311 315
312typedef struct drm_radeon_buf_priv { 316typedef struct drm_radeon_buf_priv {
@@ -382,6 +386,7 @@ extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
382extern void radeon_driver_irq_preinstall(struct drm_device * dev); 386extern void radeon_driver_irq_preinstall(struct drm_device * dev);
383extern void radeon_driver_irq_postinstall(struct drm_device * dev); 387extern void radeon_driver_irq_postinstall(struct drm_device * dev);
384extern void radeon_driver_irq_uninstall(struct drm_device * dev); 388extern void radeon_driver_irq_uninstall(struct drm_device * dev);
389extern void radeon_enable_interrupt(struct drm_device *dev);
385extern int radeon_vblank_crtc_get(struct drm_device *dev); 390extern int radeon_vblank_crtc_get(struct drm_device *dev);
386extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value); 391extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
387 392
@@ -444,13 +449,13 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
444#define RADEON_PCIE_DATA 0x0034 449#define RADEON_PCIE_DATA 0x0034
445#define RADEON_PCIE_TX_GART_CNTL 0x10 450#define RADEON_PCIE_TX_GART_CNTL 0x10
446# define RADEON_PCIE_TX_GART_EN (1 << 0) 451# define RADEON_PCIE_TX_GART_EN (1 << 0)
447# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1) 452# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1)
448# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1) 453# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1)
449# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1) 454# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1)
450# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0<<3) 455# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3)
451# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1<<3) 456# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3)
452# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1<<5) 457# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5)
453# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1<<8) 458# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8)
454#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11 459#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
455#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12 460#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
456#define RADEON_PCIE_TX_GART_BASE 0x13 461#define RADEON_PCIE_TX_GART_BASE 0x13
@@ -459,14 +464,9 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
459#define RADEON_PCIE_TX_GART_END_LO 0x16 464#define RADEON_PCIE_TX_GART_END_LO 0x16
460#define RADEON_PCIE_TX_GART_END_HI 0x17 465#define RADEON_PCIE_TX_GART_END_HI 0x17
461 466
462#define RADEON_IGPGART_INDEX 0x168 467#define RS480_NB_MC_INDEX 0x168
463#define RADEON_IGPGART_DATA 0x16c 468# define RS480_NB_MC_IND_WR_EN (1 << 8)
464#define RADEON_IGPGART_UNK_18 0x18 469#define RS480_NB_MC_DATA 0x16c
465#define RADEON_IGPGART_CTRL 0x2b
466#define RADEON_IGPGART_BASE_ADDR 0x2c
467#define RADEON_IGPGART_FLUSH 0x2e
468#define RADEON_IGPGART_ENABLE 0x38
469#define RADEON_IGPGART_UNK_39 0x39
470 470
471#define RS690_MC_INDEX 0x78 471#define RS690_MC_INDEX 0x78
472# define RS690_MC_INDEX_MASK 0x1ff 472# define RS690_MC_INDEX_MASK 0x1ff
@@ -474,45 +474,91 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
474# define RS690_MC_INDEX_WR_ACK 0x7f 474# define RS690_MC_INDEX_WR_ACK 0x7f
475#define RS690_MC_DATA 0x7c 475#define RS690_MC_DATA 0x7c
476 476
477#define RS690_MC_MISC_CNTL 0x18 477/* MC indirect registers */
478#define RS690_MC_GART_FEATURE_ID 0x2b 478#define RS480_MC_MISC_CNTL 0x18
479#define RS690_MC_GART_BASE 0x2c 479# define RS480_DISABLE_GTW (1 << 1)
480#define RS690_MC_GART_CACHE_CNTL 0x2e 480/* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */
481# define RS690_MC_GART_CC_NO_CHANGE 0x0 481# define RS480_GART_INDEX_REG_EN (1 << 12)
482# define RS690_MC_GART_CC_CLEAR 0x1 482# define RS690_BLOCK_GFX_D3_EN (1 << 14)
483# define RS690_MC_GART_CLEAR_STATUS (1 << 1) 483#define RS480_K8_FB_LOCATION 0x1e
484# define RS690_MC_GART_CLEAR_DONE (0 << 1) 484#define RS480_GART_FEATURE_ID 0x2b
485# define RS690_MC_GART_CLEAR_PENDING (1 << 1) 485# define RS480_HANG_EN (1 << 11)
486#define RS690_MC_AGP_SIZE 0x38 486# define RS480_TLB_ENABLE (1 << 18)
487# define RS690_MC_GART_DIS 0x0 487# define RS480_P2P_ENABLE (1 << 19)
488# define RS690_MC_GART_EN 0x1 488# define RS480_GTW_LAC_EN (1 << 25)
489# define RS690_MC_AGP_SIZE_32MB (0 << 1) 489# define RS480_2LEVEL_GART (0 << 30)
490# define RS690_MC_AGP_SIZE_64MB (1 << 1) 490# define RS480_1LEVEL_GART (1 << 30)
491# define RS690_MC_AGP_SIZE_128MB (2 << 1) 491# define RS480_PDC_EN (1 << 31)
492# define RS690_MC_AGP_SIZE_256MB (3 << 1) 492#define RS480_GART_BASE 0x2c
493# define RS690_MC_AGP_SIZE_512MB (4 << 1) 493#define RS480_GART_CACHE_CNTRL 0x2e
494# define RS690_MC_AGP_SIZE_1GB (5 << 1) 494# define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */
495# define RS690_MC_AGP_SIZE_2GB (6 << 1) 495#define RS480_AGP_ADDRESS_SPACE_SIZE 0x38
496#define RS690_MC_AGP_MODE_CONTROL 0x39 496# define RS480_GART_EN (1 << 0)
497# define RS480_VA_SIZE_32MB (0 << 1)
498# define RS480_VA_SIZE_64MB (1 << 1)
499# define RS480_VA_SIZE_128MB (2 << 1)
500# define RS480_VA_SIZE_256MB (3 << 1)
501# define RS480_VA_SIZE_512MB (4 << 1)
502# define RS480_VA_SIZE_1GB (5 << 1)
503# define RS480_VA_SIZE_2GB (6 << 1)
504#define RS480_AGP_MODE_CNTL 0x39
505# define RS480_POST_GART_Q_SIZE (1 << 18)
506# define RS480_NONGART_SNOOP (1 << 19)
507# define RS480_AGP_RD_BUF_SIZE (1 << 20)
508# define RS480_REQ_TYPE_SNOOP_SHIFT 22
509# define RS480_REQ_TYPE_SNOOP_MASK 0x3
510# define RS480_REQ_TYPE_SNOOP_DIS (1 << 24)
511#define RS480_MC_MISC_UMA_CNTL 0x5f
512#define RS480_MC_MCLK_CNTL 0x7a
513#define RS480_MC_UMA_DUALCH_CNTL 0x86
514
497#define RS690_MC_FB_LOCATION 0x100 515#define RS690_MC_FB_LOCATION 0x100
498#define RS690_MC_AGP_LOCATION 0x101 516#define RS690_MC_AGP_LOCATION 0x101
499#define RS690_MC_AGP_BASE 0x102 517#define RS690_MC_AGP_BASE 0x102
518#define RS690_MC_AGP_BASE_2 0x103
500 519
501#define R520_MC_IND_INDEX 0x70 520#define R520_MC_IND_INDEX 0x70
502#define R520_MC_IND_WR_EN (1<<24) 521#define R520_MC_IND_WR_EN (1 << 24)
503#define R520_MC_IND_DATA 0x74 522#define R520_MC_IND_DATA 0x74
504 523
505#define RV515_MC_FB_LOCATION 0x01 524#define RV515_MC_FB_LOCATION 0x01
506#define RV515_MC_AGP_LOCATION 0x02 525#define RV515_MC_AGP_LOCATION 0x02
526#define RV515_MC_AGP_BASE 0x03
527#define RV515_MC_AGP_BASE_2 0x04
507 528
508#define R520_MC_FB_LOCATION 0x04 529#define R520_MC_FB_LOCATION 0x04
509#define R520_MC_AGP_LOCATION 0x05 530#define R520_MC_AGP_LOCATION 0x05
531#define R520_MC_AGP_BASE 0x06
532#define R520_MC_AGP_BASE_2 0x07
510 533
511#define RADEON_MPP_TB_CONFIG 0x01c0 534#define RADEON_MPP_TB_CONFIG 0x01c0
512#define RADEON_MEM_CNTL 0x0140 535#define RADEON_MEM_CNTL 0x0140
513#define RADEON_MEM_SDRAM_MODE_REG 0x0158 536#define RADEON_MEM_SDRAM_MODE_REG 0x0158
537#define RADEON_AGP_BASE_2 0x015c /* r200+ only */
538#define RS480_AGP_BASE_2 0x0164
514#define RADEON_AGP_BASE 0x0170 539#define RADEON_AGP_BASE 0x0170
515 540
541/* pipe config regs */
542#define R400_GB_PIPE_SELECT 0x402c
543#define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */
544#define R500_SU_REG_DEST 0x42c8
545#define R300_GB_TILE_CONFIG 0x4018
546# define R300_ENABLE_TILING (1 << 0)
547# define R300_PIPE_COUNT_RV350 (0 << 1)
548# define R300_PIPE_COUNT_R300 (3 << 1)
549# define R300_PIPE_COUNT_R420_3P (6 << 1)
550# define R300_PIPE_COUNT_R420 (7 << 1)
551# define R300_TILE_SIZE_8 (0 << 4)
552# define R300_TILE_SIZE_16 (1 << 4)
553# define R300_TILE_SIZE_32 (2 << 4)
554# define R300_SUBPIXEL_1_12 (0 << 16)
555# define R300_SUBPIXEL_1_16 (1 << 16)
556#define R300_DST_PIPE_CONFIG 0x170c
557# define R300_PIPE_AUTO_CONFIG (1 << 31)
558#define R300_RB2D_DSTCACHE_MODE 0x3428
559# define R300_DC_AUTOFLUSH_ENABLE (1 << 8)
560# define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)
561
516#define RADEON_RB3D_COLOROFFSET 0x1c40 562#define RADEON_RB3D_COLOROFFSET 0x1c40
517#define RADEON_RB3D_COLORPITCH 0x1c48 563#define RADEON_RB3D_COLORPITCH 0x1c48
518 564
@@ -616,11 +662,12 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
616#define RADEON_PP_TXFILTER_1 0x1c6c 662#define RADEON_PP_TXFILTER_1 0x1c6c
617#define RADEON_PP_TXFILTER_2 0x1c84 663#define RADEON_PP_TXFILTER_2 0x1c84
618 664
619#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c 665#define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */
620# define RADEON_RB2D_DC_FLUSH (3 << 0) 666#define R300_DSTCACHE_CTLSTAT 0x1714
621# define RADEON_RB2D_DC_FREE (3 << 2) 667# define R300_RB2D_DC_FLUSH (3 << 0)
622# define RADEON_RB2D_DC_FLUSH_ALL 0xf 668# define R300_RB2D_DC_FREE (3 << 2)
623# define RADEON_RB2D_DC_BUSY (1 << 31) 669# define R300_RB2D_DC_FLUSH_ALL 0xf
670# define R300_RB2D_DC_BUSY (1 << 31)
624#define RADEON_RB3D_CNTL 0x1c3c 671#define RADEON_RB3D_CNTL 0x1c3c
625# define RADEON_ALPHA_BLEND_ENABLE (1 << 0) 672# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
626# define RADEON_PLANE_MASK_ENABLE (1 << 1) 673# define RADEON_PLANE_MASK_ENABLE (1 << 1)
@@ -643,11 +690,18 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
643# define RADEON_RB3D_ZC_FREE (1 << 2) 690# define RADEON_RB3D_ZC_FREE (1 << 2)
644# define RADEON_RB3D_ZC_FLUSH_ALL 0x5 691# define RADEON_RB3D_ZC_FLUSH_ALL 0x5
645# define RADEON_RB3D_ZC_BUSY (1 << 31) 692# define RADEON_RB3D_ZC_BUSY (1 << 31)
693#define R300_ZB_ZCACHE_CTLSTAT 0x4f18
694# define R300_ZC_FLUSH (1 << 0)
695# define R300_ZC_FREE (1 << 1)
696# define R300_ZC_FLUSH_ALL 0x3
697# define R300_ZC_BUSY (1 << 31)
646#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c 698#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
647# define RADEON_RB3D_DC_FLUSH (3 << 0) 699# define RADEON_RB3D_DC_FLUSH (3 << 0)
648# define RADEON_RB3D_DC_FREE (3 << 2) 700# define RADEON_RB3D_DC_FREE (3 << 2)
649# define RADEON_RB3D_DC_FLUSH_ALL 0xf 701# define RADEON_RB3D_DC_FLUSH_ALL 0xf
650# define RADEON_RB3D_DC_BUSY (1 << 31) 702# define RADEON_RB3D_DC_BUSY (1 << 31)
703#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
704# define R300_RB3D_DC_FINISH (1 << 4)
651#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 705#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
652# define RADEON_Z_TEST_MASK (7 << 4) 706# define RADEON_Z_TEST_MASK (7 << 4)
653# define RADEON_Z_TEST_ALWAYS (7 << 4) 707# define RADEON_Z_TEST_ALWAYS (7 << 4)
@@ -1057,6 +1111,31 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
1057 1111
1058#define R200_VAP_PVS_CNTL_1 0x22D0 1112#define R200_VAP_PVS_CNTL_1 0x22D0
1059 1113
1114#define R500_D1CRTC_STATUS 0x609c
1115#define R500_D2CRTC_STATUS 0x689c
1116#define R500_CRTC_V_BLANK (1<<0)
1117
1118#define R500_D1CRTC_FRAME_COUNT 0x60a4
1119#define R500_D2CRTC_FRAME_COUNT 0x68a4
1120
1121#define R500_D1MODE_V_COUNTER 0x6530
1122#define R500_D2MODE_V_COUNTER 0x6d30
1123
1124#define R500_D1MODE_VBLANK_STATUS 0x6534
1125#define R500_D2MODE_VBLANK_STATUS 0x6d34
1126#define R500_VBLANK_OCCURED (1<<0)
1127#define R500_VBLANK_ACK (1<<4)
1128#define R500_VBLANK_STAT (1<<12)
1129#define R500_VBLANK_INT (1<<16)
1130
1131#define R500_DxMODE_INT_MASK 0x6540
1132#define R500_D1MODE_INT_MASK (1<<0)
1133#define R500_D2MODE_INT_MASK (1<<8)
1134
1135#define R500_DISP_INTERRUPT_STATUS 0x7edc
1136#define R500_D1_VBLANK_INTERRUPT (1 << 4)
1137#define R500_D2_VBLANK_INTERRUPT (1 << 5)
1138
1060/* Constants */ 1139/* Constants */
1061#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 1140#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
1062 1141
@@ -1078,42 +1157,50 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
1078#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) 1157#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
1079#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) 1158#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
1080 1159
1081#define RADEON_WRITE_PLL( addr, val ) \ 1160#define RADEON_WRITE_PLL(addr, val) \
1082do { \ 1161do { \
1083 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \ 1162 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \
1084 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \ 1163 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
1085 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \ 1164 RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \
1086} while (0) 1165} while (0)
1087 1166
1088#define RADEON_WRITE_IGPGART( addr, val ) \ 1167#define RADEON_WRITE_PCIE(addr, val) \
1089do { \ 1168do { \
1090 RADEON_WRITE( RADEON_IGPGART_INDEX, \ 1169 RADEON_WRITE8(RADEON_PCIE_INDEX, \
1091 ((addr) & 0x7f) | (1 << 8)); \ 1170 ((addr) & 0xff)); \
1092 RADEON_WRITE( RADEON_IGPGART_DATA, (val) ); \ 1171 RADEON_WRITE(RADEON_PCIE_DATA, (val)); \
1093 RADEON_WRITE( RADEON_IGPGART_INDEX, 0x7f ); \
1094} while (0) 1172} while (0)
1095 1173
1096#define RADEON_WRITE_PCIE( addr, val ) \ 1174#define R500_WRITE_MCIND(addr, val) \
1097do { \ 1175do { \
1098 RADEON_WRITE8( RADEON_PCIE_INDEX, \ 1176 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \
1099 ((addr) & 0xff)); \ 1177 RADEON_WRITE(R520_MC_IND_DATA, (val)); \
1100 RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \ 1178 RADEON_WRITE(R520_MC_IND_INDEX, 0); \
1101} while (0) 1179} while (0)
1102 1180
1103#define RADEON_WRITE_MCIND( addr, val ) \ 1181#define RS480_WRITE_MCIND(addr, val) \
1104 do { \ 1182do { \
1105 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \ 1183 RADEON_WRITE(RS480_NB_MC_INDEX, \
1106 RADEON_WRITE(R520_MC_IND_DATA, (val)); \ 1184 ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \
1107 RADEON_WRITE(R520_MC_IND_INDEX, 0); \ 1185 RADEON_WRITE(RS480_NB_MC_DATA, (val)); \
1108 } while (0) 1186 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); \
1187} while (0)
1109 1188
1110#define RS690_WRITE_MCIND( addr, val ) \ 1189#define RS690_WRITE_MCIND(addr, val) \
1111do { \ 1190do { \
1112 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \ 1191 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \
1113 RADEON_WRITE(RS690_MC_DATA, val); \ 1192 RADEON_WRITE(RS690_MC_DATA, val); \
1114 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \ 1193 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \
1115} while (0) 1194} while (0)
1116 1195
1196#define IGP_WRITE_MCIND(addr, val) \
1197do { \
1198 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) \
1199 RS690_WRITE_MCIND(addr, val); \
1200 else \
1201 RS480_WRITE_MCIND(addr, val); \
1202} while (0)
1203
1117#define CP_PACKET0( reg, n ) \ 1204#define CP_PACKET0( reg, n ) \
1118 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) 1205 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
1119#define CP_PACKET0_TABLE( reg, n ) \ 1206#define CP_PACKET0_TABLE( reg, n ) \
@@ -1154,23 +1241,43 @@ do { \
1154} while (0) 1241} while (0)
1155 1242
1156#define RADEON_FLUSH_CACHE() do { \ 1243#define RADEON_FLUSH_CACHE() do { \
1157 OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \ 1244 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1158 OUT_RING( RADEON_RB3D_DC_FLUSH ); \ 1245 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1246 OUT_RING(RADEON_RB3D_DC_FLUSH); \
1247 } else { \
1248 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1249 OUT_RING(RADEON_RB3D_DC_FLUSH); \
1250 } \
1159} while (0) 1251} while (0)
1160 1252
1161#define RADEON_PURGE_CACHE() do { \ 1253#define RADEON_PURGE_CACHE() do { \
1162 OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \ 1254 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1163 OUT_RING( RADEON_RB3D_DC_FLUSH_ALL ); \ 1255 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1256 OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \
1257 } else { \
1258 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1259 OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \
1260 } \
1164} while (0) 1261} while (0)
1165 1262
1166#define RADEON_FLUSH_ZCACHE() do { \ 1263#define RADEON_FLUSH_ZCACHE() do { \
1167 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ 1264 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1168 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \ 1265 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1266 OUT_RING(RADEON_RB3D_ZC_FLUSH); \
1267 } else { \
1268 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
1269 OUT_RING(R300_ZC_FLUSH); \
1270 } \
1169} while (0) 1271} while (0)
1170 1272
1171#define RADEON_PURGE_ZCACHE() do { \ 1273#define RADEON_PURGE_ZCACHE() do { \
1172 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ 1274 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1173 OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \ 1275 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1276 OUT_RING(RADEON_RB3D_ZC_FLUSH_ALL); \
1277 } else { \
1278 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1279 OUT_RING(R300_ZC_FLUSH_ALL); \
1280 } \
1174} while (0) 1281} while (0)
1175 1282
1176/* ================================================================ 1283/* ================================================================
diff --git a/drivers/char/drm/radeon_irq.c b/drivers/char/drm/radeon_irq.c
index 009af3814b6..ee40d197deb 100644
--- a/drivers/char/drm/radeon_irq.c
+++ b/drivers/char/drm/radeon_irq.c
@@ -234,7 +234,7 @@ int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_pr
234 return radeon_wait_irq(dev, irqwait->irq_seq); 234 return radeon_wait_irq(dev, irqwait->irq_seq);
235} 235}
236 236
237static void radeon_enable_interrupt(struct drm_device *dev) 237void radeon_enable_interrupt(struct drm_device *dev)
238{ 238{
239 drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private; 239 drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
240 240
diff --git a/drivers/char/drm/radeon_microcode.h b/drivers/char/drm/radeon_microcode.h
new file mode 100644
index 00000000000..a348c9e7db1
--- /dev/null
+++ b/drivers/char/drm/radeon_microcode.h
@@ -0,0 +1,1844 @@
1/*
2 * Copyright 2007 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
20 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
21 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
22 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26#ifndef RADEON_MICROCODE_H
27#define RADEON_MICROCODE_H
28
29/* production radeon ucode r1xx-r6xx */
30static const u32 R100_cp_microcode[][2] = {
31 { 0x21007000, 0000000000 },
32 { 0x20007000, 0000000000 },
33 { 0x000000b4, 0x00000004 },
34 { 0x000000b8, 0x00000004 },
35 { 0x6f5b4d4c, 0000000000 },
36 { 0x4c4c427f, 0000000000 },
37 { 0x5b568a92, 0000000000 },
38 { 0x4ca09c6d, 0000000000 },
39 { 0xad4c4c4c, 0000000000 },
40 { 0x4ce1af3d, 0000000000 },
41 { 0xd8afafaf, 0000000000 },
42 { 0xd64c4cdc, 0000000000 },
43 { 0x4cd10d10, 0000000000 },
44 { 0x000f0000, 0x00000016 },
45 { 0x362f242d, 0000000000 },
46 { 0x00000012, 0x00000004 },
47 { 0x000f0000, 0x00000016 },
48 { 0x362f282d, 0000000000 },
49 { 0x000380e7, 0x00000002 },
50 { 0x04002c97, 0x00000002 },
51 { 0x000f0001, 0x00000016 },
52 { 0x333a3730, 0000000000 },
53 { 0x000077ef, 0x00000002 },
54 { 0x00061000, 0x00000002 },
55 { 0x00000021, 0x0000001a },
56 { 0x00004000, 0x0000001e },
57 { 0x00061000, 0x00000002 },
58 { 0x00000021, 0x0000001a },
59 { 0x00004000, 0x0000001e },
60 { 0x00061000, 0x00000002 },
61 { 0x00000021, 0x0000001a },
62 { 0x00004000, 0x0000001e },
63 { 0x00000017, 0x00000004 },
64 { 0x0003802b, 0x00000002 },
65 { 0x040067e0, 0x00000002 },
66 { 0x00000017, 0x00000004 },
67 { 0x000077e0, 0x00000002 },
68 { 0x00065000, 0x00000002 },
69 { 0x000037e1, 0x00000002 },
70 { 0x040067e1, 0x00000006 },
71 { 0x000077e0, 0x00000002 },
72 { 0x000077e1, 0x00000002 },
73 { 0x000077e1, 0x00000006 },
74 { 0xffffffff, 0000000000 },
75 { 0x10000000, 0000000000 },
76 { 0x0003802b, 0x00000002 },
77 { 0x040067e0, 0x00000006 },
78 { 0x00007675, 0x00000002 },
79 { 0x00007676, 0x00000002 },
80 { 0x00007677, 0x00000002 },
81 { 0x00007678, 0x00000006 },
82 { 0x0003802c, 0x00000002 },
83 { 0x04002676, 0x00000002 },
84 { 0x00007677, 0x00000002 },
85 { 0x00007678, 0x00000006 },
86 { 0x0000002f, 0x00000018 },
87 { 0x0000002f, 0x00000018 },
88 { 0000000000, 0x00000006 },
89 { 0x00000030, 0x00000018 },
90 { 0x00000030, 0x00000018 },
91 { 0000000000, 0x00000006 },
92 { 0x01605000, 0x00000002 },
93 { 0x00065000, 0x00000002 },
94 { 0x00098000, 0x00000002 },
95 { 0x00061000, 0x00000002 },
96 { 0x64c0603e, 0x00000004 },
97 { 0x000380e6, 0x00000002 },
98 { 0x040025c5, 0x00000002 },
99 { 0x00080000, 0x00000016 },
100 { 0000000000, 0000000000 },
101 { 0x0400251d, 0x00000002 },
102 { 0x00007580, 0x00000002 },
103 { 0x00067581, 0x00000002 },
104 { 0x04002580, 0x00000002 },
105 { 0x00067581, 0x00000002 },
106 { 0x00000049, 0x00000004 },
107 { 0x00005000, 0000000000 },
108 { 0x000380e6, 0x00000002 },
109 { 0x040025c5, 0x00000002 },
110 { 0x00061000, 0x00000002 },
111 { 0x0000750e, 0x00000002 },
112 { 0x00019000, 0x00000002 },
113 { 0x00011055, 0x00000014 },
114 { 0x00000055, 0x00000012 },
115 { 0x0400250f, 0x00000002 },
116 { 0x0000504f, 0x00000004 },
117 { 0x000380e6, 0x00000002 },
118 { 0x040025c5, 0x00000002 },
119 { 0x00007565, 0x00000002 },
120 { 0x00007566, 0x00000002 },
121 { 0x00000058, 0x00000004 },
122 { 0x000380e6, 0x00000002 },
123 { 0x040025c5, 0x00000002 },
124 { 0x01e655b4, 0x00000002 },
125 { 0x4401b0e4, 0x00000002 },
126 { 0x01c110e4, 0x00000002 },
127 { 0x26667066, 0x00000018 },
128 { 0x040c2565, 0x00000002 },
129 { 0x00000066, 0x00000018 },
130 { 0x04002564, 0x00000002 },
131 { 0x00007566, 0x00000002 },
132 { 0x0000005d, 0x00000004 },
133 { 0x00401069, 0x00000008 },
134 { 0x00101000, 0x00000002 },
135 { 0x000d80ff, 0x00000002 },
136 { 0x0080006c, 0x00000008 },
137 { 0x000f9000, 0x00000002 },
138 { 0x000e00ff, 0x00000002 },
139 { 0000000000, 0x00000006 },
140 { 0x0000008f, 0x00000018 },
141 { 0x0000005b, 0x00000004 },
142 { 0x000380e6, 0x00000002 },
143 { 0x040025c5, 0x00000002 },
144 { 0x00007576, 0x00000002 },
145 { 0x00065000, 0x00000002 },
146 { 0x00009000, 0x00000002 },
147 { 0x00041000, 0x00000002 },
148 { 0x0c00350e, 0x00000002 },
149 { 0x00049000, 0x00000002 },
150 { 0x00051000, 0x00000002 },
151 { 0x01e785f8, 0x00000002 },
152 { 0x00200000, 0x00000002 },
153 { 0x0060007e, 0x0000000c },
154 { 0x00007563, 0x00000002 },
155 { 0x006075f0, 0x00000021 },
156 { 0x20007073, 0x00000004 },
157 { 0x00005073, 0x00000004 },
158 { 0x000380e6, 0x00000002 },
159 { 0x040025c5, 0x00000002 },
160 { 0x00007576, 0x00000002 },
161 { 0x00007577, 0x00000002 },
162 { 0x0000750e, 0x00000002 },
163 { 0x0000750f, 0x00000002 },
164 { 0x00a05000, 0x00000002 },
165 { 0x00600083, 0x0000000c },
166 { 0x006075f0, 0x00000021 },
167 { 0x000075f8, 0x00000002 },
168 { 0x00000083, 0x00000004 },
169 { 0x000a750e, 0x00000002 },
170 { 0x000380e6, 0x00000002 },
171 { 0x040025c5, 0x00000002 },
172 { 0x0020750f, 0x00000002 },
173 { 0x00600086, 0x00000004 },
174 { 0x00007570, 0x00000002 },
175 { 0x00007571, 0x00000002 },
176 { 0x00007572, 0x00000006 },
177 { 0x000380e6, 0x00000002 },
178 { 0x040025c5, 0x00000002 },
179 { 0x00005000, 0x00000002 },
180 { 0x00a05000, 0x00000002 },
181 { 0x00007568, 0x00000002 },
182 { 0x00061000, 0x00000002 },
183 { 0x00000095, 0x0000000c },
184 { 0x00058000, 0x00000002 },
185 { 0x0c607562, 0x00000002 },
186 { 0x00000097, 0x00000004 },
187 { 0x000380e6, 0x00000002 },
188 { 0x040025c5, 0x00000002 },
189 { 0x00600096, 0x00000004 },
190 { 0x400070e5, 0000000000 },
191 { 0x000380e6, 0x00000002 },
192 { 0x040025c5, 0x00000002 },
193 { 0x000380e5, 0x00000002 },
194 { 0x000000a8, 0x0000001c },
195 { 0x000650aa, 0x00000018 },
196 { 0x040025bb, 0x00000002 },
197 { 0x000610ab, 0x00000018 },
198 { 0x040075bc, 0000000000 },
199 { 0x000075bb, 0x00000002 },
200 { 0x000075bc, 0000000000 },
201 { 0x00090000, 0x00000006 },
202 { 0x00090000, 0x00000002 },
203 { 0x000d8002, 0x00000006 },
204 { 0x00007832, 0x00000002 },
205 { 0x00005000, 0x00000002 },
206 { 0x000380e7, 0x00000002 },
207 { 0x04002c97, 0x00000002 },
208 { 0x00007820, 0x00000002 },
209 { 0x00007821, 0x00000002 },
210 { 0x00007800, 0000000000 },
211 { 0x01200000, 0x00000002 },
212 { 0x20077000, 0x00000002 },
213 { 0x01200000, 0x00000002 },
214 { 0x20007000, 0x00000002 },
215 { 0x00061000, 0x00000002 },
216 { 0x0120751b, 0x00000002 },
217 { 0x8040750a, 0x00000002 },
218 { 0x8040750b, 0x00000002 },
219 { 0x00110000, 0x00000002 },
220 { 0x000380e5, 0x00000002 },
221 { 0x000000c6, 0x0000001c },
222 { 0x000610ab, 0x00000018 },
223 { 0x844075bd, 0x00000002 },
224 { 0x000610aa, 0x00000018 },
225 { 0x840075bb, 0x00000002 },
226 { 0x000610ab, 0x00000018 },
227 { 0x844075bc, 0x00000002 },
228 { 0x000000c9, 0x00000004 },
229 { 0x804075bd, 0x00000002 },
230 { 0x800075bb, 0x00000002 },
231 { 0x804075bc, 0x00000002 },
232 { 0x00108000, 0x00000002 },
233 { 0x01400000, 0x00000002 },
234 { 0x006000cd, 0x0000000c },
235 { 0x20c07000, 0x00000020 },
236 { 0x000000cf, 0x00000012 },
237 { 0x00800000, 0x00000006 },
238 { 0x0080751d, 0x00000006 },
239 { 0000000000, 0000000000 },
240 { 0x0000775c, 0x00000002 },
241 { 0x00a05000, 0x00000002 },
242 { 0x00661000, 0x00000002 },
243 { 0x0460275d, 0x00000020 },
244 { 0x00004000, 0000000000 },
245 { 0x01e00830, 0x00000002 },
246 { 0x21007000, 0000000000 },
247 { 0x6464614d, 0000000000 },
248 { 0x69687420, 0000000000 },
249 { 0x00000073, 0000000000 },
250 { 0000000000, 0000000000 },
251 { 0x00005000, 0x00000002 },
252 { 0x000380d0, 0x00000002 },
253 { 0x040025e0, 0x00000002 },
254 { 0x000075e1, 0000000000 },
255 { 0x00000001, 0000000000 },
256 { 0x000380e0, 0x00000002 },
257 { 0x04002394, 0x00000002 },
258 { 0x00005000, 0000000000 },
259 { 0000000000, 0000000000 },
260 { 0000000000, 0000000000 },
261 { 0x00000008, 0000000000 },
262 { 0x00000004, 0000000000 },
263 { 0000000000, 0000000000 },
264 { 0000000000, 0000000000 },
265 { 0000000000, 0000000000 },
266 { 0000000000, 0000000000 },
267 { 0000000000, 0000000000 },
268 { 0000000000, 0000000000 },
269 { 0000000000, 0000000000 },
270 { 0000000000, 0000000000 },
271 { 0000000000, 0000000000 },
272 { 0000000000, 0000000000 },
273 { 0000000000, 0000000000 },
274 { 0000000000, 0000000000 },
275 { 0000000000, 0000000000 },
276 { 0000000000, 0000000000 },
277 { 0000000000, 0000000000 },
278 { 0000000000, 0000000000 },
279 { 0000000000, 0000000000 },
280 { 0000000000, 0000000000 },
281 { 0000000000, 0000000000 },
282 { 0000000000, 0000000000 },
283 { 0000000000, 0000000000 },
284 { 0000000000, 0000000000 },
285 { 0000000000, 0000000000 },
286 { 0000000000, 0000000000 },
287};
288
289static const u32 R200_cp_microcode[][2] = {
290 { 0x21007000, 0000000000 },
291 { 0x20007000, 0000000000 },
292 { 0x000000bf, 0x00000004 },
293 { 0x000000c3, 0x00000004 },
294 { 0x7a685e5d, 0000000000 },
295 { 0x5d5d5588, 0000000000 },
296 { 0x68659197, 0000000000 },
297 { 0x5da19f78, 0000000000 },
298 { 0x5d5d5d5d, 0000000000 },
299 { 0x5dee5d50, 0000000000 },
300 { 0xf2acacac, 0000000000 },
301 { 0xe75df9e9, 0000000000 },
302 { 0xb1dd0e11, 0000000000 },
303 { 0xe2afafaf, 0000000000 },
304 { 0x000f0000, 0x00000016 },
305 { 0x452f232d, 0000000000 },
306 { 0x00000013, 0x00000004 },
307 { 0x000f0000, 0x00000016 },
308 { 0x452f272d, 0000000000 },
309 { 0x000f0001, 0x00000016 },
310 { 0x3e4d4a37, 0000000000 },
311 { 0x000077ef, 0x00000002 },
312 { 0x00061000, 0x00000002 },
313 { 0x00000020, 0x0000001a },
314 { 0x00004000, 0x0000001e },
315 { 0x00061000, 0x00000002 },
316 { 0x00000020, 0x0000001a },
317 { 0x00004000, 0x0000001e },
318 { 0x00061000, 0x00000002 },
319 { 0x00000020, 0x0000001a },
320 { 0x00004000, 0x0000001e },
321 { 0x00000016, 0x00000004 },
322 { 0x0003802a, 0x00000002 },
323 { 0x040067e0, 0x00000002 },
324 { 0x00000016, 0x00000004 },
325 { 0x000077e0, 0x00000002 },
326 { 0x00065000, 0x00000002 },
327 { 0x000037e1, 0x00000002 },
328 { 0x040067e1, 0x00000006 },
329 { 0x000077e0, 0x00000002 },
330 { 0x000077e1, 0x00000002 },
331 { 0x000077e1, 0x00000006 },
332 { 0xffffffff, 0000000000 },
333 { 0x10000000, 0000000000 },
334 { 0x07f007f0, 0000000000 },
335 { 0x0003802a, 0x00000002 },
336 { 0x040067e0, 0x00000006 },
337 { 0x0003802c, 0x00000002 },
338 { 0x04002741, 0x00000002 },
339 { 0x04002741, 0x00000002 },
340 { 0x04002743, 0x00000002 },
341 { 0x00007675, 0x00000002 },
342 { 0x00007676, 0x00000002 },
343 { 0x00007677, 0x00000002 },
344 { 0x00007678, 0x00000006 },
345 { 0x0003802c, 0x00000002 },
346 { 0x04002741, 0x00000002 },
347 { 0x04002741, 0x00000002 },
348 { 0x04002743, 0x00000002 },
349 { 0x00007676, 0x00000002 },
350 { 0x00007677, 0x00000002 },
351 { 0x00007678, 0x00000006 },
352 { 0x0003802b, 0x00000002 },
353 { 0x04002676, 0x00000002 },
354 { 0x00007677, 0x00000002 },
355 { 0x0003802c, 0x00000002 },
356 { 0x04002741, 0x00000002 },
357 { 0x04002743, 0x00000002 },
358 { 0x00007678, 0x00000006 },
359 { 0x0003802c, 0x00000002 },
360 { 0x04002741, 0x00000002 },
361 { 0x04002741, 0x00000002 },
362 { 0x04002743, 0x00000002 },
363 { 0x00007678, 0x00000006 },
364 { 0x0000002f, 0x00000018 },
365 { 0x0000002f, 0x00000018 },
366 { 0000000000, 0x00000006 },
367 { 0x00000037, 0x00000018 },
368 { 0x00000037, 0x00000018 },
369 { 0000000000, 0x00000006 },
370 { 0x01605000, 0x00000002 },
371 { 0x00065000, 0x00000002 },
372 { 0x00098000, 0x00000002 },
373 { 0x00061000, 0x00000002 },
374 { 0x64c06051, 0x00000004 },
375 { 0x00080000, 0x00000016 },
376 { 0000000000, 0000000000 },
377 { 0x0400251d, 0x00000002 },
378 { 0x00007580, 0x00000002 },
379 { 0x00067581, 0x00000002 },
380 { 0x04002580, 0x00000002 },
381 { 0x00067581, 0x00000002 },
382 { 0x0000005a, 0x00000004 },
383 { 0x00005000, 0000000000 },
384 { 0x00061000, 0x00000002 },
385 { 0x0000750e, 0x00000002 },
386 { 0x00019000, 0x00000002 },
387 { 0x00011064, 0x00000014 },
388 { 0x00000064, 0x00000012 },
389 { 0x0400250f, 0x00000002 },
390 { 0x0000505e, 0x00000004 },
391 { 0x00007565, 0x00000002 },
392 { 0x00007566, 0x00000002 },
393 { 0x00000065, 0x00000004 },
394 { 0x01e655b4, 0x00000002 },
395 { 0x4401b0f0, 0x00000002 },
396 { 0x01c110f0, 0x00000002 },
397 { 0x26667071, 0x00000018 },
398 { 0x040c2565, 0x00000002 },
399 { 0x00000071, 0x00000018 },
400 { 0x04002564, 0x00000002 },
401 { 0x00007566, 0x00000002 },
402 { 0x00000068, 0x00000004 },
403 { 0x00401074, 0x00000008 },
404 { 0x00101000, 0x00000002 },
405 { 0x000d80ff, 0x00000002 },
406 { 0x00800077, 0x00000008 },
407 { 0x000f9000, 0x00000002 },
408 { 0x000e00ff, 0x00000002 },
409 { 0000000000, 0x00000006 },
410 { 0x00000094, 0x00000018 },
411 { 0x00000068, 0x00000004 },
412 { 0x00007576, 0x00000002 },
413 { 0x00065000, 0x00000002 },
414 { 0x00009000, 0x00000002 },
415 { 0x00041000, 0x00000002 },
416 { 0x0c00350e, 0x00000002 },
417 { 0x00049000, 0x00000002 },
418 { 0x00051000, 0x00000002 },
419 { 0x01e785f8, 0x00000002 },
420 { 0x00200000, 0x00000002 },
421 { 0x00600087, 0x0000000c },
422 { 0x00007563, 0x00000002 },
423 { 0x006075f0, 0x00000021 },
424 { 0x2000707c, 0x00000004 },
425 { 0x0000507c, 0x00000004 },
426 { 0x00007576, 0x00000002 },
427 { 0x00007577, 0x00000002 },
428 { 0x0000750e, 0x00000002 },
429 { 0x0000750f, 0x00000002 },
430 { 0x00a05000, 0x00000002 },
431 { 0x0060008a, 0x0000000c },
432 { 0x006075f0, 0x00000021 },
433 { 0x000075f8, 0x00000002 },
434 { 0x0000008a, 0x00000004 },
435 { 0x000a750e, 0x00000002 },
436 { 0x0020750f, 0x00000002 },
437 { 0x0060008d, 0x00000004 },
438 { 0x00007570, 0x00000002 },
439 { 0x00007571, 0x00000002 },
440 { 0x00007572, 0x00000006 },
441 { 0x00005000, 0x00000002 },
442 { 0x00a05000, 0x00000002 },
443 { 0x00007568, 0x00000002 },
444 { 0x00061000, 0x00000002 },
445 { 0x00000098, 0x0000000c },
446 { 0x00058000, 0x00000002 },
447 { 0x0c607562, 0x00000002 },
448 { 0x0000009a, 0x00000004 },
449 { 0x00600099, 0x00000004 },
450 { 0x400070f1, 0000000000 },
451 { 0x000380f1, 0x00000002 },
452 { 0x000000a7, 0x0000001c },
453 { 0x000650a9, 0x00000018 },
454 { 0x040025bb, 0x00000002 },
455 { 0x000610aa, 0x00000018 },
456 { 0x040075bc, 0000000000 },
457 { 0x000075bb, 0x00000002 },
458 { 0x000075bc, 0000000000 },
459 { 0x00090000, 0x00000006 },
460 { 0x00090000, 0x00000002 },
461 { 0x000d8002, 0x00000006 },
462 { 0x00005000, 0x00000002 },
463 { 0x00007821, 0x00000002 },
464 { 0x00007800, 0000000000 },
465 { 0x00007821, 0x00000002 },
466 { 0x00007800, 0000000000 },
467 { 0x01665000, 0x00000002 },
468 { 0x000a0000, 0x00000002 },
469 { 0x000671cc, 0x00000002 },
470 { 0x0286f1cd, 0x00000002 },
471 { 0x000000b7, 0x00000010 },
472 { 0x21007000, 0000000000 },
473 { 0x000000be, 0x0000001c },
474 { 0x00065000, 0x00000002 },
475 { 0x000a0000, 0x00000002 },
476 { 0x00061000, 0x00000002 },
477 { 0x000b0000, 0x00000002 },
478 { 0x38067000, 0x00000002 },
479 { 0x000a00ba, 0x00000004 },
480 { 0x20007000, 0000000000 },
481 { 0x01200000, 0x00000002 },
482 { 0x20077000, 0x00000002 },
483 { 0x01200000, 0x00000002 },
484 { 0x20007000, 0000000000 },
485 { 0x00061000, 0x00000002 },
486 { 0x0120751b, 0x00000002 },
487 { 0x8040750a, 0x00000002 },
488 { 0x8040750b, 0x00000002 },
489 { 0x00110000, 0x00000002 },
490 { 0x000380f1, 0x00000002 },
491 { 0x000000d1, 0x0000001c },
492 { 0x000610aa, 0x00000018 },
493 { 0x844075bd, 0x00000002 },
494 { 0x000610a9, 0x00000018 },
495 { 0x840075bb, 0x00000002 },
496 { 0x000610aa, 0x00000018 },
497 { 0x844075bc, 0x00000002 },
498 { 0x000000d4, 0x00000004 },
499 { 0x804075bd, 0x00000002 },
500 { 0x800075bb, 0x00000002 },
501 { 0x804075bc, 0x00000002 },
502 { 0x00108000, 0x00000002 },
503 { 0x01400000, 0x00000002 },
504 { 0x006000d8, 0x0000000c },
505 { 0x20c07000, 0x00000020 },
506 { 0x000000da, 0x00000012 },
507 { 0x00800000, 0x00000006 },
508 { 0x0080751d, 0x00000006 },
509 { 0x000025bb, 0x00000002 },
510 { 0x000040d4, 0x00000004 },
511 { 0x0000775c, 0x00000002 },
512 { 0x00a05000, 0x00000002 },
513 { 0x00661000, 0x00000002 },
514 { 0x0460275d, 0x00000020 },
515 { 0x00004000, 0000000000 },
516 { 0x00007999, 0x00000002 },
517 { 0x00a05000, 0x00000002 },
518 { 0x00661000, 0x00000002 },
519 { 0x0460299b, 0x00000020 },
520 { 0x00004000, 0000000000 },
521 { 0x01e00830, 0x00000002 },
522 { 0x21007000, 0000000000 },
523 { 0x00005000, 0x00000002 },
524 { 0x00038056, 0x00000002 },
525 { 0x040025e0, 0x00000002 },
526 { 0x000075e1, 0000000000 },
527 { 0x00000001, 0000000000 },
528 { 0x000380ed, 0x00000002 },
529 { 0x04007394, 0000000000 },
530 { 0000000000, 0000000000 },
531 { 0000000000, 0000000000 },
532 { 0x000078c4, 0x00000002 },
533 { 0x000078c5, 0x00000002 },
534 { 0x000078c6, 0x00000002 },
535 { 0x00007924, 0x00000002 },
536 { 0x00007925, 0x00000002 },
537 { 0x00007926, 0x00000002 },
538 { 0x000000f2, 0x00000004 },
539 { 0x00007924, 0x00000002 },
540 { 0x00007925, 0x00000002 },
541 { 0x00007926, 0x00000002 },
542 { 0x000000f9, 0x00000004 },
543 { 0000000000, 0000000000 },
544 { 0000000000, 0000000000 },
545 { 0000000000, 0000000000 },
546};
547
548static const u32 R300_cp_microcode[][2] = {
549 { 0x4200e000, 0000000000 },
550 { 0x4000e000, 0000000000 },
551 { 0x000000ae, 0x00000008 },
552 { 0x000000b2, 0x00000008 },
553 { 0x67554b4a, 0000000000 },
554 { 0x4a4a4475, 0000000000 },
555 { 0x55527d83, 0000000000 },
556 { 0x4a8c8b65, 0000000000 },
557 { 0x4aef4af6, 0000000000 },
558 { 0x4ae14a4a, 0000000000 },
559 { 0xe4979797, 0000000000 },
560 { 0xdb4aebdd, 0000000000 },
561 { 0x9ccc4a4a, 0000000000 },
562 { 0xd1989898, 0000000000 },
563 { 0x4a0f9ad6, 0000000000 },
564 { 0x000ca000, 0x00000004 },
565 { 0x000d0012, 0x00000038 },
566 { 0x0000e8b4, 0x00000004 },
567 { 0x000d0014, 0x00000038 },
568 { 0x0000e8b6, 0x00000004 },
569 { 0x000d0016, 0x00000038 },
570 { 0x0000e854, 0x00000004 },
571 { 0x000d0018, 0x00000038 },
572 { 0x0000e855, 0x00000004 },
573 { 0x000d001a, 0x00000038 },
574 { 0x0000e856, 0x00000004 },
575 { 0x000d001c, 0x00000038 },
576 { 0x0000e857, 0x00000004 },
577 { 0x000d001e, 0x00000038 },
578 { 0x0000e824, 0x00000004 },
579 { 0x000d0020, 0x00000038 },
580 { 0x0000e825, 0x00000004 },
581 { 0x000d0022, 0x00000038 },
582 { 0x0000e830, 0x00000004 },
583 { 0x000d0024, 0x00000038 },
584 { 0x0000f0c0, 0x00000004 },
585 { 0x000d0026, 0x00000038 },
586 { 0x0000f0c1, 0x00000004 },
587 { 0x000d0028, 0x00000038 },
588 { 0x0000f041, 0x00000004 },
589 { 0x000d002a, 0x00000038 },
590 { 0x0000f184, 0x00000004 },
591 { 0x000d002c, 0x00000038 },
592 { 0x0000f185, 0x00000004 },
593 { 0x000d002e, 0x00000038 },
594 { 0x0000f186, 0x00000004 },
595 { 0x000d0030, 0x00000038 },
596 { 0x0000f187, 0x00000004 },
597 { 0x000d0032, 0x00000038 },
598 { 0x0000f180, 0x00000004 },
599 { 0x000d0034, 0x00000038 },
600 { 0x0000f393, 0x00000004 },
601 { 0x000d0036, 0x00000038 },
602 { 0x0000f38a, 0x00000004 },
603 { 0x000d0038, 0x00000038 },
604 { 0x0000f38e, 0x00000004 },
605 { 0x0000e821, 0x00000004 },
606 { 0x0140a000, 0x00000004 },
607 { 0x00000043, 0x00000018 },
608 { 0x00cce800, 0x00000004 },
609 { 0x001b0001, 0x00000004 },
610 { 0x08004800, 0x00000004 },
611 { 0x001b0001, 0x00000004 },
612 { 0x08004800, 0x00000004 },
613 { 0x001b0001, 0x00000004 },
614 { 0x08004800, 0x00000004 },
615 { 0x0000003a, 0x00000008 },
616 { 0x0000a000, 0000000000 },
617 { 0x2000451d, 0x00000004 },
618 { 0x0000e580, 0x00000004 },
619 { 0x000ce581, 0x00000004 },
620 { 0x08004580, 0x00000004 },
621 { 0x000ce581, 0x00000004 },
622 { 0x00000047, 0x00000008 },
623 { 0x0000a000, 0000000000 },
624 { 0x000c2000, 0x00000004 },
625 { 0x0000e50e, 0x00000004 },
626 { 0x00032000, 0x00000004 },
627 { 0x00022051, 0x00000028 },
628 { 0x00000051, 0x00000024 },
629 { 0x0800450f, 0x00000004 },
630 { 0x0000a04b, 0x00000008 },
631 { 0x0000e565, 0x00000004 },
632 { 0x0000e566, 0x00000004 },
633 { 0x00000052, 0x00000008 },
634 { 0x03cca5b4, 0x00000004 },
635 { 0x05432000, 0x00000004 },
636 { 0x00022000, 0x00000004 },
637 { 0x4ccce05e, 0x00000030 },
638 { 0x08274565, 0x00000004 },
639 { 0x0000005e, 0x00000030 },
640 { 0x08004564, 0x00000004 },
641 { 0x0000e566, 0x00000004 },
642 { 0x00000055, 0x00000008 },
643 { 0x00802061, 0x00000010 },
644 { 0x00202000, 0x00000004 },
645 { 0x001b00ff, 0x00000004 },
646 { 0x01000064, 0x00000010 },
647 { 0x001f2000, 0x00000004 },
648 { 0x001c00ff, 0x00000004 },
649 { 0000000000, 0x0000000c },
650 { 0x00000080, 0x00000030 },
651 { 0x00000055, 0x00000008 },
652 { 0x0000e576, 0x00000004 },
653 { 0x000ca000, 0x00000004 },
654 { 0x00012000, 0x00000004 },
655 { 0x00082000, 0x00000004 },
656 { 0x1800650e, 0x00000004 },
657 { 0x00092000, 0x00000004 },
658 { 0x000a2000, 0x00000004 },
659 { 0x000f0000, 0x00000004 },
660 { 0x00400000, 0x00000004 },
661 { 0x00000074, 0x00000018 },
662 { 0x0000e563, 0x00000004 },
663 { 0x00c0e5f9, 0x000000c2 },
664 { 0x00000069, 0x00000008 },
665 { 0x0000a069, 0x00000008 },
666 { 0x0000e576, 0x00000004 },
667 { 0x0000e577, 0x00000004 },
668 { 0x0000e50e, 0x00000004 },
669 { 0x0000e50f, 0x00000004 },
670 { 0x0140a000, 0x00000004 },
671 { 0x00000077, 0x00000018 },
672 { 0x00c0e5f9, 0x000000c2 },
673 { 0x00000077, 0x00000008 },
674 { 0x0014e50e, 0x00000004 },
675 { 0x0040e50f, 0x00000004 },
676 { 0x00c0007a, 0x00000008 },
677 { 0x0000e570, 0x00000004 },
678 { 0x0000e571, 0x00000004 },
679 { 0x0000e572, 0x0000000c },
680 { 0x0000a000, 0x00000004 },
681 { 0x0140a000, 0x00000004 },
682 { 0x0000e568, 0x00000004 },
683 { 0x000c2000, 0x00000004 },
684 { 0x00000084, 0x00000018 },
685 { 0x000b0000, 0x00000004 },
686 { 0x18c0e562, 0x00000004 },
687 { 0x00000086, 0x00000008 },
688 { 0x00c00085, 0x00000008 },
689 { 0x000700e3, 0x00000004 },
690 { 0x00000092, 0x00000038 },
691 { 0x000ca094, 0x00000030 },
692 { 0x080045bb, 0x00000004 },
693 { 0x000c2095, 0x00000030 },
694 { 0x0800e5bc, 0000000000 },
695 { 0x0000e5bb, 0x00000004 },
696 { 0x0000e5bc, 0000000000 },
697 { 0x00120000, 0x0000000c },
698 { 0x00120000, 0x00000004 },
699 { 0x001b0002, 0x0000000c },
700 { 0x0000a000, 0x00000004 },
701 { 0x0000e821, 0x00000004 },
702 { 0x0000e800, 0000000000 },
703 { 0x0000e821, 0x00000004 },
704 { 0x0000e82e, 0000000000 },
705 { 0x02cca000, 0x00000004 },
706 { 0x00140000, 0x00000004 },
707 { 0x000ce1cc, 0x00000004 },
708 { 0x050de1cd, 0x00000004 },
709 { 0x00400000, 0x00000004 },
710 { 0x000000a4, 0x00000018 },
711 { 0x00c0a000, 0x00000004 },
712 { 0x000000a1, 0x00000008 },
713 { 0x000000a6, 0x00000020 },
714 { 0x4200e000, 0000000000 },
715 { 0x000000ad, 0x00000038 },
716 { 0x000ca000, 0x00000004 },
717 { 0x00140000, 0x00000004 },
718 { 0x000c2000, 0x00000004 },
719 { 0x00160000, 0x00000004 },
720 { 0x700ce000, 0x00000004 },
721 { 0x001400a9, 0x00000008 },
722 { 0x4000e000, 0000000000 },
723 { 0x02400000, 0x00000004 },
724 { 0x400ee000, 0x00000004 },
725 { 0x02400000, 0x00000004 },
726 { 0x4000e000, 0000000000 },
727 { 0x000c2000, 0x00000004 },
728 { 0x0240e51b, 0x00000004 },
729 { 0x0080e50a, 0x00000005 },
730 { 0x0080e50b, 0x00000005 },
731 { 0x00220000, 0x00000004 },
732 { 0x000700e3, 0x00000004 },
733 { 0x000000c0, 0x00000038 },
734 { 0x000c2095, 0x00000030 },
735 { 0x0880e5bd, 0x00000005 },
736 { 0x000c2094, 0x00000030 },
737 { 0x0800e5bb, 0x00000005 },
738 { 0x000c2095, 0x00000030 },
739 { 0x0880e5bc, 0x00000005 },
740 { 0x000000c3, 0x00000008 },
741 { 0x0080e5bd, 0x00000005 },
742 { 0x0000e5bb, 0x00000005 },
743 { 0x0080e5bc, 0x00000005 },
744 { 0x00210000, 0x00000004 },
745 { 0x02800000, 0x00000004 },
746 { 0x00c000c7, 0x00000018 },
747 { 0x4180e000, 0x00000040 },
748 { 0x000000c9, 0x00000024 },
749 { 0x01000000, 0x0000000c },
750 { 0x0100e51d, 0x0000000c },
751 { 0x000045bb, 0x00000004 },
752 { 0x000080c3, 0x00000008 },
753 { 0x0000f3ce, 0x00000004 },
754 { 0x0140a000, 0x00000004 },
755 { 0x00cc2000, 0x00000004 },
756 { 0x08c053cf, 0x00000040 },
757 { 0x00008000, 0000000000 },
758 { 0x0000f3d2, 0x00000004 },
759 { 0x0140a000, 0x00000004 },
760 { 0x00cc2000, 0x00000004 },
761 { 0x08c053d3, 0x00000040 },
762 { 0x00008000, 0000000000 },
763 { 0x0000f39d, 0x00000004 },
764 { 0x0140a000, 0x00000004 },
765 { 0x00cc2000, 0x00000004 },
766 { 0x08c0539e, 0x00000040 },
767 { 0x00008000, 0000000000 },
768 { 0x03c00830, 0x00000004 },
769 { 0x4200e000, 0000000000 },
770 { 0x0000a000, 0x00000004 },
771 { 0x200045e0, 0x00000004 },
772 { 0x0000e5e1, 0000000000 },
773 { 0x00000001, 0000000000 },
774 { 0x000700e0, 0x00000004 },
775 { 0x0800e394, 0000000000 },
776 { 0000000000, 0000000000 },
777 { 0x0000e8c4, 0x00000004 },
778 { 0x0000e8c5, 0x00000004 },
779 { 0x0000e8c6, 0x00000004 },
780 { 0x0000e928, 0x00000004 },
781 { 0x0000e929, 0x00000004 },
782 { 0x0000e92a, 0x00000004 },
783 { 0x000000e4, 0x00000008 },
784 { 0x0000e928, 0x00000004 },
785 { 0x0000e929, 0x00000004 },
786 { 0x0000e92a, 0x00000004 },
787 { 0x000000eb, 0x00000008 },
788 { 0x02c02000, 0x00000004 },
789 { 0x00060000, 0x00000004 },
790 { 0x000000f3, 0x00000034 },
791 { 0x000000f0, 0x00000008 },
792 { 0x00008000, 0x00000004 },
793 { 0xc000e000, 0000000000 },
794 { 0000000000, 0000000000 },
795 { 0x000c2000, 0x00000004 },
796 { 0x001d0018, 0x00000004 },
797 { 0x001a0001, 0x00000004 },
798 { 0x000000fb, 0x00000034 },
799 { 0x0000004a, 0x00000008 },
800 { 0x0500a04a, 0x00000008 },
801 { 0000000000, 0000000000 },
802 { 0000000000, 0000000000 },
803 { 0000000000, 0000000000 },
804 { 0000000000, 0000000000 },
805};
806
807static const u32 R420_cp_microcode[][2] = {
808 { 0x4200e000, 0000000000 },
809 { 0x4000e000, 0000000000 },
810 { 0x00000099, 0x00000008 },
811 { 0x0000009d, 0x00000008 },
812 { 0x4a554b4a, 0000000000 },
813 { 0x4a4a4467, 0000000000 },
814 { 0x55526f75, 0000000000 },
815 { 0x4a7e7d65, 0000000000 },
816 { 0xd9d3dff6, 0000000000 },
817 { 0x4ac54a4a, 0000000000 },
818 { 0xc8828282, 0000000000 },
819 { 0xbf4acfc1, 0000000000 },
820 { 0x87b04a4a, 0000000000 },
821 { 0xb5838383, 0000000000 },
822 { 0x4a0f85ba, 0000000000 },
823 { 0x000ca000, 0x00000004 },
824 { 0x000d0012, 0x00000038 },
825 { 0x0000e8b4, 0x00000004 },
826 { 0x000d0014, 0x00000038 },
827 { 0x0000e8b6, 0x00000004 },
828 { 0x000d0016, 0x00000038 },
829 { 0x0000e854, 0x00000004 },
830 { 0x000d0018, 0x00000038 },
831 { 0x0000e855, 0x00000004 },
832 { 0x000d001a, 0x00000038 },
833 { 0x0000e856, 0x00000004 },
834 { 0x000d001c, 0x00000038 },
835 { 0x0000e857, 0x00000004 },
836 { 0x000d001e, 0x00000038 },
837 { 0x0000e824, 0x00000004 },
838 { 0x000d0020, 0x00000038 },
839 { 0x0000e825, 0x00000004 },
840 { 0x000d0022, 0x00000038 },
841 { 0x0000e830, 0x00000004 },
842 { 0x000d0024, 0x00000038 },
843 { 0x0000f0c0, 0x00000004 },
844 { 0x000d0026, 0x00000038 },
845 { 0x0000f0c1, 0x00000004 },
846 { 0x000d0028, 0x00000038 },
847 { 0x0000f041, 0x00000004 },
848 { 0x000d002a, 0x00000038 },
849 { 0x0000f184, 0x00000004 },
850 { 0x000d002c, 0x00000038 },
851 { 0x0000f185, 0x00000004 },
852 { 0x000d002e, 0x00000038 },
853 { 0x0000f186, 0x00000004 },
854 { 0x000d0030, 0x00000038 },
855 { 0x0000f187, 0x00000004 },
856 { 0x000d0032, 0x00000038 },
857 { 0x0000f180, 0x00000004 },
858 { 0x000d0034, 0x00000038 },
859 { 0x0000f393, 0x00000004 },
860 { 0x000d0036, 0x00000038 },
861 { 0x0000f38a, 0x00000004 },
862 { 0x000d0038, 0x00000038 },
863 { 0x0000f38e, 0x00000004 },
864 { 0x0000e821, 0x00000004 },
865 { 0x0140a000, 0x00000004 },
866 { 0x00000043, 0x00000018 },
867 { 0x00cce800, 0x00000004 },
868 { 0x001b0001, 0x00000004 },
869 { 0x08004800, 0x00000004 },
870 { 0x001b0001, 0x00000004 },
871 { 0x08004800, 0x00000004 },
872 { 0x001b0001, 0x00000004 },
873 { 0x08004800, 0x00000004 },
874 { 0x0000003a, 0x00000008 },
875 { 0x0000a000, 0000000000 },
876 { 0x2000451d, 0x00000004 },
877 { 0x0000e580, 0x00000004 },
878 { 0x000ce581, 0x00000004 },
879 { 0x08004580, 0x00000004 },
880 { 0x000ce581, 0x00000004 },
881 { 0x00000047, 0x00000008 },
882 { 0x0000a000, 0000000000 },
883 { 0x000c2000, 0x00000004 },
884 { 0x0000e50e, 0x00000004 },
885 { 0x00032000, 0x00000004 },
886 { 0x00022051, 0x00000028 },
887 { 0x00000051, 0x00000024 },
888 { 0x0800450f, 0x00000004 },
889 { 0x0000a04b, 0x00000008 },
890 { 0x0000e565, 0x00000004 },
891 { 0x0000e566, 0x00000004 },
892 { 0x00000052, 0x00000008 },
893 { 0x03cca5b4, 0x00000004 },
894 { 0x05432000, 0x00000004 },
895 { 0x00022000, 0x00000004 },
896 { 0x4ccce05e, 0x00000030 },
897 { 0x08274565, 0x00000004 },
898 { 0x0000005e, 0x00000030 },
899 { 0x08004564, 0x00000004 },
900 { 0x0000e566, 0x00000004 },
901 { 0x00000055, 0x00000008 },
902 { 0x00802061, 0x00000010 },
903 { 0x00202000, 0x00000004 },
904 { 0x001b00ff, 0x00000004 },
905 { 0x01000064, 0x00000010 },
906 { 0x001f2000, 0x00000004 },
907 { 0x001c00ff, 0x00000004 },
908 { 0000000000, 0x0000000c },
909 { 0x00000072, 0x00000030 },
910 { 0x00000055, 0x00000008 },
911 { 0x0000e576, 0x00000004 },
912 { 0x0000e577, 0x00000004 },
913 { 0x0000e50e, 0x00000004 },
914 { 0x0000e50f, 0x00000004 },
915 { 0x0140a000, 0x00000004 },
916 { 0x00000069, 0x00000018 },
917 { 0x00c0e5f9, 0x000000c2 },
918 { 0x00000069, 0x00000008 },
919 { 0x0014e50e, 0x00000004 },
920 { 0x0040e50f, 0x00000004 },
921 { 0x00c0006c, 0x00000008 },
922 { 0x0000e570, 0x00000004 },
923 { 0x0000e571, 0x00000004 },
924 { 0x0000e572, 0x0000000c },
925 { 0x0000a000, 0x00000004 },
926 { 0x0140a000, 0x00000004 },
927 { 0x0000e568, 0x00000004 },
928 { 0x000c2000, 0x00000004 },
929 { 0x00000076, 0x00000018 },
930 { 0x000b0000, 0x00000004 },
931 { 0x18c0e562, 0x00000004 },
932 { 0x00000078, 0x00000008 },
933 { 0x00c00077, 0x00000008 },
934 { 0x000700c7, 0x00000004 },
935 { 0x00000080, 0x00000038 },
936 { 0x0000e5bb, 0x00000004 },
937 { 0x0000e5bc, 0000000000 },
938 { 0x0000a000, 0x00000004 },
939 { 0x0000e821, 0x00000004 },
940 { 0x0000e800, 0000000000 },
941 { 0x0000e821, 0x00000004 },
942 { 0x0000e82e, 0000000000 },
943 { 0x02cca000, 0x00000004 },
944 { 0x00140000, 0x00000004 },
945 { 0x000ce1cc, 0x00000004 },
946 { 0x050de1cd, 0x00000004 },
947 { 0x00400000, 0x00000004 },
948 { 0x0000008f, 0x00000018 },
949 { 0x00c0a000, 0x00000004 },
950 { 0x0000008c, 0x00000008 },
951 { 0x00000091, 0x00000020 },
952 { 0x4200e000, 0000000000 },
953 { 0x00000098, 0x00000038 },
954 { 0x000ca000, 0x00000004 },
955 { 0x00140000, 0x00000004 },
956 { 0x000c2000, 0x00000004 },
957 { 0x00160000, 0x00000004 },
958 { 0x700ce000, 0x00000004 },
959 { 0x00140094, 0x00000008 },
960 { 0x4000e000, 0000000000 },
961 { 0x02400000, 0x00000004 },
962 { 0x400ee000, 0x00000004 },
963 { 0x02400000, 0x00000004 },
964 { 0x4000e000, 0000000000 },
965 { 0x000c2000, 0x00000004 },
966 { 0x0240e51b, 0x00000004 },
967 { 0x0080e50a, 0x00000005 },
968 { 0x0080e50b, 0x00000005 },
969 { 0x00220000, 0x00000004 },
970 { 0x000700c7, 0x00000004 },
971 { 0x000000a4, 0x00000038 },
972 { 0x0080e5bd, 0x00000005 },
973 { 0x0000e5bb, 0x00000005 },
974 { 0x0080e5bc, 0x00000005 },
975 { 0x00210000, 0x00000004 },
976 { 0x02800000, 0x00000004 },
977 { 0x00c000ab, 0x00000018 },
978 { 0x4180e000, 0x00000040 },
979 { 0x000000ad, 0x00000024 },
980 { 0x01000000, 0x0000000c },
981 { 0x0100e51d, 0x0000000c },
982 { 0x000045bb, 0x00000004 },
983 { 0x000080a7, 0x00000008 },
984 { 0x0000f3ce, 0x00000004 },
985 { 0x0140a000, 0x00000004 },
986 { 0x00cc2000, 0x00000004 },
987 { 0x08c053cf, 0x00000040 },
988 { 0x00008000, 0000000000 },
989 { 0x0000f3d2, 0x00000004 },
990 { 0x0140a000, 0x00000004 },
991 { 0x00cc2000, 0x00000004 },
992 { 0x08c053d3, 0x00000040 },
993 { 0x00008000, 0000000000 },
994 { 0x0000f39d, 0x00000004 },
995 { 0x0140a000, 0x00000004 },
996 { 0x00cc2000, 0x00000004 },
997 { 0x08c0539e, 0x00000040 },
998 { 0x00008000, 0000000000 },
999 { 0x03c00830, 0x00000004 },
1000 { 0x4200e000, 0000000000 },
1001 { 0x0000a000, 0x00000004 },
1002 { 0x200045e0, 0x00000004 },
1003 { 0x0000e5e1, 0000000000 },
1004 { 0x00000001, 0000000000 },
1005 { 0x000700c4, 0x00000004 },
1006 { 0x0800e394, 0000000000 },
1007 { 0000000000, 0000000000 },
1008 { 0x0000e8c4, 0x00000004 },
1009 { 0x0000e8c5, 0x00000004 },
1010 { 0x0000e8c6, 0x00000004 },
1011 { 0x0000e928, 0x00000004 },
1012 { 0x0000e929, 0x00000004 },
1013 { 0x0000e92a, 0x00000004 },
1014 { 0x000000c8, 0x00000008 },
1015 { 0x0000e928, 0x00000004 },
1016 { 0x0000e929, 0x00000004 },
1017 { 0x0000e92a, 0x00000004 },
1018 { 0x000000cf, 0x00000008 },
1019 { 0x02c02000, 0x00000004 },
1020 { 0x00060000, 0x00000004 },
1021 { 0x000000d7, 0x00000034 },
1022 { 0x000000d4, 0x00000008 },
1023 { 0x00008000, 0x00000004 },
1024 { 0xc000e000, 0000000000 },
1025 { 0x0000e1cc, 0x00000004 },
1026 { 0x0500e1cd, 0x00000004 },
1027 { 0x000ca000, 0x00000004 },
1028 { 0x000000de, 0x00000034 },
1029 { 0x000000da, 0x00000008 },
1030 { 0x0000a000, 0000000000 },
1031 { 0x0019e1cc, 0x00000004 },
1032 { 0x001b0001, 0x00000004 },
1033 { 0x0500a000, 0x00000004 },
1034 { 0x080041cd, 0x00000004 },
1035 { 0x000ca000, 0x00000004 },
1036 { 0x000000fb, 0x00000034 },
1037 { 0x0000004a, 0x00000008 },
1038 { 0000000000, 0000000000 },
1039 { 0000000000, 0000000000 },
1040 { 0000000000, 0000000000 },
1041 { 0000000000, 0000000000 },
1042 { 0000000000, 0000000000 },
1043 { 0000000000, 0000000000 },
1044 { 0000000000, 0000000000 },
1045 { 0000000000, 0000000000 },
1046 { 0000000000, 0000000000 },
1047 { 0000000000, 0000000000 },
1048 { 0000000000, 0000000000 },
1049 { 0000000000, 0000000000 },
1050 { 0000000000, 0000000000 },
1051 { 0000000000, 0000000000 },
1052 { 0000000000, 0000000000 },
1053 { 0000000000, 0000000000 },
1054 { 0x000c2000, 0x00000004 },
1055 { 0x001d0018, 0x00000004 },
1056 { 0x001a0001, 0x00000004 },
1057 { 0x000000fb, 0x00000034 },
1058 { 0x0000004a, 0x00000008 },
1059 { 0x0500a04a, 0x00000008 },
1060 { 0000000000, 0000000000 },
1061 { 0000000000, 0000000000 },
1062 { 0000000000, 0000000000 },
1063 { 0000000000, 0000000000 },
1064};
1065
1066static const u32 RS600_cp_microcode[][2] = {
1067 { 0x4200e000, 0000000000 },
1068 { 0x4000e000, 0000000000 },
1069 { 0x000000a0, 0x00000008 },
1070 { 0x000000a4, 0x00000008 },
1071 { 0x4a554b4a, 0000000000 },
1072 { 0x4a4a4467, 0000000000 },
1073 { 0x55526f75, 0000000000 },
1074 { 0x4a7e7d65, 0000000000 },
1075 { 0x4ae74af6, 0000000000 },
1076 { 0x4ad34a4a, 0000000000 },
1077 { 0xd6898989, 0000000000 },
1078 { 0xcd4addcf, 0000000000 },
1079 { 0x8ebe4ae2, 0000000000 },
1080 { 0xc38a8a8a, 0000000000 },
1081 { 0x4a0f8cc8, 0000000000 },
1082 { 0x000ca000, 0x00000004 },
1083 { 0x000d0012, 0x00000038 },
1084 { 0x0000e8b4, 0x00000004 },
1085 { 0x000d0014, 0x00000038 },
1086 { 0x0000e8b6, 0x00000004 },
1087 { 0x000d0016, 0x00000038 },
1088 { 0x0000e854, 0x00000004 },
1089 { 0x000d0018, 0x00000038 },
1090 { 0x0000e855, 0x00000004 },
1091 { 0x000d001a, 0x00000038 },
1092 { 0x0000e856, 0x00000004 },
1093 { 0x000d001c, 0x00000038 },
1094 { 0x0000e857, 0x00000004 },
1095 { 0x000d001e, 0x00000038 },
1096 { 0x0000e824, 0x00000004 },
1097 { 0x000d0020, 0x00000038 },
1098 { 0x0000e825, 0x00000004 },
1099 { 0x000d0022, 0x00000038 },
1100 { 0x0000e830, 0x00000004 },
1101 { 0x000d0024, 0x00000038 },
1102 { 0x0000f0c0, 0x00000004 },
1103 { 0x000d0026, 0x00000038 },
1104 { 0x0000f0c1, 0x00000004 },
1105 { 0x000d0028, 0x00000038 },
1106 { 0x0000f041, 0x00000004 },
1107 { 0x000d002a, 0x00000038 },
1108 { 0x0000f184, 0x00000004 },
1109 { 0x000d002c, 0x00000038 },
1110 { 0x0000f185, 0x00000004 },
1111 { 0x000d002e, 0x00000038 },
1112 { 0x0000f186, 0x00000004 },
1113 { 0x000d0030, 0x00000038 },
1114 { 0x0000f187, 0x00000004 },
1115 { 0x000d0032, 0x00000038 },
1116 { 0x0000f180, 0x00000004 },
1117 { 0x000d0034, 0x00000038 },
1118 { 0x0000f393, 0x00000004 },
1119 { 0x000d0036, 0x00000038 },
1120 { 0x0000f38a, 0x00000004 },
1121 { 0x000d0038, 0x00000038 },
1122 { 0x0000f38e, 0x00000004 },
1123 { 0x0000e821, 0x00000004 },
1124 { 0x0140a000, 0x00000004 },
1125 { 0x00000043, 0x00000018 },
1126 { 0x00cce800, 0x00000004 },
1127 { 0x001b0001, 0x00000004 },
1128 { 0x08004800, 0x00000004 },
1129 { 0x001b0001, 0x00000004 },
1130 { 0x08004800, 0x00000004 },
1131 { 0x001b0001, 0x00000004 },
1132 { 0x08004800, 0x00000004 },
1133 { 0x0000003a, 0x00000008 },
1134 { 0x0000a000, 0000000000 },
1135 { 0x2000451d, 0x00000004 },
1136 { 0x0000e580, 0x00000004 },
1137 { 0x000ce581, 0x00000004 },
1138 { 0x08004580, 0x00000004 },
1139 { 0x000ce581, 0x00000004 },
1140 { 0x00000047, 0x00000008 },
1141 { 0x0000a000, 0000000000 },
1142 { 0x000c2000, 0x00000004 },
1143 { 0x0000e50e, 0x00000004 },
1144 { 0x00032000, 0x00000004 },
1145 { 0x00022051, 0x00000028 },
1146 { 0x00000051, 0x00000024 },
1147 { 0x0800450f, 0x00000004 },
1148 { 0x0000a04b, 0x00000008 },
1149 { 0x0000e565, 0x00000004 },
1150 { 0x0000e566, 0x00000004 },
1151 { 0x00000052, 0x00000008 },
1152 { 0x03cca5b4, 0x00000004 },
1153 { 0x05432000, 0x00000004 },
1154 { 0x00022000, 0x00000004 },
1155 { 0x4ccce05e, 0x00000030 },
1156 { 0x08274565, 0x00000004 },
1157 { 0x0000005e, 0x00000030 },
1158 { 0x08004564, 0x00000004 },
1159 { 0x0000e566, 0x00000004 },
1160 { 0x00000055, 0x00000008 },
1161 { 0x00802061, 0x00000010 },
1162 { 0x00202000, 0x00000004 },
1163 { 0x001b00ff, 0x00000004 },
1164 { 0x01000064, 0x00000010 },
1165 { 0x001f2000, 0x00000004 },
1166 { 0x001c00ff, 0x00000004 },
1167 { 0000000000, 0x0000000c },
1168 { 0x00000072, 0x00000030 },
1169 { 0x00000055, 0x00000008 },
1170 { 0x0000e576, 0x00000004 },
1171 { 0x0000e577, 0x00000004 },
1172 { 0x0000e50e, 0x00000004 },
1173 { 0x0000e50f, 0x00000004 },
1174 { 0x0140a000, 0x00000004 },
1175 { 0x00000069, 0x00000018 },
1176 { 0x00c0e5f9, 0x000000c2 },
1177 { 0x00000069, 0x00000008 },
1178 { 0x0014e50e, 0x00000004 },
1179 { 0x0040e50f, 0x00000004 },
1180 { 0x00c0006c, 0x00000008 },
1181 { 0x0000e570, 0x00000004 },
1182 { 0x0000e571, 0x00000004 },
1183 { 0x0000e572, 0x0000000c },
1184 { 0x0000a000, 0x00000004 },
1185 { 0x0140a000, 0x00000004 },
1186 { 0x0000e568, 0x00000004 },
1187 { 0x000c2000, 0x00000004 },
1188 { 0x00000076, 0x00000018 },
1189 { 0x000b0000, 0x00000004 },
1190 { 0x18c0e562, 0x00000004 },
1191 { 0x00000078, 0x00000008 },
1192 { 0x00c00077, 0x00000008 },
1193 { 0x000700d5, 0x00000004 },
1194 { 0x00000084, 0x00000038 },
1195 { 0x000ca086, 0x00000030 },
1196 { 0x080045bb, 0x00000004 },
1197 { 0x000c2087, 0x00000030 },
1198 { 0x0800e5bc, 0000000000 },
1199 { 0x0000e5bb, 0x00000004 },
1200 { 0x0000e5bc, 0000000000 },
1201 { 0x00120000, 0x0000000c },
1202 { 0x00120000, 0x00000004 },
1203 { 0x001b0002, 0x0000000c },
1204 { 0x0000a000, 0x00000004 },
1205 { 0x0000e821, 0x00000004 },
1206 { 0x0000e800, 0000000000 },
1207 { 0x0000e821, 0x00000004 },
1208 { 0x0000e82e, 0000000000 },
1209 { 0x02cca000, 0x00000004 },
1210 { 0x00140000, 0x00000004 },
1211 { 0x000ce1cc, 0x00000004 },
1212 { 0x050de1cd, 0x00000004 },
1213 { 0x00400000, 0x00000004 },
1214 { 0x00000096, 0x00000018 },
1215 { 0x00c0a000, 0x00000004 },
1216 { 0x00000093, 0x00000008 },
1217 { 0x00000098, 0x00000020 },
1218 { 0x4200e000, 0000000000 },
1219 { 0x0000009f, 0x00000038 },
1220 { 0x000ca000, 0x00000004 },
1221 { 0x00140000, 0x00000004 },
1222 { 0x000c2000, 0x00000004 },
1223 { 0x00160000, 0x00000004 },
1224 { 0x700ce000, 0x00000004 },
1225 { 0x0014009b, 0x00000008 },
1226 { 0x4000e000, 0000000000 },
1227 { 0x02400000, 0x00000004 },
1228 { 0x400ee000, 0x00000004 },
1229 { 0x02400000, 0x00000004 },
1230 { 0x4000e000, 0000000000 },
1231 { 0x000c2000, 0x00000004 },
1232 { 0x0240e51b, 0x00000004 },
1233 { 0x0080e50a, 0x00000005 },
1234 { 0x0080e50b, 0x00000005 },
1235 { 0x00220000, 0x00000004 },
1236 { 0x000700d5, 0x00000004 },
1237 { 0x000000b2, 0x00000038 },
1238 { 0x000c2087, 0x00000030 },
1239 { 0x0880e5bd, 0x00000005 },
1240 { 0x000c2086, 0x00000030 },
1241 { 0x0800e5bb, 0x00000005 },
1242 { 0x000c2087, 0x00000030 },
1243 { 0x0880e5bc, 0x00000005 },
1244 { 0x000000b5, 0x00000008 },
1245 { 0x0080e5bd, 0x00000005 },
1246 { 0x0000e5bb, 0x00000005 },
1247 { 0x0080e5bc, 0x00000005 },
1248 { 0x00210000, 0x00000004 },
1249 { 0x02800000, 0x00000004 },
1250 { 0x00c000b9, 0x00000018 },
1251 { 0x4180e000, 0x00000040 },
1252 { 0x000000bb, 0x00000024 },
1253 { 0x01000000, 0x0000000c },
1254 { 0x0100e51d, 0x0000000c },
1255 { 0x000045bb, 0x00000004 },
1256 { 0x000080b5, 0x00000008 },
1257 { 0x0000f3ce, 0x00000004 },
1258 { 0x0140a000, 0x00000004 },
1259 { 0x00cc2000, 0x00000004 },
1260 { 0x08c053cf, 0x00000040 },
1261 { 0x00008000, 0000000000 },
1262 { 0x0000f3d2, 0x00000004 },
1263 { 0x0140a000, 0x00000004 },
1264 { 0x00cc2000, 0x00000004 },
1265 { 0x08c053d3, 0x00000040 },
1266 { 0x00008000, 0000000000 },
1267 { 0x0000f39d, 0x00000004 },
1268 { 0x0140a000, 0x00000004 },
1269 { 0x00cc2000, 0x00000004 },
1270 { 0x08c0539e, 0x00000040 },
1271 { 0x00008000, 0000000000 },
1272 { 0x03c00830, 0x00000004 },
1273 { 0x4200e000, 0000000000 },
1274 { 0x0000a000, 0x00000004 },
1275 { 0x200045e0, 0x00000004 },
1276 { 0x0000e5e1, 0000000000 },
1277 { 0x00000001, 0000000000 },
1278 { 0x000700d2, 0x00000004 },
1279 { 0x0800e394, 0000000000 },
1280 { 0000000000, 0000000000 },
1281 { 0x0000e8c4, 0x00000004 },
1282 { 0x0000e8c5, 0x00000004 },
1283 { 0x0000e8c6, 0x00000004 },
1284 { 0x0000e928, 0x00000004 },
1285 { 0x0000e929, 0x00000004 },
1286 { 0x0000e92a, 0x00000004 },
1287 { 0x000000d6, 0x00000008 },
1288 { 0x0000e928, 0x00000004 },
1289 { 0x0000e929, 0x00000004 },
1290 { 0x0000e92a, 0x00000004 },
1291 { 0x000000dd, 0x00000008 },
1292 { 0x00e00116, 0000000000 },
1293 { 0x000700e1, 0x00000004 },
1294 { 0x0800401c, 0x00000004 },
1295 { 0x200050e7, 0x00000004 },
1296 { 0x0000e01d, 0x00000004 },
1297 { 0x000000e4, 0x00000008 },
1298 { 0x02c02000, 0x00000004 },
1299 { 0x00060000, 0x00000004 },
1300 { 0x000000eb, 0x00000034 },
1301 { 0x000000e8, 0x00000008 },
1302 { 0x00008000, 0x00000004 },
1303 { 0xc000e000, 0000000000 },
1304 { 0000000000, 0000000000 },
1305 { 0000000000, 0000000000 },
1306 { 0000000000, 0000000000 },
1307 { 0000000000, 0000000000 },
1308 { 0000000000, 0000000000 },
1309 { 0000000000, 0000000000 },
1310 { 0000000000, 0000000000 },
1311 { 0000000000, 0000000000 },
1312 { 0000000000, 0000000000 },
1313 { 0x000c2000, 0x00000004 },
1314 { 0x001d0018, 0x00000004 },
1315 { 0x001a0001, 0x00000004 },
1316 { 0x000000fb, 0x00000034 },
1317 { 0x0000004a, 0x00000008 },
1318 { 0x0500a04a, 0x00000008 },
1319 { 0000000000, 0000000000 },
1320 { 0000000000, 0000000000 },
1321 { 0000000000, 0000000000 },
1322 { 0000000000, 0000000000 },
1323};
1324
1325static const u32 RS690_cp_microcode[][2] = {
1326 { 0x000000dd, 0x00000008 },
1327 { 0x000000df, 0x00000008 },
1328 { 0x000000a0, 0x00000008 },
1329 { 0x000000a4, 0x00000008 },
1330 { 0x4a554b4a, 0000000000 },
1331 { 0x4a4a4467, 0000000000 },
1332 { 0x55526f75, 0000000000 },
1333 { 0x4a7e7d65, 0000000000 },
1334 { 0x4ad74af6, 0000000000 },
1335 { 0x4ac94a4a, 0000000000 },
1336 { 0xcc898989, 0000000000 },
1337 { 0xc34ad3c5, 0000000000 },
1338 { 0x8e4a4a4a, 0000000000 },
1339 { 0x4a8a8a8a, 0000000000 },
1340 { 0x4a0f8c4a, 0000000000 },
1341 { 0x000ca000, 0x00000004 },
1342 { 0x000d0012, 0x00000038 },
1343 { 0x0000e8b4, 0x00000004 },
1344 { 0x000d0014, 0x00000038 },
1345 { 0x0000e8b6, 0x00000004 },
1346 { 0x000d0016, 0x00000038 },
1347 { 0x0000e854, 0x00000004 },
1348 { 0x000d0018, 0x00000038 },
1349 { 0x0000e855, 0x00000004 },
1350 { 0x000d001a, 0x00000038 },
1351 { 0x0000e856, 0x00000004 },
1352 { 0x000d001c, 0x00000038 },
1353 { 0x0000e857, 0x00000004 },
1354 { 0x000d001e, 0x00000038 },
1355 { 0x0000e824, 0x00000004 },
1356 { 0x000d0020, 0x00000038 },
1357 { 0x0000e825, 0x00000004 },
1358 { 0x000d0022, 0x00000038 },
1359 { 0x0000e830, 0x00000004 },
1360 { 0x000d0024, 0x00000038 },
1361 { 0x0000f0c0, 0x00000004 },
1362 { 0x000d0026, 0x00000038 },
1363 { 0x0000f0c1, 0x00000004 },
1364 { 0x000d0028, 0x00000038 },
1365 { 0x0000f041, 0x00000004 },
1366 { 0x000d002a, 0x00000038 },
1367 { 0x0000f184, 0x00000004 },
1368 { 0x000d002c, 0x00000038 },
1369 { 0x0000f185, 0x00000004 },
1370 { 0x000d002e, 0x00000038 },
1371 { 0x0000f186, 0x00000004 },
1372 { 0x000d0030, 0x00000038 },
1373 { 0x0000f187, 0x00000004 },
1374 { 0x000d0032, 0x00000038 },
1375 { 0x0000f180, 0x00000004 },
1376 { 0x000d0034, 0x00000038 },
1377 { 0x0000f393, 0x00000004 },
1378 { 0x000d0036, 0x00000038 },
1379 { 0x0000f38a, 0x00000004 },
1380 { 0x000d0038, 0x00000038 },
1381 { 0x0000f38e, 0x00000004 },
1382 { 0x0000e821, 0x00000004 },
1383 { 0x0140a000, 0x00000004 },
1384 { 0x00000043, 0x00000018 },
1385 { 0x00cce800, 0x00000004 },
1386 { 0x001b0001, 0x00000004 },
1387 { 0x08004800, 0x00000004 },
1388 { 0x001b0001, 0x00000004 },
1389 { 0x08004800, 0x00000004 },
1390 { 0x001b0001, 0x00000004 },
1391 { 0x08004800, 0x00000004 },
1392 { 0x0000003a, 0x00000008 },
1393 { 0x0000a000, 0000000000 },
1394 { 0x2000451d, 0x00000004 },
1395 { 0x0000e580, 0x00000004 },
1396 { 0x000ce581, 0x00000004 },
1397 { 0x08004580, 0x00000004 },
1398 { 0x000ce581, 0x00000004 },
1399 { 0x00000047, 0x00000008 },
1400 { 0x0000a000, 0000000000 },
1401 { 0x000c2000, 0x00000004 },
1402 { 0x0000e50e, 0x00000004 },
1403 { 0x00032000, 0x00000004 },
1404 { 0x00022051, 0x00000028 },
1405 { 0x00000051, 0x00000024 },
1406 { 0x0800450f, 0x00000004 },
1407 { 0x0000a04b, 0x00000008 },
1408 { 0x0000e565, 0x00000004 },
1409 { 0x0000e566, 0x00000004 },
1410 { 0x00000052, 0x00000008 },
1411 { 0x03cca5b4, 0x00000004 },
1412 { 0x05432000, 0x00000004 },
1413 { 0x00022000, 0x00000004 },
1414 { 0x4ccce05e, 0x00000030 },
1415 { 0x08274565, 0x00000004 },
1416 { 0x0000005e, 0x00000030 },
1417 { 0x08004564, 0x00000004 },
1418 { 0x0000e566, 0x00000004 },
1419 { 0x00000055, 0x00000008 },
1420 { 0x00802061, 0x00000010 },
1421 { 0x00202000, 0x00000004 },
1422 { 0x001b00ff, 0x00000004 },
1423 { 0x01000064, 0x00000010 },
1424 { 0x001f2000, 0x00000004 },
1425 { 0x001c00ff, 0x00000004 },
1426 { 0000000000, 0x0000000c },
1427 { 0x00000072, 0x00000030 },
1428 { 0x00000055, 0x00000008 },
1429 { 0x0000e576, 0x00000004 },
1430 { 0x0000e577, 0x00000004 },
1431 { 0x0000e50e, 0x00000004 },
1432 { 0x0000e50f, 0x00000004 },
1433 { 0x0140a000, 0x00000004 },
1434 { 0x00000069, 0x00000018 },
1435 { 0x00c0e5f9, 0x000000c2 },
1436 { 0x00000069, 0x00000008 },
1437 { 0x0014e50e, 0x00000004 },
1438 { 0x0040e50f, 0x00000004 },
1439 { 0x00c0006c, 0x00000008 },
1440 { 0x0000e570, 0x00000004 },
1441 { 0x0000e571, 0x00000004 },
1442 { 0x0000e572, 0x0000000c },
1443 { 0x0000a000, 0x00000004 },
1444 { 0x0140a000, 0x00000004 },
1445 { 0x0000e568, 0x00000004 },
1446 { 0x000c2000, 0x00000004 },
1447 { 0x00000076, 0x00000018 },
1448 { 0x000b0000, 0x00000004 },
1449 { 0x18c0e562, 0x00000004 },
1450 { 0x00000078, 0x00000008 },
1451 { 0x00c00077, 0x00000008 },
1452 { 0x000700cb, 0x00000004 },
1453 { 0x00000084, 0x00000038 },
1454 { 0x000ca086, 0x00000030 },
1455 { 0x080045bb, 0x00000004 },
1456 { 0x000c2087, 0x00000030 },
1457 { 0x0800e5bc, 0000000000 },
1458 { 0x0000e5bb, 0x00000004 },
1459 { 0x0000e5bc, 0000000000 },
1460 { 0x00120000, 0x0000000c },
1461 { 0x00120000, 0x00000004 },
1462 { 0x001b0002, 0x0000000c },
1463 { 0x0000a000, 0x00000004 },
1464 { 0x0000e821, 0x00000004 },
1465 { 0x0000e800, 0000000000 },
1466 { 0x0000e821, 0x00000004 },
1467 { 0x0000e82e, 0000000000 },
1468 { 0x02cca000, 0x00000004 },
1469 { 0x00140000, 0x00000004 },
1470 { 0x000ce1cc, 0x00000004 },
1471 { 0x050de1cd, 0x00000004 },
1472 { 0x00400000, 0x00000004 },
1473 { 0x00000096, 0x00000018 },
1474 { 0x00c0a000, 0x00000004 },
1475 { 0x00000093, 0x00000008 },
1476 { 0x00000098, 0x00000020 },
1477 { 0x4200e000, 0000000000 },
1478 { 0x0000009f, 0x00000038 },
1479 { 0x000ca000, 0x00000004 },
1480 { 0x00140000, 0x00000004 },
1481 { 0x000c2000, 0x00000004 },
1482 { 0x00160000, 0x00000004 },
1483 { 0x700ce000, 0x00000004 },
1484 { 0x0014009b, 0x00000008 },
1485 { 0x4000e000, 0000000000 },
1486 { 0x02400000, 0x00000004 },
1487 { 0x400ee000, 0x00000004 },
1488 { 0x02400000, 0x00000004 },
1489 { 0x4000e000, 0000000000 },
1490 { 0x00100000, 0x0000002c },
1491 { 0x00004000, 0000000000 },
1492 { 0x080045c8, 0x00000004 },
1493 { 0x00240005, 0x00000004 },
1494 { 0x08004d0b, 0x00000004 },
1495 { 0x000c2000, 0x00000004 },
1496 { 0x0240e51b, 0x00000004 },
1497 { 0x0080e50a, 0x00000005 },
1498 { 0x0080e50b, 0x00000005 },
1499 { 0x00220000, 0x00000004 },
1500 { 0x000700cb, 0x00000004 },
1501 { 0x000000b7, 0x00000038 },
1502 { 0x000c2087, 0x00000030 },
1503 { 0x0880e5bd, 0x00000005 },
1504 { 0x000c2086, 0x00000030 },
1505 { 0x0800e5bb, 0x00000005 },
1506 { 0x000c2087, 0x00000030 },
1507 { 0x0880e5bc, 0x00000005 },
1508 { 0x000000ba, 0x00000008 },
1509 { 0x0080e5bd, 0x00000005 },
1510 { 0x0000e5bb, 0x00000005 },
1511 { 0x0080e5bc, 0x00000005 },
1512 { 0x00210000, 0x00000004 },
1513 { 0x02800000, 0x00000004 },
1514 { 0x00c000be, 0x00000018 },
1515 { 0x4180e000, 0x00000040 },
1516 { 0x000000c0, 0x00000024 },
1517 { 0x01000000, 0x0000000c },
1518 { 0x0100e51d, 0x0000000c },
1519 { 0x000045bb, 0x00000004 },
1520 { 0x000080ba, 0x00000008 },
1521 { 0x03c00830, 0x00000004 },
1522 { 0x4200e000, 0000000000 },
1523 { 0x0000a000, 0x00000004 },
1524 { 0x200045e0, 0x00000004 },
1525 { 0x0000e5e1, 0000000000 },
1526 { 0x00000001, 0000000000 },
1527 { 0x000700c8, 0x00000004 },
1528 { 0x0800e394, 0000000000 },
1529 { 0000000000, 0000000000 },
1530 { 0x0000e8c4, 0x00000004 },
1531 { 0x0000e8c5, 0x00000004 },
1532 { 0x0000e8c6, 0x00000004 },
1533 { 0x0000e928, 0x00000004 },
1534 { 0x0000e929, 0x00000004 },
1535 { 0x0000e92a, 0x00000004 },
1536 { 0x000000cc, 0x00000008 },
1537 { 0x0000e928, 0x00000004 },
1538 { 0x0000e929, 0x00000004 },
1539 { 0x0000e92a, 0x00000004 },
1540 { 0x000000d3, 0x00000008 },
1541 { 0x02c02000, 0x00000004 },
1542 { 0x00060000, 0x00000004 },
1543 { 0x000000db, 0x00000034 },
1544 { 0x000000d8, 0x00000008 },
1545 { 0x00008000, 0x00000004 },
1546 { 0xc000e000, 0000000000 },
1547 { 0x000000e1, 0x00000030 },
1548 { 0x4200e000, 0000000000 },
1549 { 0x000000e1, 0x00000030 },
1550 { 0x4000e000, 0000000000 },
1551 { 0x0025001b, 0x00000004 },
1552 { 0x00230000, 0x00000004 },
1553 { 0x00250005, 0x00000004 },
1554 { 0x000000e6, 0x00000034 },
1555 { 0000000000, 0x0000000c },
1556 { 0x00244000, 0x00000004 },
1557 { 0x080045c8, 0x00000004 },
1558 { 0x00240005, 0x00000004 },
1559 { 0x08004d0b, 0x0000000c },
1560 { 0000000000, 0000000000 },
1561 { 0000000000, 0000000000 },
1562 { 0000000000, 0000000000 },
1563 { 0000000000, 0000000000 },
1564 { 0000000000, 0000000000 },
1565 { 0000000000, 0000000000 },
1566 { 0000000000, 0000000000 },
1567 { 0000000000, 0000000000 },
1568 { 0000000000, 0000000000 },
1569 { 0000000000, 0000000000 },
1570 { 0000000000, 0000000000 },
1571 { 0000000000, 0000000000 },
1572 { 0x000c2000, 0x00000004 },
1573 { 0x001d0018, 0x00000004 },
1574 { 0x001a0001, 0x00000004 },
1575 { 0x000000fb, 0x00000034 },
1576 { 0x0000004a, 0x00000008 },
1577 { 0x0500a04a, 0x00000008 },
1578 { 0000000000, 0000000000 },
1579 { 0000000000, 0000000000 },
1580 { 0000000000, 0000000000 },
1581 { 0000000000, 0000000000 },
1582};
1583
1584static const u32 R520_cp_microcode[][2] = {
1585 { 0x4200e000, 0000000000 },
1586 { 0x4000e000, 0000000000 },
1587 { 0x00000099, 0x00000008 },
1588 { 0x0000009d, 0x00000008 },
1589 { 0x4a554b4a, 0000000000 },
1590 { 0x4a4a4467, 0000000000 },
1591 { 0x55526f75, 0000000000 },
1592 { 0x4a7e7d65, 0000000000 },
1593 { 0xe0dae6f6, 0000000000 },
1594 { 0x4ac54a4a, 0000000000 },
1595 { 0xc8828282, 0000000000 },
1596 { 0xbf4acfc1, 0000000000 },
1597 { 0x87b04ad5, 0000000000 },
1598 { 0xb5838383, 0000000000 },
1599 { 0x4a0f85ba, 0000000000 },
1600 { 0x000ca000, 0x00000004 },
1601 { 0x000d0012, 0x00000038 },
1602 { 0x0000e8b4, 0x00000004 },
1603 { 0x000d0014, 0x00000038 },
1604 { 0x0000e8b6, 0x00000004 },
1605 { 0x000d0016, 0x00000038 },
1606 { 0x0000e854, 0x00000004 },
1607 { 0x000d0018, 0x00000038 },
1608 { 0x0000e855, 0x00000004 },
1609 { 0x000d001a, 0x00000038 },
1610 { 0x0000e856, 0x00000004 },
1611 { 0x000d001c, 0x00000038 },
1612 { 0x0000e857, 0x00000004 },
1613 { 0x000d001e, 0x00000038 },
1614 { 0x0000e824, 0x00000004 },
1615 { 0x000d0020, 0x00000038 },
1616 { 0x0000e825, 0x00000004 },
1617 { 0x000d0022, 0x00000038 },
1618 { 0x0000e830, 0x00000004 },
1619 { 0x000d0024, 0x00000038 },
1620 { 0x0000f0c0, 0x00000004 },
1621 { 0x000d0026, 0x00000038 },
1622 { 0x0000f0c1, 0x00000004 },
1623 { 0x000d0028, 0x00000038 },
1624 { 0x0000e000, 0x00000004 },
1625 { 0x000d002a, 0x00000038 },
1626 { 0x0000e000, 0x00000004 },
1627 { 0x000d002c, 0x00000038 },
1628 { 0x0000e000, 0x00000004 },
1629 { 0x000d002e, 0x00000038 },
1630 { 0x0000e000, 0x00000004 },
1631 { 0x000d0030, 0x00000038 },
1632 { 0x0000e000, 0x00000004 },
1633 { 0x000d0032, 0x00000038 },
1634 { 0x0000f180, 0x00000004 },
1635 { 0x000d0034, 0x00000038 },
1636 { 0x0000f393, 0x00000004 },
1637 { 0x000d0036, 0x00000038 },
1638 { 0x0000f38a, 0x00000004 },
1639 { 0x000d0038, 0x00000038 },
1640 { 0x0000f38e, 0x00000004 },
1641 { 0x0000e821, 0x00000004 },
1642 { 0x0140a000, 0x00000004 },
1643 { 0x00000043, 0x00000018 },
1644 { 0x00cce800, 0x00000004 },
1645 { 0x001b0001, 0x00000004 },
1646 { 0x08004800, 0x00000004 },
1647 { 0x001b0001, 0x00000004 },
1648 { 0x08004800, 0x00000004 },
1649 { 0x001b0001, 0x00000004 },
1650 { 0x08004800, 0x00000004 },
1651 { 0x0000003a, 0x00000008 },
1652 { 0x0000a000, 0000000000 },
1653 { 0x2000451d, 0x00000004 },
1654 { 0x0000e580, 0x00000004 },
1655 { 0x000ce581, 0x00000004 },
1656 { 0x08004580, 0x00000004 },
1657 { 0x000ce581, 0x00000004 },
1658 { 0x00000047, 0x00000008 },
1659 { 0x0000a000, 0000000000 },
1660 { 0x000c2000, 0x00000004 },
1661 { 0x0000e50e, 0x00000004 },
1662 { 0x00032000, 0x00000004 },
1663 { 0x00022051, 0x00000028 },
1664 { 0x00000051, 0x00000024 },
1665 { 0x0800450f, 0x00000004 },
1666 { 0x0000a04b, 0x00000008 },
1667 { 0x0000e565, 0x00000004 },
1668 { 0x0000e566, 0x00000004 },
1669 { 0x00000052, 0x00000008 },
1670 { 0x03cca5b4, 0x00000004 },
1671 { 0x05432000, 0x00000004 },
1672 { 0x00022000, 0x00000004 },
1673 { 0x4ccce05e, 0x00000030 },
1674 { 0x08274565, 0x00000004 },
1675 { 0x0000005e, 0x00000030 },
1676 { 0x08004564, 0x00000004 },
1677 { 0x0000e566, 0x00000004 },
1678 { 0x00000055, 0x00000008 },
1679 { 0x00802061, 0x00000010 },
1680 { 0x00202000, 0x00000004 },
1681 { 0x001b00ff, 0x00000004 },
1682 { 0x01000064, 0x00000010 },
1683 { 0x001f2000, 0x00000004 },
1684 { 0x001c00ff, 0x00000004 },
1685 { 0000000000, 0x0000000c },
1686 { 0x00000072, 0x00000030 },
1687 { 0x00000055, 0x00000008 },
1688 { 0x0000e576, 0x00000004 },
1689 { 0x0000e577, 0x00000004 },
1690 { 0x0000e50e, 0x00000004 },
1691 { 0x0000e50f, 0x00000004 },
1692 { 0x0140a000, 0x00000004 },
1693 { 0x00000069, 0x00000018 },
1694 { 0x00c0e5f9, 0x000000c2 },
1695 { 0x00000069, 0x00000008 },
1696 { 0x0014e50e, 0x00000004 },
1697 { 0x0040e50f, 0x00000004 },
1698 { 0x00c0006c, 0x00000008 },
1699 { 0x0000e570, 0x00000004 },
1700 { 0x0000e571, 0x00000004 },
1701 { 0x0000e572, 0x0000000c },
1702 { 0x0000a000, 0x00000004 },
1703 { 0x0140a000, 0x00000004 },
1704 { 0x0000e568, 0x00000004 },
1705 { 0x000c2000, 0x00000004 },
1706 { 0x00000076, 0x00000018 },
1707 { 0x000b0000, 0x00000004 },
1708 { 0x18c0e562, 0x00000004 },
1709 { 0x00000078, 0x00000008 },
1710 { 0x00c00077, 0x00000008 },
1711 { 0x000700c7, 0x00000004 },
1712 { 0x00000080, 0x00000038 },
1713 { 0x0000e5bb, 0x00000004 },
1714 { 0x0000e5bc, 0000000000 },
1715 { 0x0000a000, 0x00000004 },
1716 { 0x0000e821, 0x00000004 },
1717 { 0x0000e800, 0000000000 },
1718 { 0x0000e821, 0x00000004 },
1719 { 0x0000e82e, 0000000000 },
1720 { 0x02cca000, 0x00000004 },
1721 { 0x00140000, 0x00000004 },
1722 { 0x000ce1cc, 0x00000004 },
1723 { 0x050de1cd, 0x00000004 },
1724 { 0x00400000, 0x00000004 },
1725 { 0x0000008f, 0x00000018 },
1726 { 0x00c0a000, 0x00000004 },
1727 { 0x0000008c, 0x00000008 },
1728 { 0x00000091, 0x00000020 },
1729 { 0x4200e000, 0000000000 },
1730 { 0x00000098, 0x00000038 },
1731 { 0x000ca000, 0x00000004 },
1732 { 0x00140000, 0x00000004 },
1733 { 0x000c2000, 0x00000004 },
1734 { 0x00160000, 0x00000004 },
1735 { 0x700ce000, 0x00000004 },
1736 { 0x00140094, 0x00000008 },
1737 { 0x4000e000, 0000000000 },
1738 { 0x02400000, 0x00000004 },
1739 { 0x400ee000, 0x00000004 },
1740 { 0x02400000, 0x00000004 },
1741 { 0x4000e000, 0000000000 },
1742 { 0x000c2000, 0x00000004 },
1743 { 0x0240e51b, 0x00000004 },
1744 { 0x0080e50a, 0x00000005 },
1745 { 0x0080e50b, 0x00000005 },
1746 { 0x00220000, 0x00000004 },
1747 { 0x000700c7, 0x00000004 },
1748 { 0x000000a4, 0x00000038 },
1749 { 0x0080e5bd, 0x00000005 },
1750 { 0x0000e5bb, 0x00000005 },
1751 { 0x0080e5bc, 0x00000005 },
1752 { 0x00210000, 0x00000004 },
1753 { 0x02800000, 0x00000004 },
1754 { 0x00c000ab, 0x00000018 },
1755 { 0x4180e000, 0x00000040 },
1756 { 0x000000ad, 0x00000024 },
1757 { 0x01000000, 0x0000000c },
1758 { 0x0100e51d, 0x0000000c },
1759 { 0x000045bb, 0x00000004 },
1760 { 0x000080a7, 0x00000008 },
1761 { 0x0000f3ce, 0x00000004 },
1762 { 0x0140a000, 0x00000004 },
1763 { 0x00cc2000, 0x00000004 },
1764 { 0x08c053cf, 0x00000040 },
1765 { 0x00008000, 0000000000 },
1766 { 0x0000f3d2, 0x00000004 },
1767 { 0x0140a000, 0x00000004 },
1768 { 0x00cc2000, 0x00000004 },
1769 { 0x08c053d3, 0x00000040 },
1770 { 0x00008000, 0000000000 },
1771 { 0x0000f39d, 0x00000004 },
1772 { 0x0140a000, 0x00000004 },
1773 { 0x00cc2000, 0x00000004 },
1774 { 0x08c0539e, 0x00000040 },
1775 { 0x00008000, 0000000000 },
1776 { 0x03c00830, 0x00000004 },
1777 { 0x4200e000, 0000000000 },
1778 { 0x0000a000, 0x00000004 },
1779 { 0x200045e0, 0x00000004 },
1780 { 0x0000e5e1, 0000000000 },
1781 { 0x00000001, 0000000000 },
1782 { 0x000700c4, 0x00000004 },
1783 { 0x0800e394, 0000000000 },
1784 { 0000000000, 0000000000 },
1785 { 0x0000e8c4, 0x00000004 },
1786 { 0x0000e8c5, 0x00000004 },
1787 { 0x0000e8c6, 0x00000004 },
1788 { 0x0000e928, 0x00000004 },
1789 { 0x0000e929, 0x00000004 },
1790 { 0x0000e92a, 0x00000004 },
1791 { 0x000000c8, 0x00000008 },
1792 { 0x0000e928, 0x00000004 },
1793 { 0x0000e929, 0x00000004 },
1794 { 0x0000e92a, 0x00000004 },
1795 { 0x000000cf, 0x00000008 },
1796 { 0xdeadbeef, 0000000000 },
1797 { 0x00000116, 0000000000 },
1798 { 0x000700d3, 0x00000004 },
1799 { 0x080050e7, 0x00000004 },
1800 { 0x000700d4, 0x00000004 },
1801 { 0x0800401c, 0x00000004 },
1802 { 0x0000e01d, 0000000000 },
1803 { 0x02c02000, 0x00000004 },
1804 { 0x00060000, 0x00000004 },
1805 { 0x000000de, 0x00000034 },
1806 { 0x000000db, 0x00000008 },
1807 { 0x00008000, 0x00000004 },
1808 { 0xc000e000, 0000000000 },
1809 { 0x0000e1cc, 0x00000004 },
1810 { 0x0500e1cd, 0x00000004 },
1811 { 0x000ca000, 0x00000004 },
1812 { 0x000000e5, 0x00000034 },
1813 { 0x000000e1, 0x00000008 },
1814 { 0x0000a000, 0000000000 },
1815 { 0x0019e1cc, 0x00000004 },
1816 { 0x001b0001, 0x00000004 },
1817 { 0x0500a000, 0x00000004 },
1818 { 0x080041cd, 0x00000004 },
1819 { 0x000ca000, 0x00000004 },
1820 { 0x000000fb, 0x00000034 },
1821 { 0x0000004a, 0x00000008 },
1822 { 0000000000, 0000000000 },
1823 { 0000000000, 0000000000 },
1824 { 0000000000, 0000000000 },
1825 { 0000000000, 0000000000 },
1826 { 0000000000, 0000000000 },
1827 { 0000000000, 0000000000 },
1828 { 0000000000, 0000000000 },
1829 { 0000000000, 0000000000 },
1830 { 0000000000, 0000000000 },
1831 { 0x000c2000, 0x00000004 },
1832 { 0x001d0018, 0x00000004 },
1833 { 0x001a0001, 0x00000004 },
1834 { 0x000000fb, 0x00000034 },
1835 { 0x0000004a, 0x00000008 },
1836 { 0x0500a04a, 0x00000008 },
1837 { 0000000000, 0000000000 },
1838 { 0000000000, 0000000000 },
1839 { 0000000000, 0000000000 },
1840 { 0000000000, 0000000000 },
1841};
1842
1843
1844#endif
diff --git a/drivers/char/drm/radeon_state.c b/drivers/char/drm/radeon_state.c
index 6f75512f591..11c146b4921 100644
--- a/drivers/char/drm/radeon_state.c
+++ b/drivers/char/drm/radeon_state.c
@@ -1662,7 +1662,7 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
1662 u32 height; 1662 u32 height;
1663 int i; 1663 int i;
1664 u32 texpitch, microtile; 1664 u32 texpitch, microtile;
1665 u32 offset; 1665 u32 offset, byte_offset;
1666 RING_LOCALS; 1666 RING_LOCALS;
1667 1667
1668 if (radeon_check_and_fixup_offset(dev_priv, file_priv, &tex->offset)) { 1668 if (radeon_check_and_fixup_offset(dev_priv, file_priv, &tex->offset)) {
@@ -1727,6 +1727,13 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
1727 } else 1727 } else
1728 microtile = 0; 1728 microtile = 0;
1729 1729
1730 /* this might fail for zero-sized uploads - are those illegal? */
1731 if (!radeon_check_offset(dev_priv, tex->offset + image->height *
1732 blit_width - 1)) {
1733 DRM_ERROR("Invalid final destination offset\n");
1734 return -EINVAL;
1735 }
1736
1730 DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width); 1737 DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width);
1731 1738
1732 do { 1739 do {
@@ -1840,6 +1847,7 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
1840 } 1847 }
1841 1848
1842#undef RADEON_COPY_MT 1849#undef RADEON_COPY_MT
1850 byte_offset = (image->y & ~2047) * blit_width;
1843 buf->file_priv = file_priv; 1851 buf->file_priv = file_priv;
1844 buf->used = size; 1852 buf->used = size;
1845 offset = dev_priv->gart_buffers_offset + buf->offset; 1853 offset = dev_priv->gart_buffers_offset + buf->offset;
@@ -1854,9 +1862,9 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
1854 RADEON_DP_SRC_SOURCE_MEMORY | 1862 RADEON_DP_SRC_SOURCE_MEMORY |
1855 RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS); 1863 RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS);
1856 OUT_RING((spitch << 22) | (offset >> 10)); 1864 OUT_RING((spitch << 22) | (offset >> 10));
1857 OUT_RING((texpitch << 22) | (tex->offset >> 10)); 1865 OUT_RING((texpitch << 22) | ((tex->offset >> 10) + (byte_offset >> 10)));
1858 OUT_RING(0); 1866 OUT_RING(0);
1859 OUT_RING((image->x << 16) | image->y); 1867 OUT_RING((image->x << 16) | (image->y % 2048));
1860 OUT_RING((image->width << 16) | height); 1868 OUT_RING((image->width << 16) | height);
1861 RADEON_WAIT_UNTIL_2D_IDLE(); 1869 RADEON_WAIT_UNTIL_2D_IDLE();
1862 ADVANCE_RING(); 1870 ADVANCE_RING();
@@ -3037,6 +3045,9 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil
3037 case RADEON_PARAM_FB_LOCATION: 3045 case RADEON_PARAM_FB_LOCATION:
3038 value = radeon_read_fb_location(dev_priv); 3046 value = radeon_read_fb_location(dev_priv);
3039 break; 3047 break;
3048 case RADEON_PARAM_NUM_GB_PIPES:
3049 value = dev_priv->num_gb_pipes;
3050 break;
3040 default: 3051 default:
3041 DRM_DEBUG("Invalid parameter %d\n", param->param); 3052 DRM_DEBUG("Invalid parameter %d\n", param->param);
3042 return -EINVAL; 3053 return -EINVAL;
diff --git a/drivers/char/tty_ioctl.c b/drivers/char/tty_ioctl.c
index b1a757a5ee2..8f81139d619 100644
--- a/drivers/char/tty_ioctl.c
+++ b/drivers/char/tty_ioctl.c
@@ -981,16 +981,9 @@ EXPORT_SYMBOL_GPL(tty_perform_flush);
981int n_tty_ioctl(struct tty_struct *tty, struct file *file, 981int n_tty_ioctl(struct tty_struct *tty, struct file *file,
982 unsigned int cmd, unsigned long arg) 982 unsigned int cmd, unsigned long arg)
983{ 983{
984 struct tty_struct *real_tty;
985 unsigned long flags; 984 unsigned long flags;
986 int retval; 985 int retval;
987 986
988 if (tty->driver->type == TTY_DRIVER_TYPE_PTY &&
989 tty->driver->subtype == PTY_TYPE_MASTER)
990 real_tty = tty->link;
991 else
992 real_tty = tty;
993
994 switch (cmd) { 987 switch (cmd) {
995 case TCXONC: 988 case TCXONC:
996 retval = tty_check_change(tty); 989 retval = tty_check_change(tty);
diff --git a/drivers/firewire/Kconfig b/drivers/firewire/Kconfig
index fb4d391810b..76f26710fc1 100644
--- a/drivers/firewire/Kconfig
+++ b/drivers/firewire/Kconfig
@@ -1,28 +1,26 @@
1comment "An alternative FireWire stack is available with EXPERIMENTAL=y" 1comment "A new alternative FireWire stack is available with EXPERIMENTAL=y"
2 depends on EXPERIMENTAL=n 2 depends on EXPERIMENTAL=n
3 3
4comment "Enable only one of the two stacks, unless you know what you are doing"
5 depends on EXPERIMENTAL
6
4config FIREWIRE 7config FIREWIRE
5 tristate "IEEE 1394 (FireWire) support - alternative stack, EXPERIMENTAL" 8 tristate "New FireWire stack, EXPERIMENTAL"
6 depends on EXPERIMENTAL 9 depends on EXPERIMENTAL
7 select CRC_ITU_T 10 select CRC_ITU_T
8 help 11 help
9 This is the "Juju" FireWire stack, a new alternative implementation 12 This is the "Juju" FireWire stack, a new alternative implementation
10 designed for robustness and simplicity. You can build either this 13 designed for robustness and simplicity. You can build either this
11 stack, or the classic stack (the ieee1394 driver, ohci1394 etc.) 14 stack, or the old stack (the ieee1394 driver, ohci1394 etc.) or both.
12 or both. Please read http://wiki.linux1394.org/JujuMigration before 15 Please read http://wiki.linux1394.org/JujuMigration before you
13 you enable the new stack. 16 enable the new stack.
14 17
15 To compile this driver as a module, say M here: the module will be 18 To compile this driver as a module, say M here: the module will be
16 called firewire-core. It functionally replaces ieee1394, raw1394, 19 called firewire-core. It functionally replaces ieee1394, raw1394,
17 and video1394. 20 and video1394.
18 21
19 NOTE:
20
21 You should only build ONE of the stacks, unless you REALLY know what
22 you are doing.
23
24config FIREWIRE_OHCI 22config FIREWIRE_OHCI
25 tristate "Support for OHCI FireWire host controllers" 23 tristate "OHCI-1394 controllers"
26 depends on PCI && FIREWIRE 24 depends on PCI && FIREWIRE
27 help 25 help
28 Enable this driver if you have a FireWire controller based 26 Enable this driver if you have a FireWire controller based
@@ -33,12 +31,12 @@ config FIREWIRE_OHCI
33 called firewire-ohci. It replaces ohci1394 of the classic IEEE 1394 31 called firewire-ohci. It replaces ohci1394 of the classic IEEE 1394
34 stack. 32 stack.
35 33
36 NOTE: 34 NOTE:
37 35
38 You should only build ohci1394 or firewire-ohci, but not both. 36 You should only build either firewire-ohci or the old ohci1394 driver,
39 If you nevertheless want to install both, you should configure them 37 but not both. If you nevertheless want to install both, you should
40 only as modules and blacklist the driver(s) which you don't want to 38 configure them only as modules and blacklist the driver(s) which you
41 have auto-loaded. Add either 39 don't want to have auto-loaded. Add either
42 40
43 blacklist firewire-ohci 41 blacklist firewire-ohci
44 or 42 or
@@ -60,7 +58,7 @@ config FIREWIRE_OHCI_DEBUG
60 default y 58 default y
61 59
62config FIREWIRE_SBP2 60config FIREWIRE_SBP2
63 tristate "Support for storage devices (SBP-2 protocol driver)" 61 tristate "Storage devices (SBP-2 protocol)"
64 depends on FIREWIRE && SCSI 62 depends on FIREWIRE && SCSI
65 help 63 help
66 This option enables you to use SBP-2 devices connected to a 64 This option enables you to use SBP-2 devices connected to a
diff --git a/drivers/firewire/fw-cdev.c b/drivers/firewire/fw-cdev.c
index dda14015e87..c639915fc3c 100644
--- a/drivers/firewire/fw-cdev.c
+++ b/drivers/firewire/fw-cdev.c
@@ -205,6 +205,7 @@ fw_device_op_read(struct file *file,
205 return dequeue_event(client, buffer, count); 205 return dequeue_event(client, buffer, count);
206} 206}
207 207
208/* caller must hold card->lock so that node pointers can be dereferenced here */
208static void 209static void
209fill_bus_reset_event(struct fw_cdev_event_bus_reset *event, 210fill_bus_reset_event(struct fw_cdev_event_bus_reset *event,
210 struct client *client) 211 struct client *client)
@@ -214,7 +215,6 @@ fill_bus_reset_event(struct fw_cdev_event_bus_reset *event,
214 event->closure = client->bus_reset_closure; 215 event->closure = client->bus_reset_closure;
215 event->type = FW_CDEV_EVENT_BUS_RESET; 216 event->type = FW_CDEV_EVENT_BUS_RESET;
216 event->generation = client->device->generation; 217 event->generation = client->device->generation;
217 smp_rmb(); /* node_id must not be older than generation */
218 event->node_id = client->device->node_id; 218 event->node_id = client->device->node_id;
219 event->local_node_id = card->local_node->node_id; 219 event->local_node_id = card->local_node->node_id;
220 event->bm_node_id = 0; /* FIXME: We don't track the BM. */ 220 event->bm_node_id = 0; /* FIXME: We don't track the BM. */
@@ -274,6 +274,7 @@ static int ioctl_get_info(struct client *client, void *buffer)
274{ 274{
275 struct fw_cdev_get_info *get_info = buffer; 275 struct fw_cdev_get_info *get_info = buffer;
276 struct fw_cdev_event_bus_reset bus_reset; 276 struct fw_cdev_event_bus_reset bus_reset;
277 struct fw_card *card = client->device->card;
277 unsigned long ret = 0; 278 unsigned long ret = 0;
278 279
279 client->version = get_info->version; 280 client->version = get_info->version;
@@ -299,13 +300,17 @@ static int ioctl_get_info(struct client *client, void *buffer)
299 client->bus_reset_closure = get_info->bus_reset_closure; 300 client->bus_reset_closure = get_info->bus_reset_closure;
300 if (get_info->bus_reset != 0) { 301 if (get_info->bus_reset != 0) {
301 void __user *uptr = u64_to_uptr(get_info->bus_reset); 302 void __user *uptr = u64_to_uptr(get_info->bus_reset);
303 unsigned long flags;
302 304
305 spin_lock_irqsave(&card->lock, flags);
303 fill_bus_reset_event(&bus_reset, client); 306 fill_bus_reset_event(&bus_reset, client);
307 spin_unlock_irqrestore(&card->lock, flags);
308
304 if (copy_to_user(uptr, &bus_reset, sizeof(bus_reset))) 309 if (copy_to_user(uptr, &bus_reset, sizeof(bus_reset)))
305 return -EFAULT; 310 return -EFAULT;
306 } 311 }
307 312
308 get_info->card = client->device->card->index; 313 get_info->card = card->index;
309 314
310 return 0; 315 return 0;
311} 316}
diff --git a/drivers/firewire/fw-ohci.c b/drivers/firewire/fw-ohci.c
index 4f02c55f13e..0b66306af47 100644
--- a/drivers/firewire/fw-ohci.c
+++ b/drivers/firewire/fw-ohci.c
@@ -265,27 +265,25 @@ static void log_irqs(u32 evt)
265 !(evt & OHCI1394_busReset)) 265 !(evt & OHCI1394_busReset))
266 return; 266 return;
267 267
268 printk(KERN_DEBUG KBUILD_MODNAME ": IRQ " 268 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
269 "%08x%s%s%s%s%s%s%s%s%s%s%s%s%s\n", 269 evt & OHCI1394_selfIDComplete ? " selfID" : "",
270 evt, 270 evt & OHCI1394_RQPkt ? " AR_req" : "",
271 evt & OHCI1394_selfIDComplete ? " selfID" : "", 271 evt & OHCI1394_RSPkt ? " AR_resp" : "",
272 evt & OHCI1394_RQPkt ? " AR_req" : "", 272 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
273 evt & OHCI1394_RSPkt ? " AR_resp" : "", 273 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
274 evt & OHCI1394_reqTxComplete ? " AT_req" : "", 274 evt & OHCI1394_isochRx ? " IR" : "",
275 evt & OHCI1394_respTxComplete ? " AT_resp" : "", 275 evt & OHCI1394_isochTx ? " IT" : "",
276 evt & OHCI1394_isochRx ? " IR" : "", 276 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
277 evt & OHCI1394_isochTx ? " IT" : "", 277 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
278 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "", 278 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
279 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "", 279 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
280 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "", 280 evt & OHCI1394_busReset ? " busReset" : "",
281 evt & OHCI1394_regAccessFail ? " regAccessFail" : "", 281 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
282 evt & OHCI1394_busReset ? " busReset" : "", 282 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
283 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt | 283 OHCI1394_respTxComplete | OHCI1394_isochRx |
284 OHCI1394_RSPkt | OHCI1394_reqTxComplete | 284 OHCI1394_isochTx | OHCI1394_postedWriteErr |
285 OHCI1394_respTxComplete | OHCI1394_isochRx | 285 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
286 OHCI1394_isochTx | OHCI1394_postedWriteErr | 286 OHCI1394_regAccessFail | OHCI1394_busReset)
287 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
288 OHCI1394_regAccessFail | OHCI1394_busReset)
289 ? " ?" : ""); 287 ? " ?" : "");
290} 288}
291 289
@@ -308,23 +306,22 @@ static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
308 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS))) 306 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
309 return; 307 return;
310 308
311 printk(KERN_DEBUG KBUILD_MODNAME ": %d selfIDs, generation %d, " 309 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
312 "local node ID %04x\n", self_id_count, generation, node_id); 310 self_id_count, generation, node_id);
313 311
314 for (; self_id_count--; ++s) 312 for (; self_id_count--; ++s)
315 if ((*s & 1 << 23) == 0) 313 if ((*s & 1 << 23) == 0)
316 printk(KERN_DEBUG "selfID 0: %08x, phy %d [%c%c%c] " 314 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
317 "%s gc=%d %s %s%s%s\n", 315 "%s gc=%d %s %s%s%s\n",
318 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2), 316 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
319 speed[*s >> 14 & 3], *s >> 16 & 63, 317 speed[*s >> 14 & 3], *s >> 16 & 63,
320 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "", 318 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
321 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : ""); 319 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
322 else 320 else
323 printk(KERN_DEBUG "selfID n: %08x, phy %d " 321 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
324 "[%c%c%c%c%c%c%c%c]\n", 322 *s, *s >> 24 & 63,
325 *s, *s >> 24 & 63, 323 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
326 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10), 324 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
327 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
328} 325}
329 326
330static const char *evts[] = { 327static const char *evts[] = {
@@ -373,15 +370,14 @@ static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
373 evt = 0x1f; 370 evt = 0x1f;
374 371
375 if (evt == OHCI1394_evt_bus_reset) { 372 if (evt == OHCI1394_evt_bus_reset) {
376 printk(KERN_DEBUG "A%c evt_bus_reset, generation %d\n", 373 fw_notify("A%c evt_bus_reset, generation %d\n",
377 dir, (header[2] >> 16) & 0xff); 374 dir, (header[2] >> 16) & 0xff);
378 return; 375 return;
379 } 376 }
380 377
381 if (header[0] == ~header[1]) { 378 if (header[0] == ~header[1]) {
382 printk(KERN_DEBUG "A%c %s, %s, %08x\n", 379 fw_notify("A%c %s, %s, %08x\n",
383 dir, evts[evt], phys[header[0] >> 30 & 0x3], 380 dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
384 header[0]);
385 return; 381 return;
386 } 382 }
387 383
@@ -400,24 +396,23 @@ static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
400 396
401 switch (tcode) { 397 switch (tcode) {
402 case 0xe: case 0xa: 398 case 0xe: case 0xa:
403 printk(KERN_DEBUG "A%c %s, %s\n", 399 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
404 dir, evts[evt], tcodes[tcode]);
405 break; 400 break;
406 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9: 401 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
407 printk(KERN_DEBUG "A%c spd %x tl %02x, " 402 fw_notify("A%c spd %x tl %02x, "
408 "%04x -> %04x, %s, " 403 "%04x -> %04x, %s, "
409 "%s, %04x%08x%s\n", 404 "%s, %04x%08x%s\n",
410 dir, speed, header[0] >> 10 & 0x3f, 405 dir, speed, header[0] >> 10 & 0x3f,
411 header[1] >> 16, header[0] >> 16, evts[evt], 406 header[1] >> 16, header[0] >> 16, evts[evt],
412 tcodes[tcode], header[1] & 0xffff, header[2], specific); 407 tcodes[tcode], header[1] & 0xffff, header[2], specific);
413 break; 408 break;
414 default: 409 default:
415 printk(KERN_DEBUG "A%c spd %x tl %02x, " 410 fw_notify("A%c spd %x tl %02x, "
416 "%04x -> %04x, %s, " 411 "%04x -> %04x, %s, "
417 "%s%s\n", 412 "%s%s\n",
418 dir, speed, header[0] >> 10 & 0x3f, 413 dir, speed, header[0] >> 10 & 0x3f,
419 header[1] >> 16, header[0] >> 16, evts[evt], 414 header[1] >> 16, header[0] >> 16, evts[evt],
420 tcodes[tcode], specific); 415 tcodes[tcode], specific);
421 } 416 }
422} 417}
423 418
@@ -548,6 +543,11 @@ static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
548 p.header_length = 12; 543 p.header_length = 12;
549 p.payload_length = 0; 544 p.payload_length = 0;
550 break; 545 break;
546
547 default:
548 /* FIXME: Stop context, discard everything, and restart? */
549 p.header_length = 0;
550 p.payload_length = 0;
551 } 551 }
552 552
553 p.payload = (void *) buffer + p.header_length; 553 p.payload = (void *) buffer + p.header_length;
@@ -1468,6 +1468,9 @@ static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
1468 reg_write(ohci, OHCI1394_HCControlClear, 1468 reg_write(ohci, OHCI1394_HCControlClear,
1469 OHCI1394_HCControl_noByteSwapData); 1469 OHCI1394_HCControl_noByteSwapData);
1470 1470
1471 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1472 reg_write(ohci, OHCI1394_LinkControlClear,
1473 OHCI1394_LinkControl_rcvPhyPkt);
1471 reg_write(ohci, OHCI1394_LinkControlSet, 1474 reg_write(ohci, OHCI1394_LinkControlSet,
1472 OHCI1394_LinkControl_rcvSelfID | 1475 OHCI1394_LinkControl_rcvSelfID |
1473 OHCI1394_LinkControl_cycleTimerEnable | 1476 OHCI1394_LinkControl_cycleTimerEnable |
@@ -1481,7 +1484,6 @@ static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
1481 ar_context_run(&ohci->ar_request_ctx); 1484 ar_context_run(&ohci->ar_request_ctx);
1482 ar_context_run(&ohci->ar_response_ctx); 1485 ar_context_run(&ohci->ar_response_ctx);
1483 1486
1484 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1485 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000); 1487 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1486 reg_write(ohci, OHCI1394_IntEventClear, ~0); 1488 reg_write(ohci, OHCI1394_IntEventClear, ~0);
1487 reg_write(ohci, OHCI1394_IntMaskClear, ~0); 1489 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
diff --git a/drivers/firewire/fw-transaction.c b/drivers/firewire/fw-transaction.c
index ccf0e4cf108..03ae8a77c47 100644
--- a/drivers/firewire/fw-transaction.c
+++ b/drivers/firewire/fw-transaction.c
@@ -20,6 +20,7 @@
20 20
21#include <linux/completion.h> 21#include <linux/completion.h>
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/kref.h>
23#include <linux/module.h> 24#include <linux/module.h>
24#include <linux/init.h> 25#include <linux/init.h>
25#include <linux/interrupt.h> 26#include <linux/interrupt.h>
@@ -297,37 +298,55 @@ EXPORT_SYMBOL(fw_send_request);
297struct fw_phy_packet { 298struct fw_phy_packet {
298 struct fw_packet packet; 299 struct fw_packet packet;
299 struct completion done; 300 struct completion done;
301 struct kref kref;
300}; 302};
301 303
302static void 304static void phy_packet_release(struct kref *kref)
303transmit_phy_packet_callback(struct fw_packet *packet, 305{
304 struct fw_card *card, int status) 306 struct fw_phy_packet *p =
307 container_of(kref, struct fw_phy_packet, kref);
308 kfree(p);
309}
310
311static void transmit_phy_packet_callback(struct fw_packet *packet,
312 struct fw_card *card, int status)
305{ 313{
306 struct fw_phy_packet *p = 314 struct fw_phy_packet *p =
307 container_of(packet, struct fw_phy_packet, packet); 315 container_of(packet, struct fw_phy_packet, packet);
308 316
309 complete(&p->done); 317 complete(&p->done);
318 kref_put(&p->kref, phy_packet_release);
310} 319}
311 320
312void fw_send_phy_config(struct fw_card *card, 321void fw_send_phy_config(struct fw_card *card,
313 int node_id, int generation, int gap_count) 322 int node_id, int generation, int gap_count)
314{ 323{
315 struct fw_phy_packet p; 324 struct fw_phy_packet *p;
325 long timeout = DIV_ROUND_UP(HZ, 10);
316 u32 data = PHY_IDENTIFIER(PHY_PACKET_CONFIG) | 326 u32 data = PHY_IDENTIFIER(PHY_PACKET_CONFIG) |
317 PHY_CONFIG_ROOT_ID(node_id) | 327 PHY_CONFIG_ROOT_ID(node_id) |
318 PHY_CONFIG_GAP_COUNT(gap_count); 328 PHY_CONFIG_GAP_COUNT(gap_count);
319 329
320 p.packet.header[0] = data; 330 p = kmalloc(sizeof(*p), GFP_KERNEL);
321 p.packet.header[1] = ~data; 331 if (p == NULL)
322 p.packet.header_length = 8; 332 return;
323 p.packet.payload_length = 0; 333
324 p.packet.speed = SCODE_100; 334 p->packet.header[0] = data;
325 p.packet.generation = generation; 335 p->packet.header[1] = ~data;
326 p.packet.callback = transmit_phy_packet_callback; 336 p->packet.header_length = 8;
327 init_completion(&p.done); 337 p->packet.payload_length = 0;
328 338 p->packet.speed = SCODE_100;
329 card->driver->send_request(card, &p.packet); 339 p->packet.generation = generation;
330 wait_for_completion(&p.done); 340 p->packet.callback = transmit_phy_packet_callback;
341 init_completion(&p->done);
342 kref_set(&p->kref, 2);
343
344 card->driver->send_request(card, &p->packet);
345 timeout = wait_for_completion_timeout(&p->done, timeout);
346 kref_put(&p->kref, phy_packet_release);
347
348 /* will leak p if the callback is never executed */
349 WARN_ON(timeout == 0);
331} 350}
332 351
333void fw_flush_transactions(struct fw_card *card) 352void fw_flush_transactions(struct fw_card *card)
@@ -572,7 +591,8 @@ allocate_request(struct fw_packet *p)
572 break; 591 break;
573 592
574 default: 593 default:
575 BUG(); 594 fw_error("ERROR - corrupt request received - %08x %08x %08x\n",
595 p->header[0], p->header[1], p->header[2]);
576 return NULL; 596 return NULL;
577 } 597 }
578 598
diff --git a/drivers/hwmon/abituguru3.c b/drivers/hwmon/abituguru3.c
index ed33fddc4de..f00f497b9ca 100644
--- a/drivers/hwmon/abituguru3.c
+++ b/drivers/hwmon/abituguru3.c
@@ -30,6 +30,7 @@
30#include <linux/platform_device.h> 30#include <linux/platform_device.h>
31#include <linux/hwmon.h> 31#include <linux/hwmon.h>
32#include <linux/hwmon-sysfs.h> 32#include <linux/hwmon-sysfs.h>
33#include <linux/dmi.h>
33#include <asm/io.h> 34#include <asm/io.h>
34 35
35/* uGuru3 bank addresses */ 36/* uGuru3 bank addresses */
@@ -323,7 +324,7 @@ static const struct abituguru3_motherboard_info abituguru3_motherboards[] = {
323 { "AUX1 Fan", 36, 2, 60, 1, 0 }, 324 { "AUX1 Fan", 36, 2, 60, 1, 0 },
324 { NULL, 0, 0, 0, 0, 0 } } 325 { NULL, 0, 0, 0, 0, 0 } }
325 }, 326 },
326 { 0x0013, "unknown", { 327 { 0x0013, "Abit AW8D", {
327 { "CPU Core", 0, 0, 10, 1, 0 }, 328 { "CPU Core", 0, 0, 10, 1, 0 },
328 { "DDR", 1, 0, 10, 1, 0 }, 329 { "DDR", 1, 0, 10, 1, 0 },
329 { "DDR VTT", 2, 0, 10, 1, 0 }, 330 { "DDR VTT", 2, 0, 10, 1, 0 },
@@ -349,6 +350,7 @@ static const struct abituguru3_motherboard_info abituguru3_motherboards[] = {
349 { "AUX2 Fan", 36, 2, 60, 1, 0 }, 350 { "AUX2 Fan", 36, 2, 60, 1, 0 },
350 { "AUX3 Fan", 37, 2, 60, 1, 0 }, 351 { "AUX3 Fan", 37, 2, 60, 1, 0 },
351 { "AUX4 Fan", 38, 2, 60, 1, 0 }, 352 { "AUX4 Fan", 38, 2, 60, 1, 0 },
353 { "AUX5 Fan", 39, 2, 60, 1, 0 },
352 { NULL, 0, 0, 0, 0, 0 } } 354 { NULL, 0, 0, 0, 0, 0 } }
353 }, 355 },
354 { 0x0014, "Abit AB9 Pro", { 356 { 0x0014, "Abit AB9 Pro", {
@@ -1111,11 +1113,12 @@ static int __init abituguru3_detect(void)
1111{ 1113{
1112 /* See if there is an uguru3 there. An idle uGuru3 will hold 0x00 or 1114 /* See if there is an uguru3 there. An idle uGuru3 will hold 0x00 or
1113 0x08 at DATA and 0xAC at CMD. Sometimes the uGuru3 will hold 0x05 1115 0x08 at DATA and 0xAC at CMD. Sometimes the uGuru3 will hold 0x05
1114 at CMD instead, why is unknown. So we test for 0x05 too. */ 1116 or 0x55 at CMD instead, why is unknown. */
1115 u8 data_val = inb_p(ABIT_UGURU3_BASE + ABIT_UGURU3_DATA); 1117 u8 data_val = inb_p(ABIT_UGURU3_BASE + ABIT_UGURU3_DATA);
1116 u8 cmd_val = inb_p(ABIT_UGURU3_BASE + ABIT_UGURU3_CMD); 1118 u8 cmd_val = inb_p(ABIT_UGURU3_BASE + ABIT_UGURU3_CMD);
1117 if (((data_val == 0x00) || (data_val == 0x08)) && 1119 if (((data_val == 0x00) || (data_val == 0x08)) &&
1118 ((cmd_val == 0xAC) || (cmd_val == 0x05))) 1120 ((cmd_val == 0xAC) || (cmd_val == 0x05) ||
1121 (cmd_val == 0x55)))
1119 return ABIT_UGURU3_BASE; 1122 return ABIT_UGURU3_BASE;
1120 1123
1121 ABIT_UGURU3_DEBUG("no Abit uGuru3 found, data = 0x%02X, cmd = " 1124 ABIT_UGURU3_DEBUG("no Abit uGuru3 found, data = 0x%02X, cmd = "
@@ -1138,6 +1141,15 @@ static int __init abituguru3_init(void)
1138 int address, err; 1141 int address, err;
1139 struct resource res = { .flags = IORESOURCE_IO }; 1142 struct resource res = { .flags = IORESOURCE_IO };
1140 1143
1144#ifdef CONFIG_DMI
1145 const char *board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR);
1146
1147 /* safety check, refuse to load on non Abit motherboards */
1148 if (!force && (!board_vendor ||
1149 strcmp(board_vendor, "http://www.abit.com.tw/")))
1150 return -ENODEV;
1151#endif
1152
1141 address = abituguru3_detect(); 1153 address = abituguru3_detect();
1142 if (address < 0) 1154 if (address < 0)
1143 return address; 1155 return address;
diff --git a/drivers/hwmon/adt7473.c b/drivers/hwmon/adt7473.c
index c1009d6f979..93dbf5e7ff8 100644
--- a/drivers/hwmon/adt7473.c
+++ b/drivers/hwmon/adt7473.c
@@ -309,6 +309,9 @@ no_sensor_update:
309 ADT7473_REG_PWM_BHVR(i)); 309 ADT7473_REG_PWM_BHVR(i));
310 } 310 }
311 311
312 i = i2c_smbus_read_byte_data(client, ADT7473_REG_CFG4);
313 data->max_duty_at_overheat = !!(i & ADT7473_CFG4_MAX_DUTY_AT_OVT);
314
312 data->limits_last_updated = local_jiffies; 315 data->limits_last_updated = local_jiffies;
313 data->limits_valid = 1; 316 data->limits_valid = 1;
314 317
diff --git a/drivers/hwmon/lm75.c b/drivers/hwmon/lm75.c
index fa769690515..de698dc7302 100644
--- a/drivers/hwmon/lm75.c
+++ b/drivers/hwmon/lm75.c
@@ -251,10 +251,13 @@ static int lm75_detach_client(struct i2c_client *client)
251 the SMBus standard. */ 251 the SMBus standard. */
252static int lm75_read_value(struct i2c_client *client, u8 reg) 252static int lm75_read_value(struct i2c_client *client, u8 reg)
253{ 253{
254 int value;
255
254 if (reg == LM75_REG_CONF) 256 if (reg == LM75_REG_CONF)
255 return i2c_smbus_read_byte_data(client, reg); 257 return i2c_smbus_read_byte_data(client, reg);
256 else 258
257 return swab16(i2c_smbus_read_word_data(client, reg)); 259 value = i2c_smbus_read_word_data(client, reg);
260 return (value < 0) ? value : swab16(value);
258} 261}
259 262
260static int lm75_write_value(struct i2c_client *client, u8 reg, u16 value) 263static int lm75_write_value(struct i2c_client *client, u8 reg, u16 value)
@@ -287,9 +290,16 @@ static struct lm75_data *lm75_update_device(struct device *dev)
287 int i; 290 int i;
288 dev_dbg(&client->dev, "Starting lm75 update\n"); 291 dev_dbg(&client->dev, "Starting lm75 update\n");
289 292
290 for (i = 0; i < ARRAY_SIZE(data->temp); i++) 293 for (i = 0; i < ARRAY_SIZE(data->temp); i++) {
291 data->temp[i] = lm75_read_value(client, 294 int status;
292 LM75_REG_TEMP[i]); 295
296 status = lm75_read_value(client, LM75_REG_TEMP[i]);
297 if (status < 0)
298 dev_dbg(&client->dev, "reg %d, err %d\n",
299 LM75_REG_TEMP[i], status);
300 else
301 data->temp[i] = status;
302 }
293 data->last_updated = jiffies; 303 data->last_updated = jiffies;
294 data->valid = 1; 304 data->valid = 1;
295 } 305 }
diff --git a/drivers/hwmon/lm85.c b/drivers/hwmon/lm85.c
index 182fe6a5605..ee5eca1c192 100644
--- a/drivers/hwmon/lm85.c
+++ b/drivers/hwmon/lm85.c
@@ -192,23 +192,20 @@ static int RANGE_TO_REG( int range )
192{ 192{
193 int i; 193 int i;
194 194
195 if ( range < lm85_range_map[0] ) { 195 if (range >= lm85_range_map[15])
196 return 0 ;
197 } else if ( range > lm85_range_map[15] ) {
198 return 15 ; 196 return 15 ;
199 } else { /* find closest match */ 197
200 for ( i = 14 ; i >= 0 ; --i ) { 198 /* Find the closest match */
201 if ( range > lm85_range_map[i] ) { /* range bracketed */ 199 for (i = 14; i >= 0; --i) {
202 if ((lm85_range_map[i+1] - range) < 200 if (range >= lm85_range_map[i]) {
203 (range - lm85_range_map[i])) { 201 if ((lm85_range_map[i + 1] - range) <
204 i++; 202 (range - lm85_range_map[i]))
205 break; 203 return i + 1;
206 } 204 return i;
207 break;
208 }
209 } 205 }
210 } 206 }
211 return( i & 0x0f ); 207
208 return 0;
212} 209}
213#define RANGE_FROM_REG(val) (lm85_range_map[(val)&0x0f]) 210#define RANGE_FROM_REG(val) (lm85_range_map[(val)&0x0f])
214 211
diff --git a/drivers/ide/Kconfig b/drivers/ide/Kconfig
index 1607536ff5f..8e07de23d22 100644
--- a/drivers/ide/Kconfig
+++ b/drivers/ide/Kconfig
@@ -823,13 +823,6 @@ config BLK_DEV_IDE_RAPIDE
823 Say Y here if you want to support the Yellowstone RapIDE controller 823 Say Y here if you want to support the Yellowstone RapIDE controller
824 manufactured for use with Acorn computers. 824 manufactured for use with Acorn computers.
825 825
826config BLK_DEV_IDE_BAST
827 tristate "Simtec BAST / Thorcom VR1000 IDE support"
828 depends on ARM && (ARCH_BAST || MACH_VR1000)
829 help
830 Say Y here if you want to support the onboard IDE channels on the
831 Simtec BAST or the Thorcom VR1000
832
833config IDE_H8300 826config IDE_H8300
834 tristate "H8300 IDE support" 827 tristate "H8300 IDE support"
835 depends on H8300 828 depends on H8300
diff --git a/drivers/ide/arm/Makefile b/drivers/ide/arm/Makefile
index 936e7b0237f..5bc26053afa 100644
--- a/drivers/ide/arm/Makefile
+++ b/drivers/ide/arm/Makefile
@@ -1,7 +1,6 @@
1 1
2obj-$(CONFIG_BLK_DEV_IDE_ICSIDE) += icside.o 2obj-$(CONFIG_BLK_DEV_IDE_ICSIDE) += icside.o
3obj-$(CONFIG_BLK_DEV_IDE_RAPIDE) += rapide.o 3obj-$(CONFIG_BLK_DEV_IDE_RAPIDE) += rapide.o
4obj-$(CONFIG_BLK_DEV_IDE_BAST) += bast-ide.o
5obj-$(CONFIG_BLK_DEV_PALMCHIP_BK3710) += palm_bk3710.o 4obj-$(CONFIG_BLK_DEV_PALMCHIP_BK3710) += palm_bk3710.o
6 5
7ifeq ($(CONFIG_IDE_ARM), m) 6ifeq ($(CONFIG_IDE_ARM), m)
diff --git a/drivers/ide/arm/bast-ide.c b/drivers/ide/arm/bast-ide.c
deleted file mode 100644
index 8e8c28104b4..00000000000
--- a/drivers/ide/arm/bast-ide.c
+++ /dev/null
@@ -1,90 +0,0 @@
1/*
2 * Copyright (c) 2003-2004 Simtec Electronics
3 * Ben Dooks <ben@simtec.co.uk>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9*/
10
11#include <linux/module.h>
12#include <linux/errno.h>
13#include <linux/ide.h>
14#include <linux/init.h>
15
16#include <asm/mach-types.h>
17
18#include <asm/io.h>
19#include <asm/irq.h>
20#include <asm/arch/map.h>
21#include <asm/arch/bast-map.h>
22#include <asm/arch/bast-irq.h>
23
24#define DRV_NAME "bast-ide"
25
26static int __init bastide_register(unsigned int base, unsigned int aux, int irq)
27{
28 ide_hwif_t *hwif;
29 hw_regs_t hw;
30 int i;
31 u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
32
33 memset(&hw, 0, sizeof(hw));
34
35 base += BAST_IDE_CS;
36 aux += BAST_IDE_CS;
37
38 for (i = 0; i <= 7; i++) {
39 hw.io_ports_array[i] = (unsigned long)base;
40 base += 0x20;
41 }
42
43 hw.io_ports.ctl_addr = aux + (6 * 0x20);
44 hw.irq = irq;
45 hw.chipset = ide_generic;
46
47 hwif = ide_find_port();
48 if (hwif == NULL)
49 goto out;
50
51 i = hwif->index;
52
53 ide_init_port_data(hwif, i);
54 ide_init_port_hw(hwif, &hw);
55 hwif->port_ops = NULL;
56
57 idx[0] = i;
58
59 ide_device_add(idx, NULL);
60out:
61 return 0;
62}
63
64static int __init bastide_init(void)
65{
66 unsigned long base = BAST_VA_IDEPRI + BAST_IDE_CS;
67
68 /* we can treat the VR1000 and the BAST the same */
69
70 if (!(machine_is_bast() || machine_is_vr1000()))
71 return 0;
72
73 printk("BAST: IDE driver, (c) 2003-2004 Simtec Electronics\n");
74
75 if (!request_mem_region(base, 0x400000, DRV_NAME)) {
76 printk(KERN_ERR "%s: resources busy\n", DRV_NAME);
77 return -EBUSY;
78 }
79
80 bastide_register(BAST_VA_IDEPRI, BAST_VA_IDEPRIAUX, IRQ_IDE0);
81 bastide_register(BAST_VA_IDESEC, BAST_VA_IDESECAUX, IRQ_IDE1);
82
83 return 0;
84}
85
86module_init(bastide_init);
87
88MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
89MODULE_LICENSE("GPL");
90MODULE_DESCRIPTION("Simtec BAST / Thorcom VR1000 IDE driver");
diff --git a/drivers/ide/arm/palm_bk3710.c b/drivers/ide/arm/palm_bk3710.c
index d024ac8fad1..cc24803fadf 100644
--- a/drivers/ide/arm/palm_bk3710.c
+++ b/drivers/ide/arm/palm_bk3710.c
@@ -353,8 +353,8 @@ static int __devinit palm_bk3710_probe(struct platform_device *pdev)
353 struct clk *clkp; 353 struct clk *clkp;
354 struct resource *mem, *irq; 354 struct resource *mem, *irq;
355 ide_hwif_t *hwif; 355 ide_hwif_t *hwif;
356 void __iomem *base; 356 unsigned long base;
357 int pribase, i; 357 int i;
358 hw_regs_t hw; 358 hw_regs_t hw;
359 u8 idx[4] = { 0xff, 0xff, 0xff, 0xff }; 359 u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
360 360
@@ -374,22 +374,27 @@ static int __devinit palm_bk3710_probe(struct platform_device *pdev)
374 printk(KERN_ERR "failed to get memory region resource\n"); 374 printk(KERN_ERR "failed to get memory region resource\n");
375 return -ENODEV; 375 return -ENODEV;
376 } 376 }
377
377 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 378 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
378 if (irq == NULL) { 379 if (irq == NULL) {
379 printk(KERN_ERR "failed to get IRQ resource\n"); 380 printk(KERN_ERR "failed to get IRQ resource\n");
380 return -ENODEV; 381 return -ENODEV;
381 } 382 }
382 383
383 base = (void *)mem->start; 384 if (request_mem_region(mem->start, mem->end - mem->start + 1,
385 "palm_bk3710") == NULL) {
386 printk(KERN_ERR "failed to request memory region\n");
387 return -EBUSY;
388 }
389
390 base = IO_ADDRESS(mem->start);
384 391
385 /* Configure the Palm Chip controller */ 392 /* Configure the Palm Chip controller */
386 palm_bk3710_chipinit(base); 393 palm_bk3710_chipinit((void __iomem *)base);
387 394
388 pribase = mem->start + IDE_PALM_ATA_PRI_REG_OFFSET;
389 for (i = 0; i < IDE_NR_PORTS - 2; i++) 395 for (i = 0; i < IDE_NR_PORTS - 2; i++)
390 hw.io_ports_array[i] = pribase + i; 396 hw.io_ports_array[i] = base + IDE_PALM_ATA_PRI_REG_OFFSET + i;
391 hw.io_ports.ctl_addr = mem->start + 397 hw.io_ports.ctl_addr = base + IDE_PALM_ATA_PRI_CTL_OFFSET;
392 IDE_PALM_ATA_PRI_CTL_OFFSET;
393 hw.irq = irq->start; 398 hw.irq = irq->start;
394 hw.chipset = ide_palm3710; 399 hw.chipset = ide_palm3710;
395 400
@@ -434,4 +439,3 @@ static int __init palm_bk3710_init(void)
434 439
435module_init(palm_bk3710_init); 440module_init(palm_bk3710_init);
436MODULE_LICENSE("GPL"); 441MODULE_LICENSE("GPL");
437
diff --git a/drivers/ide/ide-taskfile.c b/drivers/ide/ide-taskfile.c
index 0c908ca3ff7..ab545ffa154 100644
--- a/drivers/ide/ide-taskfile.c
+++ b/drivers/ide/ide-taskfile.c
@@ -225,10 +225,10 @@ static u8 wait_drive_not_busy(ide_drive_t *drive)
225 u8 stat; 225 u8 stat;
226 226
227 /* 227 /*
228 * Last sector was transfered, wait until drive is ready. 228 * Last sector was transfered, wait until device is ready. This can
229 * This can take up to 10 usec, but we will wait max 1 ms. 229 * take up to 6 ms on some ATAPI devices, so we will wait max 10 ms.
230 */ 230 */
231 for (retries = 0; retries < 100; retries++) { 231 for (retries = 0; retries < 1000; retries++) {
232 stat = ide_read_status(drive); 232 stat = ide_read_status(drive);
233 233
234 if (stat & BUSY_STAT) 234 if (stat & BUSY_STAT)
diff --git a/drivers/ide/legacy/ide-cs.c b/drivers/ide/legacy/ide-cs.c
index f633b6b3c7f..3381424d70a 100644
--- a/drivers/ide/legacy/ide-cs.c
+++ b/drivers/ide/legacy/ide-cs.c
@@ -410,6 +410,7 @@ static struct pcmcia_device_id ide_ids[] = {
410 PCMCIA_DEVICE_MANF_CARD(0x001c, 0x0001), /* Mitsubishi CFA */ 410 PCMCIA_DEVICE_MANF_CARD(0x001c, 0x0001), /* Mitsubishi CFA */
411 PCMCIA_DEVICE_MANF_CARD(0x0032, 0x0704), 411 PCMCIA_DEVICE_MANF_CARD(0x0032, 0x0704),
412 PCMCIA_DEVICE_MANF_CARD(0x0045, 0x0401), /* SanDisk CFA */ 412 PCMCIA_DEVICE_MANF_CARD(0x0045, 0x0401), /* SanDisk CFA */
413 PCMCIA_DEVICE_MANF_CARD(0x004f, 0x0000), /* Kingston */
413 PCMCIA_DEVICE_MANF_CARD(0x0098, 0x0000), /* Toshiba */ 414 PCMCIA_DEVICE_MANF_CARD(0x0098, 0x0000), /* Toshiba */
414 PCMCIA_DEVICE_MANF_CARD(0x00a4, 0x002d), 415 PCMCIA_DEVICE_MANF_CARD(0x00a4, 0x002d),
415 PCMCIA_DEVICE_MANF_CARD(0x00ce, 0x0000), /* Samsung */ 416 PCMCIA_DEVICE_MANF_CARD(0x00ce, 0x0000), /* Samsung */
@@ -439,6 +440,7 @@ static struct pcmcia_device_id ide_ids[] = {
439 PCMCIA_DEVICE_PROD_ID12("IO DATA", "PCIDE", 0x547e66dc, 0x5c5ab149), 440 PCMCIA_DEVICE_PROD_ID12("IO DATA", "PCIDE", 0x547e66dc, 0x5c5ab149),
440 PCMCIA_DEVICE_PROD_ID12("IO DATA", "PCIDEII", 0x547e66dc, 0xb3662674), 441 PCMCIA_DEVICE_PROD_ID12("IO DATA", "PCIDEII", 0x547e66dc, 0xb3662674),
441 PCMCIA_DEVICE_PROD_ID12("LOOKMEET", "CBIDE2 ", 0xe37be2b5, 0x8671043b), 442 PCMCIA_DEVICE_PROD_ID12("LOOKMEET", "CBIDE2 ", 0xe37be2b5, 0x8671043b),
443 PCMCIA_DEVICE_PROD_ID12("M-Systems", "CF300", 0x7ed2ad87, 0x7e9e78ee),
442 PCMCIA_DEVICE_PROD_ID12("M-Systems", "CF500", 0x7ed2ad87, 0x7a13045c), 444 PCMCIA_DEVICE_PROD_ID12("M-Systems", "CF500", 0x7ed2ad87, 0x7a13045c),
443 PCMCIA_DEVICE_PROD_ID2("NinjaATA-", 0xebe0bd79), 445 PCMCIA_DEVICE_PROD_ID2("NinjaATA-", 0xebe0bd79),
444 PCMCIA_DEVICE_PROD_ID12("PCMCIA", "CD-ROM", 0x281f1c5d, 0x66536591), 446 PCMCIA_DEVICE_PROD_ID12("PCMCIA", "CD-ROM", 0x281f1c5d, 0x66536591),
@@ -449,6 +451,7 @@ static struct pcmcia_device_id ide_ids[] = {
449 PCMCIA_DEVICE_PROD_ID12("SMI VENDOR", "SMI PRODUCT", 0x30896c92, 0x703cc5f6), 451 PCMCIA_DEVICE_PROD_ID12("SMI VENDOR", "SMI PRODUCT", 0x30896c92, 0x703cc5f6),
450 PCMCIA_DEVICE_PROD_ID12("TOSHIBA", "MK2001MPL", 0xb4585a1a, 0x3489e003), 452 PCMCIA_DEVICE_PROD_ID12("TOSHIBA", "MK2001MPL", 0xb4585a1a, 0x3489e003),
451 PCMCIA_DEVICE_PROD_ID1("TRANSCEND 512M ", 0xd0909443), 453 PCMCIA_DEVICE_PROD_ID1("TRANSCEND 512M ", 0xd0909443),
454 PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS1GCF45", 0x709b1bf1, 0xf68b6f32),
452 PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS1GCF80", 0x709b1bf1, 0x2a54d4b1), 455 PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS1GCF80", 0x709b1bf1, 0x2a54d4b1),
453 PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS2GCF120", 0x709b1bf1, 0x969aa4f2), 456 PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS2GCF120", 0x709b1bf1, 0x969aa4f2),
454 PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS4GCF120", 0x709b1bf1, 0xf54a91c8), 457 PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS4GCF120", 0x709b1bf1, 0xf54a91c8),
diff --git a/drivers/ieee1394/Kconfig b/drivers/ieee1394/Kconfig
index 545663ef820..95f45f9b8e5 100644
--- a/drivers/ieee1394/Kconfig
+++ b/drivers/ieee1394/Kconfig
@@ -4,7 +4,7 @@ menu "IEEE 1394 (FireWire) support"
4source "drivers/firewire/Kconfig" 4source "drivers/firewire/Kconfig"
5 5
6config IEEE1394 6config IEEE1394
7 tristate "IEEE 1394 (FireWire) support" 7 tristate "Stable FireWire stack"
8 depends on PCI || BROKEN 8 depends on PCI || BROKEN
9 help 9 help
10 IEEE 1394 describes a high performance serial bus, which is also 10 IEEE 1394 describes a high performance serial bus, which is also
@@ -19,30 +19,45 @@ config IEEE1394
19 To compile this driver as a module, say M here: the 19 To compile this driver as a module, say M here: the
20 module will be called ieee1394. 20 module will be called ieee1394.
21 21
22comment "Subsystem Options" 22config IEEE1394_OHCI1394
23 depends on IEEE1394 23 tristate "OHCI-1394 controllers"
24 24 depends on PCI && IEEE1394
25config IEEE1394_VERBOSEDEBUG
26 bool "Excessive debugging output"
27 depends on IEEE1394
28 help 25 help
29 If you say Y here, you will get very verbose debugging logs from 26 Enable this driver if you have an IEEE 1394 controller based on the
30 the subsystem which includes a dump of the header of every sent 27 OHCI-1394 specification. The current driver is only tested with OHCI
31 and received packet. This can amount to a high amount of data 28 chipsets made by Texas Instruments and NEC. Most third-party vendors
32 collected in a very short time which is usually also saved to 29 use one of these chipsets. It should work with any OHCI-1394
33 disk by the system logging daemons. 30 compliant card, however.
34 31
35 Say Y if you really want or need the debugging output, everyone 32 To compile this driver as a module, say M here: the
36 else says N. 33 module will be called ohci1394.
37 34
38comment "Controllers" 35 NOTE:
39 depends on IEEE1394
40 36
41comment "Texas Instruments PCILynx requires I2C" 37 You should only build either ohci1394 or the new firewire-ohci driver,
38 but not both. If you nevertheless want to install both, you should
39 configure them only as modules and blacklist the driver(s) which you
40 don't want to have auto-loaded. Add either
41
42 blacklist firewire-ohci
43 or
44 blacklist ohci1394
45 blacklist video1394
46 blacklist dv1394
47
48 to /etc/modprobe.conf or /etc/modprobe.d/* and update modprobe.conf
49 depending on your distribution. The latter two modules should be
50 blacklisted together with ohci1394 because they depend on ohci1394.
51
52 If you have an old modprobe which doesn't implement the blacklist
53 directive, use "install modulename /bin/true" for the modules to be
54 blacklisted.
55
56comment "PCILynx controller requires I2C"
42 depends on IEEE1394 && I2C=n 57 depends on IEEE1394 && I2C=n
43 58
44config IEEE1394_PCILYNX 59config IEEE1394_PCILYNX
45 tristate "Texas Instruments PCILynx support" 60 tristate "PCILynx controller"
46 depends on PCI && IEEE1394 && I2C 61 depends on PCI && IEEE1394 && I2C
47 select I2C_ALGOBIT 62 select I2C_ALGOBIT
48 help 63 help
@@ -57,35 +72,11 @@ config IEEE1394_PCILYNX
57 PowerMacs G3 B&W contain the PCILynx controller. Therefore 72 PowerMacs G3 B&W contain the PCILynx controller. Therefore
58 almost everybody can say N here. 73 almost everybody can say N here.
59 74
60config IEEE1394_OHCI1394
61 tristate "OHCI-1394 support"
62 depends on PCI && IEEE1394
63 help
64 Enable this driver if you have an IEEE 1394 controller based on the
65 OHCI-1394 specification. The current driver is only tested with OHCI
66 chipsets made by Texas Instruments and NEC. Most third-party vendors
67 use one of these chipsets. It should work with any OHCI-1394
68 compliant card, however.
69
70 To compile this driver as a module, say M here: the
71 module will be called ohci1394.
72
73comment "Protocols"
74 depends on IEEE1394
75
76config IEEE1394_VIDEO1394
77 tristate "OHCI-1394 Video support"
78 depends on IEEE1394 && IEEE1394_OHCI1394
79 help
80 This option enables video device usage for OHCI-1394 cards. Enable
81 this option only if you have an IEEE 1394 video device connected to
82 an OHCI-1394 card.
83
84comment "SBP-2 support (for storage devices) requires SCSI" 75comment "SBP-2 support (for storage devices) requires SCSI"
85 depends on IEEE1394 && SCSI=n 76 depends on IEEE1394 && SCSI=n
86 77
87config IEEE1394_SBP2 78config IEEE1394_SBP2
88 tristate "SBP-2 support (Harddisks etc.)" 79 tristate "Storage devices (SBP-2 protocol)"
89 depends on IEEE1394 && SCSI 80 depends on IEEE1394 && SCSI
90 help 81 help
91 This option enables you to use SBP-2 devices connected to an IEEE 82 This option enables you to use SBP-2 devices connected to an IEEE
@@ -127,24 +118,47 @@ config IEEE1394_ETH1394
127 118
128 The module is called eth1394 although it does not emulate Ethernet. 119 The module is called eth1394 although it does not emulate Ethernet.
129 120
121config IEEE1394_RAWIO
122 tristate "raw1394 userspace interface"
123 depends on IEEE1394
124 help
125 This option adds support for the raw1394 device file which enables
126 direct communication of user programs with IEEE 1394 devices
127 (isochronous and asynchronous). Almost all application programs
128 which access FireWire require this option.
129
130 To compile this driver as a module, say M here: the module will be
131 called raw1394.
132
133config IEEE1394_VIDEO1394
134 tristate "video1394 userspace interface"
135 depends on IEEE1394 && IEEE1394_OHCI1394
136 help
137 This option adds support for the video1394 device files which enable
138 isochronous communication of user programs with IEEE 1394 devices,
139 especially video capture or export. This interface is used by all
140 libdc1394 based programs and by several other programs, in addition to
141 the raw1394 interface. It is generally not required for DV capture.
142
143 To compile this driver as a module, say M here: the module will be
144 called video1394.
145
130config IEEE1394_DV1394 146config IEEE1394_DV1394
131 tristate "OHCI-DV I/O support (deprecated)" 147 tristate "dv1394 userspace interface (deprecated)"
132 depends on IEEE1394 && IEEE1394_OHCI1394 148 depends on IEEE1394 && IEEE1394_OHCI1394
133 help 149 help
134 The dv1394 driver is unsupported and may be removed from Linux in a 150 The dv1394 driver is unsupported and may be removed from Linux in a
135 future release. Its functionality is now provided by raw1394 together 151 future release. Its functionality is now provided by raw1394 together
136 with libraries such as libiec61883. 152 with libraries such as libiec61883.
137 153
138config IEEE1394_RAWIO 154config IEEE1394_VERBOSEDEBUG
139 tristate "Raw IEEE1394 I/O support" 155 bool "Excessive debugging output"
140 depends on IEEE1394 156 depends on IEEE1394
141 help 157 help
142 This option adds support for the raw1394 device file which enables 158 If you say Y here, you will get very verbose debugging logs from the
143 direct communication of user programs with the IEEE 1394 bus and thus 159 ieee1394 drivers, including sent and received packet headers. This
144 with the attached peripherals. Almost all application programs which 160 will quickly result in large amounts of data sent to the system log.
145 access FireWire require this option.
146 161
147 To compile this driver as a module, say M here: the module will be 162 Say Y if you really need the debugging output. Everyone else says N.
148 called raw1394.
149 163
150endmenu 164endmenu
diff --git a/drivers/infiniband/core/uverbs_main.c b/drivers/infiniband/core/uverbs_main.c
index f806da184b5..caed42bf7ef 100644
--- a/drivers/infiniband/core/uverbs_main.c
+++ b/drivers/infiniband/core/uverbs_main.c
@@ -423,7 +423,7 @@ static void ib_uverbs_async_handler(struct ib_uverbs_file *file,
423 unsigned long flags; 423 unsigned long flags;
424 424
425 spin_lock_irqsave(&file->async_file->lock, flags); 425 spin_lock_irqsave(&file->async_file->lock, flags);
426 if (!file->async_file->is_closed) { 426 if (file->async_file->is_closed) {
427 spin_unlock_irqrestore(&file->async_file->lock, flags); 427 spin_unlock_irqrestore(&file->async_file->lock, flags);
428 return; 428 return;
429 } 429 }
diff --git a/drivers/infiniband/hw/mthca/mthca_memfree.c b/drivers/infiniband/hw/mthca/mthca_memfree.c
index b224079d4e1..d5862e5d99a 100644
--- a/drivers/infiniband/hw/mthca/mthca_memfree.c
+++ b/drivers/infiniband/hw/mthca/mthca_memfree.c
@@ -109,7 +109,11 @@ static int mthca_alloc_icm_pages(struct scatterlist *mem, int order, gfp_t gfp_m
109{ 109{
110 struct page *page; 110 struct page *page;
111 111
112 page = alloc_pages(gfp_mask, order); 112 /*
113 * Use __GFP_ZERO because buggy firmware assumes ICM pages are
114 * cleared, and subtle failures are seen if they aren't.
115 */
116 page = alloc_pages(gfp_mask | __GFP_ZERO, order);
113 if (!page) 117 if (!page)
114 return -ENOMEM; 118 return -ENOMEM;
115 119
diff --git a/drivers/infiniband/hw/nes/nes_verbs.c b/drivers/infiniband/hw/nes/nes_verbs.c
index 99b3c4ae86e..d617da9bd35 100644
--- a/drivers/infiniband/hw/nes/nes_verbs.c
+++ b/drivers/infiniband/hw/nes/nes_verbs.c
@@ -2456,10 +2456,8 @@ static struct ib_mr *nes_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
2456 if ((page_count!=0)&&(page_count<<12)-(region->offset&(4096-1))>=region->length) 2456 if ((page_count!=0)&&(page_count<<12)-(region->offset&(4096-1))>=region->length)
2457 goto enough_pages; 2457 goto enough_pages;
2458 if ((page_count&0x01FF) == 0) { 2458 if ((page_count&0x01FF) == 0) {
2459 if (page_count>(1024*512)) { 2459 if (page_count >= 1024 * 512) {
2460 ib_umem_release(region); 2460 ib_umem_release(region);
2461 pci_free_consistent(nesdev->pcidev, 4096, vpbl.pbl_vbase,
2462 vpbl.pbl_pbase);
2463 nes_free_resource(nesadapter, 2461 nes_free_resource(nesadapter,
2464 nesadapter->allocated_mrs, stag_index); 2462 nesadapter->allocated_mrs, stag_index);
2465 kfree(nesmr); 2463 kfree(nesmr);
diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig
index 3ad8bd9f754..432699d61c5 100644
--- a/drivers/input/misc/Kconfig
+++ b/drivers/input/misc/Kconfig
@@ -15,7 +15,6 @@ if INPUT_MISC
15config INPUT_PCSPKR 15config INPUT_PCSPKR
16 tristate "PC Speaker support" 16 tristate "PC Speaker support"
17 depends on PCSPKR_PLATFORM 17 depends on PCSPKR_PLATFORM
18 depends on SND_PCSP=n
19 help 18 help
20 Say Y here if you want the standard PC Speaker to be used for 19 Say Y here if you want the standard PC Speaker to be used for
21 bells and whistles. 20 bells and whistles.
diff --git a/drivers/input/mouse/appletouch.c b/drivers/input/mouse/appletouch.c
index 8dd3942f302..ce6fdec19e1 100644
--- a/drivers/input/mouse/appletouch.c
+++ b/drivers/input/mouse/appletouch.c
@@ -589,6 +589,21 @@ static void atp_close(struct input_dev *input)
589 dev->open = 0; 589 dev->open = 0;
590} 590}
591 591
592static int atp_handle_geyser(struct atp *dev)
593{
594 struct usb_device *udev = dev->udev;
595
596 if (!atp_is_fountain(dev)) {
597 /* switch to raw sensor mode */
598 if (atp_geyser_init(udev))
599 return -EIO;
600
601 printk(KERN_INFO "appletouch: Geyser mode initialized.\n");
602 }
603
604 return 0;
605}
606
592static int atp_probe(struct usb_interface *iface, const struct usb_device_id *id) 607static int atp_probe(struct usb_interface *iface, const struct usb_device_id *id)
593{ 608{
594 struct atp *dev; 609 struct atp *dev;
@@ -633,14 +648,6 @@ static int atp_probe(struct usb_interface *iface, const struct usb_device_id *id
633 else 648 else
634 dev->datalen = 81; 649 dev->datalen = 81;
635 650
636 if (!atp_is_fountain(dev)) {
637 /* switch to raw sensor mode */
638 if (atp_geyser_init(udev))
639 goto err_free_devs;
640
641 printk(KERN_INFO "appletouch: Geyser mode initialized.\n");
642 }
643
644 dev->urb = usb_alloc_urb(0, GFP_KERNEL); 651 dev->urb = usb_alloc_urb(0, GFP_KERNEL);
645 if (!dev->urb) 652 if (!dev->urb)
646 goto err_free_devs; 653 goto err_free_devs;
@@ -654,6 +661,10 @@ static int atp_probe(struct usb_interface *iface, const struct usb_device_id *id
654 usb_rcvintpipe(udev, int_in_endpointAddr), 661 usb_rcvintpipe(udev, int_in_endpointAddr),
655 dev->data, dev->datalen, atp_complete, dev, 1); 662 dev->data, dev->datalen, atp_complete, dev, 1);
656 663
664 error = atp_handle_geyser(dev);
665 if (error)
666 goto err_free_buffer;
667
657 usb_make_path(udev, dev->phys, sizeof(dev->phys)); 668 usb_make_path(udev, dev->phys, sizeof(dev->phys));
658 strlcat(dev->phys, "/input0", sizeof(dev->phys)); 669 strlcat(dev->phys, "/input0", sizeof(dev->phys));
659 670
@@ -744,6 +755,20 @@ static void atp_disconnect(struct usb_interface *iface)
744 printk(KERN_INFO "input: appletouch disconnected\n"); 755 printk(KERN_INFO "input: appletouch disconnected\n");
745} 756}
746 757
758static int atp_recover(struct atp *dev)
759{
760 int error;
761
762 error = atp_handle_geyser(dev);
763 if (error)
764 return error;
765
766 if (dev->open && usb_submit_urb(dev->urb, GFP_ATOMIC))
767 return -EIO;
768
769 return 0;
770}
771
747static int atp_suspend(struct usb_interface *iface, pm_message_t message) 772static int atp_suspend(struct usb_interface *iface, pm_message_t message)
748{ 773{
749 struct atp *dev = usb_get_intfdata(iface); 774 struct atp *dev = usb_get_intfdata(iface);
@@ -764,12 +789,20 @@ static int atp_resume(struct usb_interface *iface)
764 return 0; 789 return 0;
765} 790}
766 791
792static int atp_reset_resume(struct usb_interface *iface)
793{
794 struct atp *dev = usb_get_intfdata(iface);
795
796 return atp_recover(dev);
797}
798
767static struct usb_driver atp_driver = { 799static struct usb_driver atp_driver = {
768 .name = "appletouch", 800 .name = "appletouch",
769 .probe = atp_probe, 801 .probe = atp_probe,
770 .disconnect = atp_disconnect, 802 .disconnect = atp_disconnect,
771 .suspend = atp_suspend, 803 .suspend = atp_suspend,
772 .resume = atp_resume, 804 .resume = atp_resume,
805 .reset_resume = atp_reset_resume,
773 .id_table = atp_table, 806 .id_table = atp_table,
774}; 807};
775 808
diff --git a/drivers/input/serio/i8042-x86ia64io.h b/drivers/input/serio/i8042-x86ia64io.h
index 9aafa96cb74..78eb7841174 100644
--- a/drivers/input/serio/i8042-x86ia64io.h
+++ b/drivers/input/serio/i8042-x86ia64io.h
@@ -193,6 +193,13 @@ static struct dmi_system_id __initdata i8042_dmi_nomux_table[] = {
193 }, 193 },
194 }, 194 },
195 { 195 {
196 .ident = "Fujitsu-Siemens Amilo Pro 2030",
197 .matches = {
198 DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU SIEMENS"),
199 DMI_MATCH(DMI_PRODUCT_NAME, "AMILO PRO V2030"),
200 },
201 },
202 {
196 /* 203 /*
197 * No data is coming from the touchscreen unless KBC 204 * No data is coming from the touchscreen unless KBC
198 * is in legacy mode. 205 * is in legacy mode.
diff --git a/drivers/input/serio/i8042.c b/drivers/input/serio/i8042.c
index 592ff55b62d..170f71ee577 100644
--- a/drivers/input/serio/i8042.c
+++ b/drivers/input/serio/i8042.c
@@ -952,8 +952,12 @@ static int i8042_resume(struct platform_device *dev)
952 i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS; 952 i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS;
953 i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT); 953 i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT);
954 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 954 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
955 printk(KERN_ERR "i8042: Can't write CTR to resume\n"); 955 printk(KERN_WARNING "i8042: Can't write CTR to resume, retrying...\n");
956 return -EIO; 956 msleep(50);
957 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
958 printk(KERN_ERR "i8042: CTR write retry failed\n");
959 return -EIO;
960 }
957 } 961 }
958 962
959 963
diff --git a/drivers/lguest/x86/core.c b/drivers/lguest/x86/core.c
index 5126d5d9ea0..2e554a4ab33 100644
--- a/drivers/lguest/x86/core.c
+++ b/drivers/lguest/x86/core.c
@@ -176,7 +176,7 @@ void lguest_arch_run_guest(struct lg_cpu *cpu)
176 * we set it now, so we can trap and pass that trap to the Guest if it 176 * we set it now, so we can trap and pass that trap to the Guest if it
177 * uses the FPU. */ 177 * uses the FPU. */
178 if (cpu->ts) 178 if (cpu->ts)
179 lguest_set_ts(); 179 unlazy_fpu(current);
180 180
181 /* SYSENTER is an optimized way of doing system calls. We can't allow 181 /* SYSENTER is an optimized way of doing system calls. We can't allow
182 * it because it always jumps to privilege level 0. A normal Guest 182 * it because it always jumps to privilege level 0. A normal Guest
@@ -196,6 +196,10 @@ void lguest_arch_run_guest(struct lg_cpu *cpu)
196 * trap made the switcher code come back, and an error code which some 196 * trap made the switcher code come back, and an error code which some
197 * traps set. */ 197 * traps set. */
198 198
199 /* Restore SYSENTER if it's supposed to be on. */
200 if (boot_cpu_has(X86_FEATURE_SEP))
201 wrmsr(MSR_IA32_SYSENTER_CS, __KERNEL_CS, 0);
202
199 /* If the Guest page faulted, then the cr2 register will tell us the 203 /* If the Guest page faulted, then the cr2 register will tell us the
200 * bad virtual address. We have to grab this now, because once we 204 * bad virtual address. We have to grab this now, because once we
201 * re-enable interrupts an interrupt could fault and thus overwrite 205 * re-enable interrupts an interrupt could fault and thus overwrite
@@ -203,13 +207,12 @@ void lguest_arch_run_guest(struct lg_cpu *cpu)
203 if (cpu->regs->trapnum == 14) 207 if (cpu->regs->trapnum == 14)
204 cpu->arch.last_pagefault = read_cr2(); 208 cpu->arch.last_pagefault = read_cr2();
205 /* Similarly, if we took a trap because the Guest used the FPU, 209 /* Similarly, if we took a trap because the Guest used the FPU,
206 * we have to restore the FPU it expects to see. */ 210 * we have to restore the FPU it expects to see.
211 * math_state_restore() may sleep and we may even move off to
212 * a different CPU. So all the critical stuff should be done
213 * before this. */
207 else if (cpu->regs->trapnum == 7) 214 else if (cpu->regs->trapnum == 7)
208 math_state_restore(); 215 math_state_restore();
209
210 /* Restore SYSENTER if it's supposed to be on. */
211 if (boot_cpu_has(X86_FEATURE_SEP))
212 wrmsr(MSR_IA32_SYSENTER_CS, __KERNEL_CS, 0);
213} 216}
214 217
215/*H:130 Now we've examined the hypercall code; our Guest can make requests. 218/*H:130 Now we've examined the hypercall code; our Guest can make requests.
diff --git a/drivers/macintosh/mediabay.c b/drivers/macintosh/mediabay.c
index c34bdf852e3..818aba36854 100644
--- a/drivers/macintosh/mediabay.c
+++ b/drivers/macintosh/mediabay.c
@@ -84,7 +84,7 @@ struct media_bay_info {
84 int cd_irq; 84 int cd_irq;
85 int cd_retry; 85 int cd_retry;
86#endif 86#endif
87#if defined(CONFIG_BLK_DEV_IDE_PMAC) || defined(CONFIG_MAC_FLOPPY) 87#if defined(CONFIG_BLK_DEV_IDE_PMAC)
88 int cd_index; 88 int cd_index;
89#endif 89#endif
90}; 90};
@@ -417,6 +417,7 @@ static void poll_media_bay(struct media_bay_info* bay)
417 } 417 }
418} 418}
419 419
420#ifdef CONFIG_BLK_DEV_IDE_PMAC
420int check_media_bay(struct device_node *which_bay, int what) 421int check_media_bay(struct device_node *which_bay, int what)
421{ 422{
422 int i; 423 int i;
@@ -432,7 +433,6 @@ int check_media_bay(struct device_node *which_bay, int what)
432} 433}
433EXPORT_SYMBOL(check_media_bay); 434EXPORT_SYMBOL(check_media_bay);
434 435
435#ifdef CONFIG_BLK_DEV_IDE_PMAC
436int check_media_bay_by_base(unsigned long base, int what) 436int check_media_bay_by_base(unsigned long base, int what)
437{ 437{
438 int i; 438 int i;
diff --git a/drivers/macintosh/smu.c b/drivers/macintosh/smu.c
index 77ad192962c..d86d57af282 100644
--- a/drivers/macintosh/smu.c
+++ b/drivers/macintosh/smu.c
@@ -483,12 +483,15 @@ int __init smu_init (void)
483 483
484 if (smu_cmdbuf_abs == 0) { 484 if (smu_cmdbuf_abs == 0) {
485 printk(KERN_ERR "SMU: Command buffer not allocated !\n"); 485 printk(KERN_ERR "SMU: Command buffer not allocated !\n");
486 of_node_put(np);
486 return -EINVAL; 487 return -EINVAL;
487 } 488 }
488 489
489 smu = alloc_bootmem(sizeof(struct smu_device)); 490 smu = alloc_bootmem(sizeof(struct smu_device));
490 if (smu == NULL) 491 if (smu == NULL) {
492 of_node_put(np);
491 return -ENOMEM; 493 return -ENOMEM;
494 }
492 memset(smu, 0, sizeof(*smu)); 495 memset(smu, 0, sizeof(*smu));
493 496
494 spin_lock_init(&smu->lock); 497 spin_lock_init(&smu->lock);
diff --git a/drivers/macintosh/therm_adt746x.c b/drivers/macintosh/therm_adt746x.c
index 54f4942a296..5366dc93fb3 100644
--- a/drivers/macintosh/therm_adt746x.c
+++ b/drivers/macintosh/therm_adt746x.c
@@ -562,18 +562,24 @@ thermostat_init(void)
562 therm_type = ADT7460; 562 therm_type = ADT7460;
563 else if (of_device_is_compatible(np, "adt7467")) 563 else if (of_device_is_compatible(np, "adt7467"))
564 therm_type = ADT7467; 564 therm_type = ADT7467;
565 else 565 else {
566 of_node_put(np);
566 return -ENODEV; 567 return -ENODEV;
568 }
567 569
568 prop = of_get_property(np, "hwsensor-params-version", NULL); 570 prop = of_get_property(np, "hwsensor-params-version", NULL);
569 printk(KERN_INFO "adt746x: version %d (%ssupported)\n", *prop, 571 printk(KERN_INFO "adt746x: version %d (%ssupported)\n", *prop,
570 (*prop == 1)?"":"un"); 572 (*prop == 1)?"":"un");
571 if (*prop != 1) 573 if (*prop != 1) {
574 of_node_put(np);
572 return -ENODEV; 575 return -ENODEV;
576 }
573 577
574 prop = of_get_property(np, "reg", NULL); 578 prop = of_get_property(np, "reg", NULL);
575 if (!prop) 579 if (!prop) {
580 of_node_put(np);
576 return -ENODEV; 581 return -ENODEV;
582 }
577 583
578 /* look for bus either by path or using "reg" */ 584 /* look for bus either by path or using "reg" */
579 if (strstr(np->full_name, "/i2c-bus@") != NULL) { 585 if (strstr(np->full_name, "/i2c-bus@") != NULL) {
@@ -610,6 +616,7 @@ thermostat_init(void)
610 616
611 if (of_dev == NULL) { 617 if (of_dev == NULL) {
612 printk(KERN_ERR "Can't register temperatures device !\n"); 618 printk(KERN_ERR "Can't register temperatures device !\n");
619 of_node_put(np);
613 return -ENODEV; 620 return -ENODEV;
614 } 621 }
615 622
diff --git a/drivers/net/atlx/atl1.c b/drivers/net/atlx/atl1.c
index 99e0b4cdc56..3c798ae5c34 100644
--- a/drivers/net/atlx/atl1.c
+++ b/drivers/net/atlx/atl1.c
@@ -471,7 +471,6 @@ static int atl1_get_permanent_address(struct atl1_hw *hw)
471 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN); 471 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
472 return 0; 472 return 0;
473 } 473 }
474 return 1;
475 } 474 }
476 475
477 /* see if SPI FLAGS exist ? */ 476 /* see if SPI FLAGS exist ? */
diff --git a/drivers/net/enc28j60.c b/drivers/net/enc28j60.c
index 46a90e9ec56..c05cb159c77 100644
--- a/drivers/net/enc28j60.c
+++ b/drivers/net/enc28j60.c
@@ -400,26 +400,31 @@ enc28j60_packet_write(struct enc28j60_net *priv, int len, const u8 *data)
400 mutex_unlock(&priv->lock); 400 mutex_unlock(&priv->lock);
401} 401}
402 402
403/* 403static unsigned long msec20_to_jiffies;
404 * Wait until the PHY operation is complete. 404
405 */ 405static int poll_ready(struct enc28j60_net *priv, u8 reg, u8 mask, u8 val)
406static int wait_phy_ready(struct enc28j60_net *priv)
407{ 406{
408 unsigned long timeout = jiffies + 20 * HZ / 1000; 407 unsigned long timeout = jiffies + msec20_to_jiffies;
409 int ret = 1;
410 408
411 /* 20 msec timeout read */ 409 /* 20 msec timeout read */
412 while (nolock_regb_read(priv, MISTAT) & MISTAT_BUSY) { 410 while ((nolock_regb_read(priv, reg) & mask) != val) {
413 if (time_after(jiffies, timeout)) { 411 if (time_after(jiffies, timeout)) {
414 if (netif_msg_drv(priv)) 412 if (netif_msg_drv(priv))
415 printk(KERN_DEBUG DRV_NAME 413 dev_dbg(&priv->spi->dev,
416 ": PHY ready timeout!\n"); 414 "reg %02x ready timeout!\n", reg);
417 ret = 0; 415 return -ETIMEDOUT;
418 break;
419 } 416 }
420 cpu_relax(); 417 cpu_relax();
421 } 418 }
422 return ret; 419 return 0;
420}
421
422/*
423 * Wait until the PHY operation is complete.
424 */
425static int wait_phy_ready(struct enc28j60_net *priv)
426{
427 return poll_ready(priv, MISTAT, MISTAT_BUSY, 0) ? 0 : 1;
423} 428}
424 429
425/* 430/*
@@ -594,6 +599,32 @@ static void nolock_txfifo_init(struct enc28j60_net *priv, u16 start, u16 end)
594 nolock_regw_write(priv, ETXNDL, end); 599 nolock_regw_write(priv, ETXNDL, end);
595} 600}
596 601
602/*
603 * Low power mode shrinks power consumption about 100x, so we'd like
604 * the chip to be in that mode whenever it's inactive. (However, we
605 * can't stay in lowpower mode during suspend with WOL active.)
606 */
607static void enc28j60_lowpower(struct enc28j60_net *priv, bool is_low)
608{
609 if (netif_msg_drv(priv))
610 dev_dbg(&priv->spi->dev, "%s power...\n",
611 is_low ? "low" : "high");
612
613 mutex_lock(&priv->lock);
614 if (is_low) {
615 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
616 poll_ready(priv, ESTAT, ESTAT_RXBUSY, 0);
617 poll_ready(priv, ECON1, ECON1_TXRTS, 0);
618 /* ECON2_VRPS was set during initialization */
619 nolock_reg_bfset(priv, ECON2, ECON2_PWRSV);
620 } else {
621 nolock_reg_bfclr(priv, ECON2, ECON2_PWRSV);
622 poll_ready(priv, ESTAT, ESTAT_CLKRDY, ESTAT_CLKRDY);
623 /* caller sets ECON1_RXEN */
624 }
625 mutex_unlock(&priv->lock);
626}
627
597static int enc28j60_hw_init(struct enc28j60_net *priv) 628static int enc28j60_hw_init(struct enc28j60_net *priv)
598{ 629{
599 u8 reg; 630 u8 reg;
@@ -612,8 +643,8 @@ static int enc28j60_hw_init(struct enc28j60_net *priv)
612 priv->tx_retry_count = 0; 643 priv->tx_retry_count = 0;
613 priv->max_pk_counter = 0; 644 priv->max_pk_counter = 0;
614 priv->rxfilter = RXFILTER_NORMAL; 645 priv->rxfilter = RXFILTER_NORMAL;
615 /* enable address auto increment */ 646 /* enable address auto increment and voltage regulator powersave */
616 nolock_regb_write(priv, ECON2, ECON2_AUTOINC); 647 nolock_regb_write(priv, ECON2, ECON2_AUTOINC | ECON2_VRPS);
617 648
618 nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT); 649 nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT);
619 nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT); 650 nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT);
@@ -690,7 +721,7 @@ static int enc28j60_hw_init(struct enc28j60_net *priv)
690 721
691static void enc28j60_hw_enable(struct enc28j60_net *priv) 722static void enc28j60_hw_enable(struct enc28j60_net *priv)
692{ 723{
693 /* enable interrutps */ 724 /* enable interrupts */
694 if (netif_msg_hw(priv)) 725 if (netif_msg_hw(priv))
695 printk(KERN_DEBUG DRV_NAME ": %s() enabling interrupts.\n", 726 printk(KERN_DEBUG DRV_NAME ": %s() enabling interrupts.\n",
696 __FUNCTION__); 727 __FUNCTION__);
@@ -726,15 +757,12 @@ enc28j60_setlink(struct net_device *ndev, u8 autoneg, u16 speed, u8 duplex)
726 int ret = 0; 757 int ret = 0;
727 758
728 if (!priv->hw_enable) { 759 if (!priv->hw_enable) {
729 if (autoneg == AUTONEG_DISABLE && speed == SPEED_10) { 760 /* link is in low power mode now; duplex setting
761 * will take effect on next enc28j60_hw_init().
762 */
763 if (autoneg == AUTONEG_DISABLE && speed == SPEED_10)
730 priv->full_duplex = (duplex == DUPLEX_FULL); 764 priv->full_duplex = (duplex == DUPLEX_FULL);
731 if (!enc28j60_hw_init(priv)) { 765 else {
732 if (netif_msg_drv(priv))
733 dev_err(&ndev->dev,
734 "hw_reset() failed\n");
735 ret = -EINVAL;
736 }
737 } else {
738 if (netif_msg_link(priv)) 766 if (netif_msg_link(priv))
739 dev_warn(&ndev->dev, 767 dev_warn(&ndev->dev,
740 "unsupported link setting\n"); 768 "unsupported link setting\n");
@@ -1307,7 +1335,8 @@ static int enc28j60_net_open(struct net_device *dev)
1307 } 1335 }
1308 return -EADDRNOTAVAIL; 1336 return -EADDRNOTAVAIL;
1309 } 1337 }
1310 /* Reset the hardware here */ 1338 /* Reset the hardware here (and take it out of low power mode) */
1339 enc28j60_lowpower(priv, false);
1311 enc28j60_hw_disable(priv); 1340 enc28j60_hw_disable(priv);
1312 if (!enc28j60_hw_init(priv)) { 1341 if (!enc28j60_hw_init(priv)) {
1313 if (netif_msg_ifup(priv)) 1342 if (netif_msg_ifup(priv))
@@ -1337,6 +1366,7 @@ static int enc28j60_net_close(struct net_device *dev)
1337 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __FUNCTION__); 1366 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __FUNCTION__);
1338 1367
1339 enc28j60_hw_disable(priv); 1368 enc28j60_hw_disable(priv);
1369 enc28j60_lowpower(priv, true);
1340 netif_stop_queue(dev); 1370 netif_stop_queue(dev);
1341 1371
1342 return 0; 1372 return 0;
@@ -1537,6 +1567,8 @@ static int __devinit enc28j60_probe(struct spi_device *spi)
1537 dev->watchdog_timeo = TX_TIMEOUT; 1567 dev->watchdog_timeo = TX_TIMEOUT;
1538 SET_ETHTOOL_OPS(dev, &enc28j60_ethtool_ops); 1568 SET_ETHTOOL_OPS(dev, &enc28j60_ethtool_ops);
1539 1569
1570 enc28j60_lowpower(priv, true);
1571
1540 ret = register_netdev(dev); 1572 ret = register_netdev(dev);
1541 if (ret) { 1573 if (ret) {
1542 if (netif_msg_probe(priv)) 1574 if (netif_msg_probe(priv))
@@ -1556,7 +1588,7 @@ error_alloc:
1556 return ret; 1588 return ret;
1557} 1589}
1558 1590
1559static int enc28j60_remove(struct spi_device *spi) 1591static int __devexit enc28j60_remove(struct spi_device *spi)
1560{ 1592{
1561 struct enc28j60_net *priv = dev_get_drvdata(&spi->dev); 1593 struct enc28j60_net *priv = dev_get_drvdata(&spi->dev);
1562 1594
@@ -1573,15 +1605,16 @@ static int enc28j60_remove(struct spi_device *spi)
1573static struct spi_driver enc28j60_driver = { 1605static struct spi_driver enc28j60_driver = {
1574 .driver = { 1606 .driver = {
1575 .name = DRV_NAME, 1607 .name = DRV_NAME,
1576 .bus = &spi_bus_type,
1577 .owner = THIS_MODULE, 1608 .owner = THIS_MODULE,
1578 }, 1609 },
1579 .probe = enc28j60_probe, 1610 .probe = enc28j60_probe,
1580 .remove = __devexit_p(enc28j60_remove), 1611 .remove = __devexit_p(enc28j60_remove),
1581}; 1612};
1582 1613
1583static int __init enc28j60_init(void) 1614static int __init enc28j60_init(void)
1584{ 1615{
1616 msec20_to_jiffies = msecs_to_jiffies(20);
1617
1585 return spi_register_driver(&enc28j60_driver); 1618 return spi_register_driver(&enc28j60_driver);
1586} 1619}
1587 1620
diff --git a/drivers/net/ibm_newemac/Kconfig b/drivers/net/ibm_newemac/Kconfig
index 0d3e7380bad..70a3272ee99 100644
--- a/drivers/net/ibm_newemac/Kconfig
+++ b/drivers/net/ibm_newemac/Kconfig
@@ -1,6 +1,7 @@
1config IBM_NEW_EMAC 1config IBM_NEW_EMAC
2 tristate "IBM EMAC Ethernet support" 2 tristate "IBM EMAC Ethernet support"
3 depends on PPC_DCR && PPC_MERGE 3 depends on PPC_DCR && PPC_MERGE
4 select CRC32
4 help 5 help
5 This driver supports the IBM EMAC family of Ethernet controllers 6 This driver supports the IBM EMAC family of Ethernet controllers
6 typically found on 4xx embedded PowerPC chips, but also on the 7 typically found on 4xx embedded PowerPC chips, but also on the
diff --git a/drivers/net/netxen/netxen_nic.h b/drivers/net/netxen/netxen_nic.h
index 8cb29f5b103..da4c4fb9706 100644
--- a/drivers/net/netxen/netxen_nic.h
+++ b/drivers/net/netxen/netxen_nic.h
@@ -776,7 +776,6 @@ struct netxen_hardware_context {
776 776
777 u8 revision_id; 777 u8 revision_id;
778 u16 board_type; 778 u16 board_type;
779 u16 max_ports;
780 struct netxen_board_info boardcfg; 779 struct netxen_board_info boardcfg;
781 u32 xg_linkup; 780 u32 xg_linkup;
782 u32 qg_linksup; 781 u32 qg_linksup;
@@ -863,6 +862,7 @@ struct netxen_adapter {
863 unsigned char mac_addr[ETH_ALEN]; 862 unsigned char mac_addr[ETH_ALEN];
864 int mtu; 863 int mtu;
865 int portnum; 864 int portnum;
865 u8 physical_port;
866 866
867 struct work_struct watchdog_task; 867 struct work_struct watchdog_task;
868 struct timer_list watchdog_timer; 868 struct timer_list watchdog_timer;
@@ -1034,7 +1034,6 @@ int netxen_rom_se(struct netxen_adapter *adapter, int addr);
1034 1034
1035/* Functions from netxen_nic_isr.c */ 1035/* Functions from netxen_nic_isr.c */
1036void netxen_initialize_adapter_sw(struct netxen_adapter *adapter); 1036void netxen_initialize_adapter_sw(struct netxen_adapter *adapter);
1037void netxen_initialize_adapter_hw(struct netxen_adapter *adapter);
1038void *netxen_alloc(struct pci_dev *pdev, size_t sz, dma_addr_t * ptr, 1037void *netxen_alloc(struct pci_dev *pdev, size_t sz, dma_addr_t * ptr,
1039 struct pci_dev **used_dev); 1038 struct pci_dev **used_dev);
1040void netxen_initialize_adapter_ops(struct netxen_adapter *adapter); 1039void netxen_initialize_adapter_ops(struct netxen_adapter *adapter);
@@ -1077,20 +1076,6 @@ static const struct netxen_brdinfo netxen_boards[] = {
1077 1076
1078#define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards) 1077#define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards)
1079 1078
1080static inline void get_brd_port_by_type(u32 type, int *ports)
1081{
1082 int i, found = 0;
1083 for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
1084 if (netxen_boards[i].brdtype == type) {
1085 *ports = netxen_boards[i].ports;
1086 found = 1;
1087 break;
1088 }
1089 }
1090 if (!found)
1091 *ports = 0;
1092}
1093
1094static inline void get_brd_name_by_type(u32 type, char *name) 1079static inline void get_brd_name_by_type(u32 type, char *name)
1095{ 1080{
1096 int i, found = 0; 1081 int i, found = 0;
@@ -1169,5 +1154,4 @@ extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr,
1169 1154
1170extern struct ethtool_ops netxen_nic_ethtool_ops; 1155extern struct ethtool_ops netxen_nic_ethtool_ops;
1171 1156
1172extern int physical_port[]; /* physical port # from virtual port.*/
1173#endif /* __NETXEN_NIC_H_ */ 1157#endif /* __NETXEN_NIC_H_ */
diff --git a/drivers/net/netxen/netxen_nic_ethtool.c b/drivers/net/netxen/netxen_nic_ethtool.c
index 6e98d830eef..723487bf200 100644
--- a/drivers/net/netxen/netxen_nic_ethtool.c
+++ b/drivers/net/netxen/netxen_nic_ethtool.c
@@ -369,7 +369,7 @@ netxen_nic_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *p)
369 for (i = 3; niu_registers[mode].reg[i - 3] != -1; i++) { 369 for (i = 3; niu_registers[mode].reg[i - 3] != -1; i++) {
370 /* GB: port specific registers */ 370 /* GB: port specific registers */
371 if (mode == 0 && i >= 19) 371 if (mode == 0 && i >= 19)
372 window = physical_port[adapter->portnum] * 372 window = adapter->physical_port *
373 NETXEN_NIC_PORT_WINDOW; 373 NETXEN_NIC_PORT_WINDOW;
374 374
375 NETXEN_NIC_LOCKED_READ_REG(niu_registers[mode]. 375 NETXEN_NIC_LOCKED_READ_REG(niu_registers[mode].
@@ -527,7 +527,7 @@ netxen_nic_get_pauseparam(struct net_device *dev,
527{ 527{
528 struct netxen_adapter *adapter = netdev_priv(dev); 528 struct netxen_adapter *adapter = netdev_priv(dev);
529 __u32 val; 529 __u32 val;
530 int port = physical_port[adapter->portnum]; 530 int port = adapter->physical_port;
531 531
532 if (adapter->ahw.board_type == NETXEN_NIC_GBE) { 532 if (adapter->ahw.board_type == NETXEN_NIC_GBE) {
533 if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS)) 533 if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS))
@@ -573,7 +573,7 @@ netxen_nic_set_pauseparam(struct net_device *dev,
573{ 573{
574 struct netxen_adapter *adapter = netdev_priv(dev); 574 struct netxen_adapter *adapter = netdev_priv(dev);
575 __u32 val; 575 __u32 val;
576 int port = physical_port[adapter->portnum]; 576 int port = adapter->physical_port;
577 /* read mode */ 577 /* read mode */
578 if (adapter->ahw.board_type == NETXEN_NIC_GBE) { 578 if (adapter->ahw.board_type == NETXEN_NIC_GBE) {
579 if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS)) 579 if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS))
diff --git a/drivers/net/netxen/netxen_nic_hw.c b/drivers/net/netxen/netxen_nic_hw.c
index af735646825..c43d06b8de9 100644
--- a/drivers/net/netxen/netxen_nic_hw.c
+++ b/drivers/net/netxen/netxen_nic_hw.c
@@ -396,11 +396,8 @@ int netxen_nic_hw_resources(struct netxen_adapter *adapter)
396 } 396 }
397 adapter->intr_scheme = readl( 397 adapter->intr_scheme = readl(
398 NETXEN_CRB_NORMALIZE(adapter, CRB_NIC_CAPABILITIES_FW)); 398 NETXEN_CRB_NORMALIZE(adapter, CRB_NIC_CAPABILITIES_FW));
399 printk(KERN_NOTICE "%s: FW capabilities:0x%x\n", netxen_nic_driver_name,
400 adapter->intr_scheme);
401 adapter->msi_mode = readl( 399 adapter->msi_mode = readl(
402 NETXEN_CRB_NORMALIZE(adapter, CRB_NIC_MSI_MODE_FW)); 400 NETXEN_CRB_NORMALIZE(adapter, CRB_NIC_MSI_MODE_FW));
403 DPRINTK(INFO, "Receive Peg ready too. starting stuff\n");
404 401
405 addr = netxen_alloc(adapter->ahw.pdev, 402 addr = netxen_alloc(adapter->ahw.pdev,
406 sizeof(struct netxen_ring_ctx) + 403 sizeof(struct netxen_ring_ctx) +
@@ -408,8 +405,6 @@ int netxen_nic_hw_resources(struct netxen_adapter *adapter)
408 (dma_addr_t *) & adapter->ctx_desc_phys_addr, 405 (dma_addr_t *) & adapter->ctx_desc_phys_addr,
409 &adapter->ctx_desc_pdev); 406 &adapter->ctx_desc_pdev);
410 407
411 printk(KERN_INFO "ctx_desc_phys_addr: 0x%llx\n",
412 (unsigned long long) adapter->ctx_desc_phys_addr);
413 if (addr == NULL) { 408 if (addr == NULL) {
414 DPRINTK(ERR, "bad return from pci_alloc_consistent\n"); 409 DPRINTK(ERR, "bad return from pci_alloc_consistent\n");
415 err = -ENOMEM; 410 err = -ENOMEM;
@@ -429,8 +424,6 @@ int netxen_nic_hw_resources(struct netxen_adapter *adapter)
429 adapter->max_tx_desc_count, 424 adapter->max_tx_desc_count,
430 (dma_addr_t *) & hw->cmd_desc_phys_addr, 425 (dma_addr_t *) & hw->cmd_desc_phys_addr,
431 &adapter->ahw.cmd_desc_pdev); 426 &adapter->ahw.cmd_desc_pdev);
432 printk(KERN_INFO "cmd_desc_phys_addr: 0x%llx\n",
433 (unsigned long long) hw->cmd_desc_phys_addr);
434 427
435 if (addr == NULL) { 428 if (addr == NULL) {
436 DPRINTK(ERR, "bad return from pci_alloc_consistent\n"); 429 DPRINTK(ERR, "bad return from pci_alloc_consistent\n");
@@ -1032,15 +1025,15 @@ int netxen_nic_get_board_info(struct netxen_adapter *adapter)
1032int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu) 1025int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
1033{ 1026{
1034 netxen_nic_write_w0(adapter, 1027 netxen_nic_write_w0(adapter,
1035 NETXEN_NIU_GB_MAX_FRAME_SIZE( 1028 NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
1036 physical_port[adapter->portnum]), new_mtu); 1029 new_mtu);
1037 return 0; 1030 return 0;
1038} 1031}
1039 1032
1040int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu) 1033int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
1041{ 1034{
1042 new_mtu += NETXEN_NIU_HDRSIZE + NETXEN_NIU_TLRSIZE; 1035 new_mtu += NETXEN_NIU_HDRSIZE + NETXEN_NIU_TLRSIZE;
1043 if (physical_port[adapter->portnum] == 0) 1036 if (adapter->physical_port == 0)
1044 netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, 1037 netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE,
1045 new_mtu); 1038 new_mtu);
1046 else 1039 else
@@ -1051,7 +1044,7 @@ int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
1051 1044
1052void netxen_nic_init_niu_gb(struct netxen_adapter *adapter) 1045void netxen_nic_init_niu_gb(struct netxen_adapter *adapter)
1053{ 1046{
1054 netxen_niu_gbe_init_port(adapter, physical_port[adapter->portnum]); 1047 netxen_niu_gbe_init_port(adapter, adapter->physical_port);
1055} 1048}
1056 1049
1057void 1050void
@@ -1127,7 +1120,6 @@ void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
1127 1120
1128void netxen_nic_flash_print(struct netxen_adapter *adapter) 1121void netxen_nic_flash_print(struct netxen_adapter *adapter)
1129{ 1122{
1130 int valid = 1;
1131 u32 fw_major = 0; 1123 u32 fw_major = 0;
1132 u32 fw_minor = 0; 1124 u32 fw_minor = 0;
1133 u32 fw_build = 0; 1125 u32 fw_build = 0;
@@ -1137,70 +1129,62 @@ void netxen_nic_flash_print(struct netxen_adapter *adapter)
1137 __le32 *ptr32; 1129 __le32 *ptr32;
1138 1130
1139 struct netxen_board_info *board_info = &(adapter->ahw.boardcfg); 1131 struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
1140 if (board_info->magic != NETXEN_BDINFO_MAGIC) { 1132
1141 printk 1133 adapter->driver_mismatch = 0;
1142 ("NetXen Unknown board config, Read 0x%x expected as 0x%x\n", 1134
1143 board_info->magic, NETXEN_BDINFO_MAGIC); 1135 ptr32 = (u32 *)&serial_num;
1144 valid = 0; 1136 addr = NETXEN_USER_START +
1145 } 1137 offsetof(struct netxen_new_user_info, serial_num);
1146 if (board_info->header_version != NETXEN_BDINFO_VERSION) { 1138 for (i = 0; i < 8; i++) {
1147 printk("NetXen Unknown board config version." 1139 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
1148 " Read %x, expected %x\n", 1140 printk("%s: ERROR reading %s board userarea.\n",
1149 board_info->header_version, NETXEN_BDINFO_VERSION); 1141 netxen_nic_driver_name,
1150 valid = 0; 1142 netxen_nic_driver_name);
1151 } 1143 adapter->driver_mismatch = 1;
1152 if (valid) { 1144 return;
1153 ptr32 = (u32 *)&serial_num;
1154 addr = NETXEN_USER_START +
1155 offsetof(struct netxen_new_user_info, serial_num);
1156 for (i = 0; i < 8; i++) {
1157 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
1158 printk("%s: ERROR reading %s board userarea.\n",
1159 netxen_nic_driver_name,
1160 netxen_nic_driver_name);
1161 return;
1162 }
1163 ptr32++;
1164 addr += sizeof(u32);
1165 } 1145 }
1146 ptr32++;
1147 addr += sizeof(u32);
1148 }
1149
1150 fw_major = readl(NETXEN_CRB_NORMALIZE(adapter,
1151 NETXEN_FW_VERSION_MAJOR));
1152 fw_minor = readl(NETXEN_CRB_NORMALIZE(adapter,
1153 NETXEN_FW_VERSION_MINOR));
1154 fw_build =
1155 readl(NETXEN_CRB_NORMALIZE(adapter, NETXEN_FW_VERSION_SUB));
1166 1156
1157 if (adapter->portnum == 0) {
1167 get_brd_name_by_type(board_info->board_type, brd_name); 1158 get_brd_name_by_type(board_info->board_type, brd_name);
1168 1159
1169 printk("NetXen %s Board S/N %s Chip id 0x%x\n", 1160 printk("NetXen %s Board S/N %s Chip id 0x%x\n",
1170 brd_name, serial_num, board_info->chip_id); 1161 brd_name, serial_num, board_info->chip_id);
1171 1162 printk("NetXen Firmware version %d.%d.%d\n", fw_major,
1172 printk("NetXen %s Board #%d, Chip id 0x%x\n", 1163 fw_minor, fw_build);
1173 board_info->board_type == 0x0b ? "XGB" : "GBE",
1174 board_info->board_num, board_info->chip_id);
1175 fw_major = readl(NETXEN_CRB_NORMALIZE(adapter,
1176 NETXEN_FW_VERSION_MAJOR));
1177 fw_minor = readl(NETXEN_CRB_NORMALIZE(adapter,
1178 NETXEN_FW_VERSION_MINOR));
1179 fw_build =
1180 readl(NETXEN_CRB_NORMALIZE(adapter, NETXEN_FW_VERSION_SUB));
1181
1182 printk("NetXen Firmware version %d.%d.%d\n", fw_major, fw_minor,
1183 fw_build);
1184 } 1164 }
1165
1185 if (fw_major != _NETXEN_NIC_LINUX_MAJOR) { 1166 if (fw_major != _NETXEN_NIC_LINUX_MAJOR) {
1186 printk(KERN_ERR "The mismatch in driver version and firmware "
1187 "version major number\n"
1188 "Driver version major number = %d \t"
1189 "Firmware version major number = %d \n",
1190 _NETXEN_NIC_LINUX_MAJOR, fw_major);
1191 adapter->driver_mismatch = 1; 1167 adapter->driver_mismatch = 1;
1192 } 1168 }
1193 if (fw_minor != _NETXEN_NIC_LINUX_MINOR && 1169 if (fw_minor != _NETXEN_NIC_LINUX_MINOR &&
1194 fw_minor != (_NETXEN_NIC_LINUX_MINOR + 1)) { 1170 fw_minor != (_NETXEN_NIC_LINUX_MINOR + 1)) {
1195 printk(KERN_ERR "The mismatch in driver version and firmware "
1196 "version minor number\n"
1197 "Driver version minor number = %d \t"
1198 "Firmware version minor number = %d \n",
1199 _NETXEN_NIC_LINUX_MINOR, fw_minor);
1200 adapter->driver_mismatch = 1; 1171 adapter->driver_mismatch = 1;
1201 } 1172 }
1202 if (adapter->driver_mismatch) 1173 if (adapter->driver_mismatch) {
1203 printk(KERN_INFO "Use the driver with version no %d.%d.xxx\n", 1174 printk(KERN_ERR "%s: driver and firmware version mismatch\n",
1204 fw_major, fw_minor); 1175 adapter->netdev->name);
1176 return;
1177 }
1178
1179 switch (adapter->ahw.board_type) {
1180 case NETXEN_NIC_GBE:
1181 dev_info(&adapter->pdev->dev, "%s: GbE port initialized\n",
1182 adapter->netdev->name);
1183 break;
1184 case NETXEN_NIC_XGBE:
1185 dev_info(&adapter->pdev->dev, "%s: XGbE port initialized\n",
1186 adapter->netdev->name);
1187 break;
1188 }
1205} 1189}
1206 1190
diff --git a/drivers/net/netxen/netxen_nic_init.c b/drivers/net/netxen/netxen_nic_init.c
index 45fa33e0cb9..70d1b22ced2 100644
--- a/drivers/net/netxen/netxen_nic_init.c
+++ b/drivers/net/netxen/netxen_nic_init.c
@@ -203,21 +203,6 @@ void netxen_initialize_adapter_sw(struct netxen_adapter *adapter)
203 } 203 }
204} 204}
205 205
206void netxen_initialize_adapter_hw(struct netxen_adapter *adapter)
207{
208 int ports = 0;
209 struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
210
211 if (netxen_nic_get_board_info(adapter) != 0)
212 printk("%s: Error getting board config info.\n",
213 netxen_nic_driver_name);
214 get_brd_port_by_type(board_info->board_type, &ports);
215 if (ports == 0)
216 printk(KERN_ERR "%s: Unknown board type\n",
217 netxen_nic_driver_name);
218 adapter->ahw.max_ports = ports;
219}
220
221void netxen_initialize_adapter_ops(struct netxen_adapter *adapter) 206void netxen_initialize_adapter_ops(struct netxen_adapter *adapter)
222{ 207{
223 switch (adapter->ahw.board_type) { 208 switch (adapter->ahw.board_type) {
@@ -765,18 +750,13 @@ int netxen_flash_unlock(struct netxen_adapter *adapter)
765 750
766int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose) 751int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
767{ 752{
768 int addr, val, status; 753 int addr, val;
769 int n, i; 754 int n, i;
770 int init_delay = 0; 755 int init_delay = 0;
771 struct crb_addr_pair *buf; 756 struct crb_addr_pair *buf;
772 u32 off; 757 u32 off;
773 758
774 /* resetall */ 759 /* resetall */
775 status = netxen_nic_get_board_info(adapter);
776 if (status)
777 printk("%s: netxen_pinit_from_rom: Error getting board info\n",
778 netxen_nic_driver_name);
779
780 netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 760 netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET,
781 NETXEN_ROMBUS_RESET); 761 NETXEN_ROMBUS_RESET);
782 762
@@ -860,10 +840,10 @@ int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
860 netxen_nic_pci_change_crbwindow(adapter, 1); 840 netxen_nic_pci_change_crbwindow(adapter, 1);
861 } 841 }
862 if (init_delay == 1) { 842 if (init_delay == 1) {
863 msleep(2000); 843 msleep(1000);
864 init_delay = 0; 844 init_delay = 0;
865 } 845 }
866 msleep(20); 846 msleep(1);
867 } 847 }
868 kfree(buf); 848 kfree(buf);
869 849
@@ -938,12 +918,28 @@ int netxen_initialize_adapter_offload(struct netxen_adapter *adapter)
938 918
939void netxen_free_adapter_offload(struct netxen_adapter *adapter) 919void netxen_free_adapter_offload(struct netxen_adapter *adapter)
940{ 920{
921 int i;
922
941 if (adapter->dummy_dma.addr) { 923 if (adapter->dummy_dma.addr) {
942 pci_free_consistent(adapter->ahw.pdev, 924 i = 100;
925 do {
926 if (dma_watchdog_shutdown_request(adapter) == 1)
927 break;
928 msleep(50);
929 if (dma_watchdog_shutdown_poll_result(adapter) == 1)
930 break;
931 } while (--i);
932
933 if (i) {
934 pci_free_consistent(adapter->ahw.pdev,
943 NETXEN_HOST_DUMMY_DMA_SIZE, 935 NETXEN_HOST_DUMMY_DMA_SIZE,
944 adapter->dummy_dma.addr, 936 adapter->dummy_dma.addr,
945 adapter->dummy_dma.phys_addr); 937 adapter->dummy_dma.phys_addr);
946 adapter->dummy_dma.addr = NULL; 938 adapter->dummy_dma.addr = NULL;
939 } else {
940 printk(KERN_ERR "%s: dma_watchdog_shutdown failed\n",
941 adapter->netdev->name);
942 }
947 } 943 }
948} 944}
949 945
diff --git a/drivers/net/netxen/netxen_nic_isr.c b/drivers/net/netxen/netxen_nic_isr.c
index f487615f406..96cec41f901 100644
--- a/drivers/net/netxen/netxen_nic_isr.c
+++ b/drivers/net/netxen/netxen_nic_isr.c
@@ -145,7 +145,7 @@ static void netxen_nic_isr_other(struct netxen_adapter *adapter)
145 145
146 /* verify the offset */ 146 /* verify the offset */
147 val = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_XG_STATE)); 147 val = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_XG_STATE));
148 val = val >> physical_port[adapter->portnum]; 148 val = val >> adapter->physical_port;
149 if (val == adapter->ahw.qg_linksup) 149 if (val == adapter->ahw.qg_linksup)
150 return; 150 return;
151 151
@@ -199,7 +199,7 @@ void netxen_nic_xgbe_handle_phy_intr(struct netxen_adapter *adapter)
199 199
200 /* WINDOW = 1 */ 200 /* WINDOW = 1 */
201 val = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_XG_STATE)); 201 val = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_XG_STATE));
202 val >>= (physical_port[adapter->portnum] * 8); 202 val >>= (adapter->physical_port * 8);
203 val &= 0xff; 203 val &= 0xff;
204 204
205 if (adapter->ahw.xg_linkup == 1 && val != XG_LINK_UP) { 205 if (adapter->ahw.xg_linkup == 1 && val != XG_LINK_UP) {
diff --git a/drivers/net/netxen/netxen_nic_main.c b/drivers/net/netxen/netxen_nic_main.c
index 7144c255ce5..6797ed069f1 100644
--- a/drivers/net/netxen/netxen_nic_main.c
+++ b/drivers/net/netxen/netxen_nic_main.c
@@ -70,17 +70,15 @@ static void netxen_nic_poll_controller(struct net_device *netdev);
70static irqreturn_t netxen_intr(int irq, void *data); 70static irqreturn_t netxen_intr(int irq, void *data);
71static irqreturn_t netxen_msi_intr(int irq, void *data); 71static irqreturn_t netxen_msi_intr(int irq, void *data);
72 72
73int physical_port[] = {0, 1, 2, 3};
74
75/* PCI Device ID Table */ 73/* PCI Device ID Table */
76static struct pci_device_id netxen_pci_tbl[] __devinitdata = { 74static struct pci_device_id netxen_pci_tbl[] __devinitdata = {
77 {PCI_DEVICE(0x4040, 0x0001)}, 75 {PCI_DEVICE(0x4040, 0x0001), PCI_DEVICE_CLASS(0x020000, ~0)},
78 {PCI_DEVICE(0x4040, 0x0002)}, 76 {PCI_DEVICE(0x4040, 0x0002), PCI_DEVICE_CLASS(0x020000, ~0)},
79 {PCI_DEVICE(0x4040, 0x0003)}, 77 {PCI_DEVICE(0x4040, 0x0003), PCI_DEVICE_CLASS(0x020000, ~0)},
80 {PCI_DEVICE(0x4040, 0x0004)}, 78 {PCI_DEVICE(0x4040, 0x0004), PCI_DEVICE_CLASS(0x020000, ~0)},
81 {PCI_DEVICE(0x4040, 0x0005)}, 79 {PCI_DEVICE(0x4040, 0x0005), PCI_DEVICE_CLASS(0x020000, ~0)},
82 {PCI_DEVICE(0x4040, 0x0024)}, 80 {PCI_DEVICE(0x4040, 0x0024), PCI_DEVICE_CLASS(0x020000, ~0)},
83 {PCI_DEVICE(0x4040, 0x0025)}, 81 {PCI_DEVICE(0x4040, 0x0025), PCI_DEVICE_CLASS(0x020000, ~0)},
84 {0,} 82 {0,}
85}; 83};
86 84
@@ -288,10 +286,11 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
288 int pci_func_id = PCI_FUNC(pdev->devfn); 286 int pci_func_id = PCI_FUNC(pdev->devfn);
289 DECLARE_MAC_BUF(mac); 287 DECLARE_MAC_BUF(mac);
290 288
291 printk(KERN_INFO "%s \n", netxen_nic_driver_string); 289 if (pci_func_id == 0)
290 printk(KERN_INFO "%s \n", netxen_nic_driver_string);
292 291
293 if (pdev->class != 0x020000) { 292 if (pdev->class != 0x020000) {
294 printk(KERN_ERR"NetXen function %d, class %x will not " 293 printk(KERN_DEBUG "NetXen function %d, class %x will not "
295 "be enabled.\n",pci_func_id, pdev->class); 294 "be enabled.\n",pci_func_id, pdev->class);
296 return -ENODEV; 295 return -ENODEV;
297 } 296 }
@@ -450,8 +449,12 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
450 */ 449 */
451 adapter->curr_window = 255; 450 adapter->curr_window = 255;
452 451
453 /* initialize the adapter */ 452 if (netxen_nic_get_board_info(adapter) != 0) {
454 netxen_initialize_adapter_hw(adapter); 453 printk("%s: Error getting board config info.\n",
454 netxen_nic_driver_name);
455 err = -EIO;
456 goto err_out_iounmap;
457 }
455 458
456 /* 459 /*
457 * Adapter in our case is quad port so initialize it before 460 * Adapter in our case is quad port so initialize it before
@@ -530,17 +533,15 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
530 netxen_initialize_adapter_sw(adapter); /* initialize the buffers in adapter */ 533 netxen_initialize_adapter_sw(adapter); /* initialize the buffers in adapter */
531 534
532 /* Mezz cards have PCI function 0,2,3 enabled */ 535 /* Mezz cards have PCI function 0,2,3 enabled */
533 if ((adapter->ahw.boardcfg.board_type == NETXEN_BRDTYPE_P2_SB31_10G_IMEZ) 536 switch (adapter->ahw.boardcfg.board_type) {
534 && (pci_func_id >= 2)) 537 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
538 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
539 if (pci_func_id >= 2)
535 adapter->portnum = pci_func_id - 2; 540 adapter->portnum = pci_func_id - 2;
536 541 break;
537#ifdef CONFIG_IA64 542 default:
538 if(adapter->portnum == 0) { 543 break;
539 netxen_pinit_from_rom(adapter, 0);
540 udelay(500);
541 netxen_load_firmware(adapter);
542 } 544 }
543#endif
544 545
545 init_timer(&adapter->watchdog_timer); 546 init_timer(&adapter->watchdog_timer);
546 adapter->ahw.xg_linkup = 0; 547 adapter->ahw.xg_linkup = 0;
@@ -613,11 +614,18 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
613 err = -ENODEV; 614 err = -ENODEV;
614 goto err_out_free_dev; 615 goto err_out_free_dev;
615 } 616 }
617 } else {
618 writel(0, NETXEN_CRB_NORMALIZE(adapter,
619 CRB_CMDPEG_STATE));
620 netxen_pinit_from_rom(adapter, 0);
621 msleep(1);
622 netxen_load_firmware(adapter);
623 netxen_phantom_init(adapter, NETXEN_NIC_PEG_TUNE);
616 } 624 }
617 625
618 /* clear the register for future unloads/loads */ 626 /* clear the register for future unloads/loads */
619 writel(0, NETXEN_CRB_NORMALIZE(adapter, NETXEN_CAM_RAM(0x1fc))); 627 writel(0, NETXEN_CRB_NORMALIZE(adapter, NETXEN_CAM_RAM(0x1fc)));
620 printk(KERN_INFO "State: 0x%0x\n", 628 dev_info(&pdev->dev, "cmdpeg state: 0x%0x\n",
621 readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE))); 629 readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE)));
622 630
623 /* 631 /*
@@ -639,9 +647,10 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
639 /* 647 /*
640 * See if the firmware gave us a virtual-physical port mapping. 648 * See if the firmware gave us a virtual-physical port mapping.
641 */ 649 */
650 adapter->physical_port = adapter->portnum;
642 i = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_V2P(adapter->portnum))); 651 i = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_V2P(adapter->portnum)));
643 if (i != 0x55555555) 652 if (i != 0x55555555)
644 physical_port[adapter->portnum] = i; 653 adapter->physical_port = i;
645 654
646 netif_carrier_off(netdev); 655 netif_carrier_off(netdev);
647 netif_stop_queue(netdev); 656 netif_stop_queue(netdev);
@@ -654,22 +663,9 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
654 goto err_out_free_dev; 663 goto err_out_free_dev;
655 } 664 }
656 665
666 netxen_nic_flash_print(adapter);
657 pci_set_drvdata(pdev, adapter); 667 pci_set_drvdata(pdev, adapter);
658 668
659 switch (adapter->ahw.board_type) {
660 case NETXEN_NIC_GBE:
661 printk(KERN_INFO "%s: QUAD GbE board initialized\n",
662 netxen_nic_driver_name);
663 break;
664
665 case NETXEN_NIC_XGBE:
666 printk(KERN_INFO "%s: XGbE board initialized\n",
667 netxen_nic_driver_name);
668 break;
669 }
670
671 adapter->driver_mismatch = 0;
672
673 return 0; 669 return 0;
674 670
675err_out_free_dev: 671err_out_free_dev:
@@ -760,55 +756,8 @@ static void __devexit netxen_nic_remove(struct pci_dev *pdev)
760 756
761 vfree(adapter->cmd_buf_arr); 757 vfree(adapter->cmd_buf_arr);
762 758
763 if (adapter->portnum == 0) { 759 if (adapter->portnum == 0)
764 if (init_firmware_done) { 760 netxen_free_adapter_offload(adapter);
765 i = 100;
766 do {
767 if (dma_watchdog_shutdown_request(adapter) == 1)
768 break;
769 msleep(100);
770 if (dma_watchdog_shutdown_poll_result(adapter) == 1)
771 break;
772 } while (--i);
773
774 if (i == 0)
775 printk(KERN_ERR "%s: dma_watchdog_shutdown failed\n",
776 netdev->name);
777
778 /* clear the register for future unloads/loads */
779 writel(0, NETXEN_CRB_NORMALIZE(adapter, NETXEN_CAM_RAM(0x1fc)));
780 printk(KERN_INFO "State: 0x%0x\n",
781 readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE)));
782
783 /* leave the hw in the same state as reboot */
784 writel(0, NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
785 netxen_pinit_from_rom(adapter, 0);
786 msleep(1);
787 netxen_load_firmware(adapter);
788 netxen_phantom_init(adapter, NETXEN_NIC_PEG_TUNE);
789 }
790
791 /* clear the register for future unloads/loads */
792 writel(0, NETXEN_CRB_NORMALIZE(adapter, NETXEN_CAM_RAM(0x1fc)));
793 printk(KERN_INFO "State: 0x%0x\n",
794 readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE)));
795
796 i = 100;
797 do {
798 if (dma_watchdog_shutdown_request(adapter) == 1)
799 break;
800 msleep(100);
801 if (dma_watchdog_shutdown_poll_result(adapter) == 1)
802 break;
803 } while (--i);
804
805 if (i) {
806 netxen_free_adapter_offload(adapter);
807 } else {
808 printk(KERN_ERR "%s: dma_watchdog_shutdown failed\n",
809 netdev->name);
810 }
811 }
812 761
813 if (adapter->irq) 762 if (adapter->irq)
814 free_irq(adapter->irq, adapter); 763 free_irq(adapter->irq, adapter);
@@ -840,13 +789,15 @@ static int netxen_nic_open(struct net_device *netdev)
840 irq_handler_t handler; 789 irq_handler_t handler;
841 unsigned long flags = IRQF_SAMPLE_RANDOM; 790 unsigned long flags = IRQF_SAMPLE_RANDOM;
842 791
792 if (adapter->driver_mismatch)
793 return -EIO;
794
843 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC) { 795 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC) {
844 err = netxen_init_firmware(adapter); 796 err = netxen_init_firmware(adapter);
845 if (err != 0) { 797 if (err != 0) {
846 printk(KERN_ERR "Failed to init firmware\n"); 798 printk(KERN_ERR "Failed to init firmware\n");
847 return -EIO; 799 return -EIO;
848 } 800 }
849 netxen_nic_flash_print(adapter);
850 801
851 /* setup all the resources for the Phantom... */ 802 /* setup all the resources for the Phantom... */
852 /* this include the descriptors for rcv, tx, and status */ 803 /* this include the descriptors for rcv, tx, and status */
@@ -895,14 +846,12 @@ static int netxen_nic_open(struct net_device *netdev)
895 if (adapter->set_mtu) 846 if (adapter->set_mtu)
896 adapter->set_mtu(adapter, netdev->mtu); 847 adapter->set_mtu(adapter, netdev->mtu);
897 848
898 if (!adapter->driver_mismatch) 849 mod_timer(&adapter->watchdog_timer, jiffies);
899 mod_timer(&adapter->watchdog_timer, jiffies);
900 850
901 napi_enable(&adapter->napi); 851 napi_enable(&adapter->napi);
902 netxen_nic_enable_int(adapter); 852 netxen_nic_enable_int(adapter);
903 853
904 if (!adapter->driver_mismatch) 854 netif_start_queue(netdev);
905 netif_start_queue(netdev);
906 855
907 return 0; 856 return 0;
908} 857}
diff --git a/drivers/net/netxen/netxen_nic_niu.c b/drivers/net/netxen/netxen_nic_niu.c
index 1c852a76c80..a3bc7cc67a6 100644
--- a/drivers/net/netxen/netxen_nic_niu.c
+++ b/drivers/net/netxen/netxen_nic_niu.c
@@ -94,7 +94,7 @@ int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
94 long timeout = 0; 94 long timeout = 0;
95 long result = 0; 95 long result = 0;
96 long restore = 0; 96 long restore = 0;
97 long phy = physical_port[adapter->portnum]; 97 long phy = adapter->physical_port;
98 __u32 address; 98 __u32 address;
99 __u32 command; 99 __u32 command;
100 __u32 status; 100 __u32 status;
@@ -190,7 +190,7 @@ int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter, long reg,
190 long timeout = 0; 190 long timeout = 0;
191 long result = 0; 191 long result = 0;
192 long restore = 0; 192 long restore = 0;
193 long phy = physical_port[adapter->portnum]; 193 long phy = adapter->physical_port;
194 __u32 address; 194 __u32 address;
195 __u32 command; 195 __u32 command;
196 __u32 status; 196 __u32 status;
@@ -456,7 +456,7 @@ int netxen_niu_gbe_init_port(struct netxen_adapter *adapter, int port)
456 456
457int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port) 457int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port)
458{ 458{
459 u32 portnum = physical_port[adapter->portnum]; 459 u32 portnum = adapter->physical_port;
460 460
461 netxen_crb_writelit_adapter(adapter, 461 netxen_crb_writelit_adapter(adapter,
462 NETXEN_NIU_XGE_CONFIG_1+(0x10000*portnum), 0x1447); 462 NETXEN_NIU_XGE_CONFIG_1+(0x10000*portnum), 0x1447);
@@ -573,7 +573,7 @@ static int netxen_niu_macaddr_get(struct netxen_adapter *adapter,
573{ 573{
574 u32 stationhigh; 574 u32 stationhigh;
575 u32 stationlow; 575 u32 stationlow;
576 int phy = physical_port[adapter->portnum]; 576 int phy = adapter->physical_port;
577 u8 val[8]; 577 u8 val[8];
578 578
579 if (addr == NULL) 579 if (addr == NULL)
@@ -604,7 +604,7 @@ int netxen_niu_macaddr_set(struct netxen_adapter *adapter,
604{ 604{
605 u8 temp[4]; 605 u8 temp[4];
606 u32 val; 606 u32 val;
607 int phy = physical_port[adapter->portnum]; 607 int phy = adapter->physical_port;
608 unsigned char mac_addr[6]; 608 unsigned char mac_addr[6];
609 int i; 609 int i;
610 DECLARE_MAC_BUF(mac); 610 DECLARE_MAC_BUF(mac);
@@ -724,7 +724,7 @@ int netxen_niu_enable_gbe_port(struct netxen_adapter *adapter,
724int netxen_niu_disable_gbe_port(struct netxen_adapter *adapter) 724int netxen_niu_disable_gbe_port(struct netxen_adapter *adapter)
725{ 725{
726 __u32 mac_cfg0; 726 __u32 mac_cfg0;
727 u32 port = physical_port[adapter->portnum]; 727 u32 port = adapter->physical_port;
728 728
729 if (port > NETXEN_NIU_MAX_GBE_PORTS) 729 if (port > NETXEN_NIU_MAX_GBE_PORTS)
730 return -EINVAL; 730 return -EINVAL;
@@ -740,7 +740,7 @@ int netxen_niu_disable_gbe_port(struct netxen_adapter *adapter)
740int netxen_niu_disable_xg_port(struct netxen_adapter *adapter) 740int netxen_niu_disable_xg_port(struct netxen_adapter *adapter)
741{ 741{
742 __u32 mac_cfg; 742 __u32 mac_cfg;
743 u32 port = physical_port[adapter->portnum]; 743 u32 port = adapter->physical_port;
744 744
745 if (port > NETXEN_NIU_MAX_XG_PORTS) 745 if (port > NETXEN_NIU_MAX_XG_PORTS)
746 return -EINVAL; 746 return -EINVAL;
@@ -757,7 +757,7 @@ int netxen_niu_set_promiscuous_mode(struct netxen_adapter *adapter,
757 netxen_niu_prom_mode_t mode) 757 netxen_niu_prom_mode_t mode)
758{ 758{
759 __u32 reg; 759 __u32 reg;
760 u32 port = physical_port[adapter->portnum]; 760 u32 port = adapter->physical_port;
761 761
762 if (port > NETXEN_NIU_MAX_GBE_PORTS) 762 if (port > NETXEN_NIU_MAX_GBE_PORTS)
763 return -EINVAL; 763 return -EINVAL;
@@ -814,7 +814,7 @@ int netxen_niu_set_promiscuous_mode(struct netxen_adapter *adapter,
814int netxen_niu_xg_macaddr_set(struct netxen_adapter *adapter, 814int netxen_niu_xg_macaddr_set(struct netxen_adapter *adapter,
815 netxen_ethernet_macaddr_t addr) 815 netxen_ethernet_macaddr_t addr)
816{ 816{
817 int phy = physical_port[adapter->portnum]; 817 int phy = adapter->physical_port;
818 u8 temp[4]; 818 u8 temp[4];
819 u32 val; 819 u32 val;
820 820
@@ -867,7 +867,7 @@ int netxen_niu_xg_macaddr_set(struct netxen_adapter *adapter,
867int netxen_niu_xg_macaddr_get(struct netxen_adapter *adapter, 867int netxen_niu_xg_macaddr_get(struct netxen_adapter *adapter,
868 netxen_ethernet_macaddr_t * addr) 868 netxen_ethernet_macaddr_t * addr)
869{ 869{
870 int phy = physical_port[adapter->portnum]; 870 int phy = adapter->physical_port;
871 u32 stationhigh; 871 u32 stationhigh;
872 u32 stationlow; 872 u32 stationlow;
873 u8 val[8]; 873 u8 val[8];
@@ -896,7 +896,7 @@ int netxen_niu_xg_set_promiscuous_mode(struct netxen_adapter *adapter,
896 netxen_niu_prom_mode_t mode) 896 netxen_niu_prom_mode_t mode)
897{ 897{
898 __u32 reg; 898 __u32 reg;
899 u32 port = physical_port[adapter->portnum]; 899 u32 port = adapter->physical_port;
900 900
901 if (port > NETXEN_NIU_MAX_XG_PORTS) 901 if (port > NETXEN_NIU_MAX_XG_PORTS)
902 return -EINVAL; 902 return -EINVAL;
diff --git a/drivers/net/pppoe.c b/drivers/net/pppoe.c
index bafb69b6f7c..fc6f4b8c64b 100644
--- a/drivers/net/pppoe.c
+++ b/drivers/net/pppoe.c
@@ -942,7 +942,7 @@ static int pppoe_recvmsg(struct kiocb *iocb, struct socket *sock,
942 m->msg_namelen = 0; 942 m->msg_namelen = 0;
943 943
944 if (skb) { 944 if (skb) {
945 total_len = min(total_len, skb->len); 945 total_len = min_t(size_t, total_len, skb->len);
946 error = skb_copy_datagram_iovec(skb, 0, m->msg_iov, total_len); 946 error = skb_copy_datagram_iovec(skb, 0, m->msg_iov, total_len);
947 if (error == 0) 947 if (error == 0)
948 error = total_len; 948 error = total_len;
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
index 62436b3a18c..c8a5ef2d75f 100644
--- a/drivers/net/sky2.c
+++ b/drivers/net/sky2.c
@@ -118,6 +118,7 @@ static const struct pci_device_id sky2_id_table[] = {
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */ 118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */ 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */ 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */ 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */ 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */ 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
diff --git a/drivers/net/tun.c b/drivers/net/tun.c
index 0ce07a339c7..7ab94c825b5 100644
--- a/drivers/net/tun.c
+++ b/drivers/net/tun.c
@@ -313,6 +313,21 @@ static __inline__ ssize_t tun_get_user(struct tun_struct *tun, struct iovec *iv,
313 313
314 switch (tun->flags & TUN_TYPE_MASK) { 314 switch (tun->flags & TUN_TYPE_MASK) {
315 case TUN_TUN_DEV: 315 case TUN_TUN_DEV:
316 if (tun->flags & TUN_NO_PI) {
317 switch (skb->data[0] & 0xf0) {
318 case 0x40:
319 pi.proto = htons(ETH_P_IP);
320 break;
321 case 0x60:
322 pi.proto = htons(ETH_P_IPV6);
323 break;
324 default:
325 tun->dev->stats.rx_dropped++;
326 kfree_skb(skb);
327 return -EINVAL;
328 }
329 }
330
316 skb_reset_mac_header(skb); 331 skb_reset_mac_header(skb);
317 skb->protocol = pi.proto; 332 skb->protocol = pi.proto;
318 skb->dev = tun->dev; 333 skb->dev = tun->dev;
diff --git a/drivers/net/wireless/b43/b43.h b/drivers/net/wireless/b43/b43.h
index dfa4bdd5597..d3db298c05f 100644
--- a/drivers/net/wireless/b43/b43.h
+++ b/drivers/net/wireless/b43/b43.h
@@ -630,7 +630,6 @@ struct b43_pio {
630 630
631/* Context information for a noise calculation (Link Quality). */ 631/* Context information for a noise calculation (Link Quality). */
632struct b43_noise_calculation { 632struct b43_noise_calculation {
633 u8 channel_at_start;
634 bool calculation_running; 633 bool calculation_running;
635 u8 nr_samples; 634 u8 nr_samples;
636 s8 samples[8][4]; 635 s8 samples[8][4];
diff --git a/drivers/net/wireless/b43/dma.c b/drivers/net/wireless/b43/dma.c
index 6dcbb3c87e7..e23f2f172bd 100644
--- a/drivers/net/wireless/b43/dma.c
+++ b/drivers/net/wireless/b43/dma.c
@@ -795,24 +795,49 @@ struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
795{ 795{
796 struct b43_dmaring *ring; 796 struct b43_dmaring *ring;
797 int err; 797 int err;
798 int nr_slots;
799 dma_addr_t dma_test; 798 dma_addr_t dma_test;
800 799
801 ring = kzalloc(sizeof(*ring), GFP_KERNEL); 800 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
802 if (!ring) 801 if (!ring)
803 goto out; 802 goto out;
804 ring->type = type;
805 803
806 nr_slots = B43_RXRING_SLOTS; 804 ring->nr_slots = B43_RXRING_SLOTS;
807 if (for_tx) 805 if (for_tx)
808 nr_slots = B43_TXRING_SLOTS; 806 ring->nr_slots = B43_TXRING_SLOTS;
809 807
810 ring->meta = kcalloc(nr_slots, sizeof(struct b43_dmadesc_meta), 808 ring->meta = kcalloc(ring->nr_slots, sizeof(struct b43_dmadesc_meta),
811 GFP_KERNEL); 809 GFP_KERNEL);
812 if (!ring->meta) 810 if (!ring->meta)
813 goto err_kfree_ring; 811 goto err_kfree_ring;
812
813 ring->type = type;
814 ring->dev = dev;
815 ring->mmio_base = b43_dmacontroller_base(type, controller_index);
816 ring->index = controller_index;
817 if (type == B43_DMA_64BIT)
818 ring->ops = &dma64_ops;
819 else
820 ring->ops = &dma32_ops;
814 if (for_tx) { 821 if (for_tx) {
815 ring->txhdr_cache = kcalloc(nr_slots, 822 ring->tx = 1;
823 ring->current_slot = -1;
824 } else {
825 if (ring->index == 0) {
826 ring->rx_buffersize = B43_DMA0_RX_BUFFERSIZE;
827 ring->frameoffset = B43_DMA0_RX_FRAMEOFFSET;
828 } else if (ring->index == 3) {
829 ring->rx_buffersize = B43_DMA3_RX_BUFFERSIZE;
830 ring->frameoffset = B43_DMA3_RX_FRAMEOFFSET;
831 } else
832 B43_WARN_ON(1);
833 }
834 spin_lock_init(&ring->lock);
835#ifdef CONFIG_B43_DEBUG
836 ring->last_injected_overflow = jiffies;
837#endif
838
839 if (for_tx) {
840 ring->txhdr_cache = kcalloc(ring->nr_slots,
816 b43_txhdr_size(dev), 841 b43_txhdr_size(dev),
817 GFP_KERNEL); 842 GFP_KERNEL);
818 if (!ring->txhdr_cache) 843 if (!ring->txhdr_cache)
@@ -828,7 +853,7 @@ struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
828 b43_txhdr_size(dev), 1)) { 853 b43_txhdr_size(dev), 1)) {
829 /* ugh realloc */ 854 /* ugh realloc */
830 kfree(ring->txhdr_cache); 855 kfree(ring->txhdr_cache);
831 ring->txhdr_cache = kcalloc(nr_slots, 856 ring->txhdr_cache = kcalloc(ring->nr_slots,
832 b43_txhdr_size(dev), 857 b43_txhdr_size(dev),
833 GFP_KERNEL | GFP_DMA); 858 GFP_KERNEL | GFP_DMA);
834 if (!ring->txhdr_cache) 859 if (!ring->txhdr_cache)
@@ -853,32 +878,6 @@ struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
853 DMA_TO_DEVICE); 878 DMA_TO_DEVICE);
854 } 879 }
855 880
856 ring->dev = dev;
857 ring->nr_slots = nr_slots;
858 ring->mmio_base = b43_dmacontroller_base(type, controller_index);
859 ring->index = controller_index;
860 if (type == B43_DMA_64BIT)
861 ring->ops = &dma64_ops;
862 else
863 ring->ops = &dma32_ops;
864 if (for_tx) {
865 ring->tx = 1;
866 ring->current_slot = -1;
867 } else {
868 if (ring->index == 0) {
869 ring->rx_buffersize = B43_DMA0_RX_BUFFERSIZE;
870 ring->frameoffset = B43_DMA0_RX_FRAMEOFFSET;
871 } else if (ring->index == 3) {
872 ring->rx_buffersize = B43_DMA3_RX_BUFFERSIZE;
873 ring->frameoffset = B43_DMA3_RX_FRAMEOFFSET;
874 } else
875 B43_WARN_ON(1);
876 }
877 spin_lock_init(&ring->lock);
878#ifdef CONFIG_B43_DEBUG
879 ring->last_injected_overflow = jiffies;
880#endif
881
882 err = alloc_ringmemory(ring); 881 err = alloc_ringmemory(ring);
883 if (err) 882 if (err)
884 goto err_kfree_txhdr_cache; 883 goto err_kfree_txhdr_cache;
diff --git a/drivers/net/wireless/b43/main.c b/drivers/net/wireless/b43/main.c
index 6c3d9ea0a9f..fa4b0d8b74a 100644
--- a/drivers/net/wireless/b43/main.c
+++ b/drivers/net/wireless/b43/main.c
@@ -1145,7 +1145,6 @@ static void b43_generate_noise_sample(struct b43_wldev *dev)
1145 b43_jssi_write(dev, 0x7F7F7F7F); 1145 b43_jssi_write(dev, 0x7F7F7F7F);
1146 b43_write32(dev, B43_MMIO_MACCMD, 1146 b43_write32(dev, B43_MMIO_MACCMD,
1147 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE); 1147 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1148 B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel);
1149} 1148}
1150 1149
1151static void b43_calculate_link_quality(struct b43_wldev *dev) 1150static void b43_calculate_link_quality(struct b43_wldev *dev)
@@ -1154,7 +1153,6 @@ static void b43_calculate_link_quality(struct b43_wldev *dev)
1154 1153
1155 if (dev->noisecalc.calculation_running) 1154 if (dev->noisecalc.calculation_running)
1156 return; 1155 return;
1157 dev->noisecalc.channel_at_start = dev->phy.channel;
1158 dev->noisecalc.calculation_running = 1; 1156 dev->noisecalc.calculation_running = 1;
1159 dev->noisecalc.nr_samples = 0; 1157 dev->noisecalc.nr_samples = 0;
1160 1158
@@ -1171,9 +1169,16 @@ static void handle_irq_noise(struct b43_wldev *dev)
1171 1169
1172 /* Bottom half of Link Quality calculation. */ 1170 /* Bottom half of Link Quality calculation. */
1173 1171
1172 /* Possible race condition: It might be possible that the user
1173 * changed to a different channel in the meantime since we
1174 * started the calculation. We ignore that fact, since it's
1175 * not really that much of a problem. The background noise is
1176 * an estimation only anyway. Slightly wrong results will get damped
1177 * by the averaging of the 8 sample rounds. Additionally the
1178 * value is shortlived. So it will be replaced by the next noise
1179 * calculation round soon. */
1180
1174 B43_WARN_ON(!dev->noisecalc.calculation_running); 1181 B43_WARN_ON(!dev->noisecalc.calculation_running);
1175 if (dev->noisecalc.channel_at_start != phy->channel)
1176 goto drop_calculation;
1177 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev)); 1182 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1178 if (noise[0] == 0x7F || noise[1] == 0x7F || 1183 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1179 noise[2] == 0x7F || noise[3] == 0x7F) 1184 noise[2] == 0x7F || noise[3] == 0x7F)
@@ -1214,11 +1219,10 @@ static void handle_irq_noise(struct b43_wldev *dev)
1214 average -= 48; 1219 average -= 48;
1215 1220
1216 dev->stats.link_noise = average; 1221 dev->stats.link_noise = average;
1217 drop_calculation:
1218 dev->noisecalc.calculation_running = 0; 1222 dev->noisecalc.calculation_running = 0;
1219 return; 1223 return;
1220 } 1224 }
1221 generate_new: 1225generate_new:
1222 b43_generate_noise_sample(dev); 1226 b43_generate_noise_sample(dev);
1223} 1227}
1224 1228
diff --git a/drivers/net/wireless/rt2x00/Kconfig b/drivers/net/wireless/rt2x00/Kconfig
index ab1029e7988..2d611876bbe 100644
--- a/drivers/net/wireless/rt2x00/Kconfig
+++ b/drivers/net/wireless/rt2x00/Kconfig
@@ -32,12 +32,13 @@ config RT2X00_LIB_FIRMWARE
32config RT2X00_LIB_RFKILL 32config RT2X00_LIB_RFKILL
33 boolean 33 boolean
34 depends on RT2X00_LIB 34 depends on RT2X00_LIB
35 depends on INPUT
35 select RFKILL 36 select RFKILL
36 select INPUT_POLLDEV 37 select INPUT_POLLDEV
37 38
38config RT2X00_LIB_LEDS 39config RT2X00_LIB_LEDS
39 boolean 40 boolean
40 depends on RT2X00_LIB 41 depends on RT2X00_LIB && NEW_LEDS
41 42
42config RT2400PCI 43config RT2400PCI
43 tristate "Ralink rt2400 pci/pcmcia support" 44 tristate "Ralink rt2400 pci/pcmcia support"
@@ -51,7 +52,7 @@ config RT2400PCI
51 52
52config RT2400PCI_RFKILL 53config RT2400PCI_RFKILL
53 bool "RT2400 rfkill support" 54 bool "RT2400 rfkill support"
54 depends on RT2400PCI 55 depends on RT2400PCI && INPUT
55 select RT2X00_LIB_RFKILL 56 select RT2X00_LIB_RFKILL
56 ---help--- 57 ---help---
57 This adds support for integrated rt2400 devices that feature a 58 This adds support for integrated rt2400 devices that feature a
@@ -60,7 +61,7 @@ config RT2400PCI_RFKILL
60 61
61config RT2400PCI_LEDS 62config RT2400PCI_LEDS
62 bool "RT2400 leds support" 63 bool "RT2400 leds support"
63 depends on RT2400PCI 64 depends on RT2400PCI && NEW_LEDS
64 select LEDS_CLASS 65 select LEDS_CLASS
65 select RT2X00_LIB_LEDS 66 select RT2X00_LIB_LEDS
66 ---help--- 67 ---help---
@@ -78,7 +79,7 @@ config RT2500PCI
78 79
79config RT2500PCI_RFKILL 80config RT2500PCI_RFKILL
80 bool "RT2500 rfkill support" 81 bool "RT2500 rfkill support"
81 depends on RT2500PCI 82 depends on RT2500PCI && INPUT
82 select RT2X00_LIB_RFKILL 83 select RT2X00_LIB_RFKILL
83 ---help--- 84 ---help---
84 This adds support for integrated rt2500 devices that feature a 85 This adds support for integrated rt2500 devices that feature a
@@ -87,7 +88,7 @@ config RT2500PCI_RFKILL
87 88
88config RT2500PCI_LEDS 89config RT2500PCI_LEDS
89 bool "RT2500 leds support" 90 bool "RT2500 leds support"
90 depends on RT2500PCI 91 depends on RT2500PCI && NEW_LEDS
91 select LEDS_CLASS 92 select LEDS_CLASS
92 select RT2X00_LIB_LEDS 93 select RT2X00_LIB_LEDS
93 ---help--- 94 ---help---
@@ -107,7 +108,7 @@ config RT61PCI
107 108
108config RT61PCI_RFKILL 109config RT61PCI_RFKILL
109 bool "RT61 rfkill support" 110 bool "RT61 rfkill support"
110 depends on RT61PCI 111 depends on RT61PCI && INPUT
111 select RT2X00_LIB_RFKILL 112 select RT2X00_LIB_RFKILL
112 ---help--- 113 ---help---
113 This adds support for integrated rt61 devices that feature a 114 This adds support for integrated rt61 devices that feature a
@@ -116,7 +117,7 @@ config RT61PCI_RFKILL
116 117
117config RT61PCI_LEDS 118config RT61PCI_LEDS
118 bool "RT61 leds support" 119 bool "RT61 leds support"
119 depends on RT61PCI 120 depends on RT61PCI && NEW_LEDS
120 select LEDS_CLASS 121 select LEDS_CLASS
121 select RT2X00_LIB_LEDS 122 select RT2X00_LIB_LEDS
122 ---help--- 123 ---help---
@@ -133,7 +134,7 @@ config RT2500USB
133 134
134config RT2500USB_LEDS 135config RT2500USB_LEDS
135 bool "RT2500 leds support" 136 bool "RT2500 leds support"
136 depends on RT2500USB 137 depends on RT2500USB && NEW_LEDS
137 select LEDS_CLASS 138 select LEDS_CLASS
138 select RT2X00_LIB_LEDS 139 select RT2X00_LIB_LEDS
139 ---help--- 140 ---help---
@@ -152,7 +153,7 @@ config RT73USB
152 153
153config RT73USB_LEDS 154config RT73USB_LEDS
154 bool "RT73 leds support" 155 bool "RT73 leds support"
155 depends on RT73USB 156 depends on RT73USB && NEW_LEDS
156 select LEDS_CLASS 157 select LEDS_CLASS
157 select RT2X00_LIB_LEDS 158 select RT2X00_LIB_LEDS
158 ---help--- 159 ---help---
diff --git a/drivers/net/wireless/rt2x00/rt2x00pci.c b/drivers/net/wireless/rt2x00/rt2x00pci.c
index 971af2546b5..60893de3bf8 100644
--- a/drivers/net/wireless/rt2x00/rt2x00pci.c
+++ b/drivers/net/wireless/rt2x00/rt2x00pci.c
@@ -412,8 +412,7 @@ int rt2x00pci_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
412 if (pci_set_mwi(pci_dev)) 412 if (pci_set_mwi(pci_dev))
413 ERROR_PROBE("MWI not available.\n"); 413 ERROR_PROBE("MWI not available.\n");
414 414
415 if (pci_set_dma_mask(pci_dev, DMA_64BIT_MASK) && 415 if (pci_set_dma_mask(pci_dev, DMA_32BIT_MASK)) {
416 pci_set_dma_mask(pci_dev, DMA_32BIT_MASK)) {
417 ERROR_PROBE("PCI DMA not supported.\n"); 416 ERROR_PROBE("PCI DMA not supported.\n");
418 retval = -EIO; 417 retval = -EIO;
419 goto exit_disable_device; 418 goto exit_disable_device;
diff --git a/drivers/net/wireless/rt2x00/rt2x00usb.c b/drivers/net/wireless/rt2x00/rt2x00usb.c
index 5a331674dcb..e5ceae805b5 100644
--- a/drivers/net/wireless/rt2x00/rt2x00usb.c
+++ b/drivers/net/wireless/rt2x00/rt2x00usb.c
@@ -362,6 +362,12 @@ void rt2x00usb_disable_radio(struct rt2x00_dev *rt2x00dev)
362 } 362 }
363 } 363 }
364 364
365 /*
366 * Kill guardian urb (if required by driver).
367 */
368 if (!test_bit(DRIVER_REQUIRE_BEACON_GUARD, &rt2x00dev->flags))
369 return;
370
365 for (i = 0; i < rt2x00dev->bcn->limit; i++) { 371 for (i = 0; i < rt2x00dev->bcn->limit; i++) {
366 priv_bcn = rt2x00dev->bcn->entries[i].priv_data; 372 priv_bcn = rt2x00dev->bcn->entries[i].priv_data;
367 usb_kill_urb(priv_bcn->urb); 373 usb_kill_urb(priv_bcn->urb);
diff --git a/drivers/net/wireless/rt2x00/rt73usb.c b/drivers/net/wireless/rt2x00/rt73usb.c
index da19a3a91f4..fff8386e816 100644
--- a/drivers/net/wireless/rt2x00/rt73usb.c
+++ b/drivers/net/wireless/rt2x00/rt73usb.c
@@ -2131,6 +2131,7 @@ static struct usb_device_id rt73usb_device_table[] = {
2131 /* D-Link */ 2131 /* D-Link */
2132 { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) }, 2132 { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2133 { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) }, 2133 { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
2134 { USB_DEVICE(0x07d1, 0x3c06), USB_DEVICE_DATA(&rt73usb_ops) },
2134 { USB_DEVICE(0x07d1, 0x3c07), USB_DEVICE_DATA(&rt73usb_ops) }, 2135 { USB_DEVICE(0x07d1, 0x3c07), USB_DEVICE_DATA(&rt73usb_ops) },
2135 /* Gemtek */ 2136 /* Gemtek */
2136 { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) }, 2137 { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
diff --git a/drivers/scsi/dpt/dptsig.h b/drivers/scsi/dpt/dptsig.h
index 72c8992fdf2..a6644b332b5 100644
--- a/drivers/scsi/dpt/dptsig.h
+++ b/drivers/scsi/dpt/dptsig.h
@@ -85,7 +85,7 @@ typedef unsigned int sigINT;
85/* ------------------------------------------------------------------ */ 85/* ------------------------------------------------------------------ */
86/* What type of processor the file is meant to run on. */ 86/* What type of processor the file is meant to run on. */
87/* This will let us know whether to read sigWORDs as high/low or low/high. */ 87/* This will let us know whether to read sigWORDs as high/low or low/high. */
88#define PROC_INTEL 0x00 /* Intel 80x86 */ 88#define PROC_INTEL 0x00 /* Intel 80x86/ia64 */
89#define PROC_MOTOROLA 0x01 /* Motorola 68K */ 89#define PROC_MOTOROLA 0x01 /* Motorola 68K */
90#define PROC_MIPS4000 0x02 /* MIPS RISC 4000 */ 90#define PROC_MIPS4000 0x02 /* MIPS RISC 4000 */
91#define PROC_ALPHA 0x03 /* DEC Alpha */ 91#define PROC_ALPHA 0x03 /* DEC Alpha */
@@ -104,6 +104,7 @@ typedef unsigned int sigINT;
104#define PROC_486 0x08 /* Intel 80486 */ 104#define PROC_486 0x08 /* Intel 80486 */
105#define PROC_PENTIUM 0x10 /* Intel 586 aka P5 aka Pentium */ 105#define PROC_PENTIUM 0x10 /* Intel 586 aka P5 aka Pentium */
106#define PROC_SEXIUM 0x20 /* Intel 686 aka P6 aka Pentium Pro or MMX */ 106#define PROC_SEXIUM 0x20 /* Intel 686 aka P6 aka Pentium Pro or MMX */
107#define PROC_IA64 0x40 /* Intel IA64 processor */
107 108
108/* PROC_i960: */ 109/* PROC_i960: */
109#define PROC_960RX 0x01 /* Intel 80960RC/RD */ 110#define PROC_960RX 0x01 /* Intel 80960RC/RD */
diff --git a/drivers/scsi/hosts.c b/drivers/scsi/hosts.c
index 3690360d7a7..c6457bfc8a4 100644
--- a/drivers/scsi/hosts.c
+++ b/drivers/scsi/hosts.c
@@ -456,6 +456,10 @@ static int __scsi_host_match(struct device *dev, void *data)
456 * 456 *
457 * Return value: 457 * Return value:
458 * A pointer to located Scsi_Host or NULL. 458 * A pointer to located Scsi_Host or NULL.
459 *
460 * The caller must do a scsi_host_put() to drop the reference
461 * that scsi_host_get() took. The put_device() below dropped
462 * the reference from class_find_device().
459 **/ 463 **/
460struct Scsi_Host *scsi_host_lookup(unsigned short hostnum) 464struct Scsi_Host *scsi_host_lookup(unsigned short hostnum)
461{ 465{
@@ -463,9 +467,10 @@ struct Scsi_Host *scsi_host_lookup(unsigned short hostnum)
463 struct Scsi_Host *shost = ERR_PTR(-ENXIO); 467 struct Scsi_Host *shost = ERR_PTR(-ENXIO);
464 468
465 cdev = class_find_device(&shost_class, &hostnum, __scsi_host_match); 469 cdev = class_find_device(&shost_class, &hostnum, __scsi_host_match);
466 if (cdev) 470 if (cdev) {
467 shost = scsi_host_get(class_to_shost(cdev)); 471 shost = scsi_host_get(class_to_shost(cdev));
468 472 put_device(cdev);
473 }
469 return shost; 474 return shost;
470} 475}
471EXPORT_SYMBOL(scsi_host_lookup); 476EXPORT_SYMBOL(scsi_host_lookup);
diff --git a/drivers/scsi/sr.c b/drivers/scsi/sr.c
index 7ee86d4a761..c82df8bd4d8 100644
--- a/drivers/scsi/sr.c
+++ b/drivers/scsi/sr.c
@@ -178,6 +178,9 @@ int sr_test_unit_ready(struct scsi_device *sdev, struct scsi_sense_hdr *sshdr)
178 the_result = scsi_execute_req(sdev, cmd, DMA_NONE, NULL, 178 the_result = scsi_execute_req(sdev, cmd, DMA_NONE, NULL,
179 0, sshdr, SR_TIMEOUT, 179 0, sshdr, SR_TIMEOUT,
180 retries--); 180 retries--);
181 if (scsi_sense_valid(sshdr) &&
182 sshdr->sense_key == UNIT_ATTENTION)
183 sdev->changed = 1;
181 184
182 } while (retries > 0 && 185 } while (retries > 0 &&
183 (!scsi_status_is_good(the_result) || 186 (!scsi_status_is_good(the_result) ||
diff --git a/drivers/serial/bfin_5xx.c b/drivers/serial/bfin_5xx.c
index f20952c43cb..fd9bb777df2 100644
--- a/drivers/serial/bfin_5xx.c
+++ b/drivers/serial/bfin_5xx.c
@@ -49,6 +49,7 @@
49#define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT) 49#define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT)
50 50
51#define DMA_RX_FLUSH_JIFFIES (HZ / 50) 51#define DMA_RX_FLUSH_JIFFIES (HZ / 50)
52#define CTS_CHECK_JIFFIES (HZ / 50)
52 53
53#ifdef CONFIG_SERIAL_BFIN_DMA 54#ifdef CONFIG_SERIAL_BFIN_DMA
54static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart); 55static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart);
@@ -290,11 +291,6 @@ static void bfin_serial_tx_chars(struct bfin_serial_port *uart)
290{ 291{
291 struct circ_buf *xmit = &uart->port.info->xmit; 292 struct circ_buf *xmit = &uart->port.info->xmit;
292 293
293 if (uart->port.x_char) {
294 UART_PUT_CHAR(uart, uart->port.x_char);
295 uart->port.icount.tx++;
296 uart->port.x_char = 0;
297 }
298 /* 294 /*
299 * Check the modem control lines before 295 * Check the modem control lines before
300 * transmitting anything. 296 * transmitting anything.
@@ -306,6 +302,12 @@ static void bfin_serial_tx_chars(struct bfin_serial_port *uart)
306 return; 302 return;
307 } 303 }
308 304
305 if (uart->port.x_char) {
306 UART_PUT_CHAR(uart, uart->port.x_char);
307 uart->port.icount.tx++;
308 uart->port.x_char = 0;
309 }
310
309 while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) { 311 while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) {
310 UART_PUT_CHAR(uart, xmit->buf[xmit->tail]); 312 UART_PUT_CHAR(uart, xmit->buf[xmit->tail]);
311 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 313 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
@@ -345,15 +347,6 @@ static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id)
345} 347}
346#endif 348#endif
347 349
348#ifdef CONFIG_SERIAL_BFIN_CTSRTS
349static void bfin_serial_do_work(struct work_struct *work)
350{
351 struct bfin_serial_port *uart = container_of(work, struct bfin_serial_port, cts_workqueue);
352
353 bfin_serial_mctrl_check(uart);
354}
355#endif
356
357#ifdef CONFIG_SERIAL_BFIN_DMA 350#ifdef CONFIG_SERIAL_BFIN_DMA
358static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart) 351static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart)
359{ 352{
@@ -361,6 +354,12 @@ static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart)
361 354
362 uart->tx_done = 0; 355 uart->tx_done = 0;
363 356
357 /*
358 * Check the modem control lines before
359 * transmitting anything.
360 */
361 bfin_serial_mctrl_check(uart);
362
364 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) { 363 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
365 uart->tx_count = 0; 364 uart->tx_count = 0;
366 uart->tx_done = 1; 365 uart->tx_done = 1;
@@ -373,12 +372,6 @@ static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart)
373 uart->port.x_char = 0; 372 uart->port.x_char = 0;
374 } 373 }
375 374
376 /*
377 * Check the modem control lines before
378 * transmitting anything.
379 */
380 bfin_serial_mctrl_check(uart);
381
382 uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE); 375 uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE);
383 if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail)) 376 if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail))
384 uart->tx_count = UART_XMIT_SIZE - xmit->tail; 377 uart->tx_count = UART_XMIT_SIZE - xmit->tail;
@@ -565,7 +558,10 @@ static void bfin_serial_mctrl_check(struct bfin_serial_port *uart)
565 uart_handle_cts_change(&uart->port, status & TIOCM_CTS); 558 uart_handle_cts_change(&uart->port, status & TIOCM_CTS);
566 if (!(status & TIOCM_CTS)) { 559 if (!(status & TIOCM_CTS)) {
567 tty->hw_stopped = 1; 560 tty->hw_stopped = 1;
568 schedule_work(&uart->cts_workqueue); 561 uart->cts_timer.data = (unsigned long)(uart);
562 uart->cts_timer.function = (void *)bfin_serial_mctrl_check;
563 uart->cts_timer.expires = jiffies + CTS_CHECK_JIFFIES;
564 add_timer(&(uart->cts_timer));
569 } else { 565 } else {
570 tty->hw_stopped = 0; 566 tty->hw_stopped = 0;
571 } 567 }
@@ -885,7 +881,7 @@ static void __init bfin_serial_init_ports(void)
885 init_timer(&(bfin_serial_ports[i].rx_dma_timer)); 881 init_timer(&(bfin_serial_ports[i].rx_dma_timer));
886#endif 882#endif
887#ifdef CONFIG_SERIAL_BFIN_CTSRTS 883#ifdef CONFIG_SERIAL_BFIN_CTSRTS
888 INIT_WORK(&bfin_serial_ports[i].cts_workqueue, bfin_serial_do_work); 884 init_timer(&(bfin_serial_ports[i].cts_timer));
889 bfin_serial_ports[i].cts_pin = 885 bfin_serial_ports[i].cts_pin =
890 bfin_serial_resource[i].uart_cts_pin; 886 bfin_serial_resource[i].uart_cts_pin;
891 bfin_serial_ports[i].rts_pin = 887 bfin_serial_ports[i].rts_pin =
diff --git a/drivers/ssb/main.c b/drivers/ssb/main.c
index 7cf8851286b..d184f2aea78 100644
--- a/drivers/ssb/main.c
+++ b/drivers/ssb/main.c
@@ -1168,15 +1168,21 @@ EXPORT_SYMBOL(ssb_dma_translation);
1168int ssb_dma_set_mask(struct ssb_device *ssb_dev, u64 mask) 1168int ssb_dma_set_mask(struct ssb_device *ssb_dev, u64 mask)
1169{ 1169{
1170 struct device *dma_dev = ssb_dev->dma_dev; 1170 struct device *dma_dev = ssb_dev->dma_dev;
1171 int err = 0;
1171 1172
1172#ifdef CONFIG_SSB_PCIHOST 1173#ifdef CONFIG_SSB_PCIHOST
1173 if (ssb_dev->bus->bustype == SSB_BUSTYPE_PCI) 1174 if (ssb_dev->bus->bustype == SSB_BUSTYPE_PCI) {
1174 return dma_set_mask(dma_dev, mask); 1175 err = pci_set_dma_mask(ssb_dev->bus->host_pci, mask);
1176 if (err)
1177 return err;
1178 err = pci_set_consistent_dma_mask(ssb_dev->bus->host_pci, mask);
1179 return err;
1180 }
1175#endif 1181#endif
1176 dma_dev->coherent_dma_mask = mask; 1182 dma_dev->coherent_dma_mask = mask;
1177 dma_dev->dma_mask = &dma_dev->coherent_dma_mask; 1183 dma_dev->dma_mask = &dma_dev->coherent_dma_mask;
1178 1184
1179 return 0; 1185 return err;
1180} 1186}
1181EXPORT_SYMBOL(ssb_dma_set_mask); 1187EXPORT_SYMBOL(ssb_dma_set_mask);
1182 1188
diff --git a/drivers/usb/core/quirks.c b/drivers/usb/core/quirks.c
index 3da1ab4b389..c070b34b669 100644
--- a/drivers/usb/core/quirks.c
+++ b/drivers/usb/core/quirks.c
@@ -47,6 +47,9 @@ static const struct usb_device_id usb_quirk_list[] = {
47 /* Edirol SD-20 */ 47 /* Edirol SD-20 */
48 { USB_DEVICE(0x0582, 0x0027), .driver_info = USB_QUIRK_RESET_RESUME }, 48 { USB_DEVICE(0x0582, 0x0027), .driver_info = USB_QUIRK_RESET_RESUME },
49 49
50 /* appletouch */
51 { USB_DEVICE(0x05ac, 0x021a), .driver_info = USB_QUIRK_RESET_RESUME },
52
50 /* Avision AV600U */ 53 /* Avision AV600U */
51 { USB_DEVICE(0x0638, 0x0a13), .driver_info = 54 { USB_DEVICE(0x0638, 0x0a13), .driver_info =
52 USB_QUIRK_STRING_FETCH_255 }, 55 USB_QUIRK_STRING_FETCH_255 },
diff --git a/drivers/watchdog/hpwdt.c b/drivers/watchdog/hpwdt.c
index 6a63535fc04..eaa3f2a79ff 100644
--- a/drivers/watchdog/hpwdt.c
+++ b/drivers/watchdog/hpwdt.c
@@ -140,49 +140,53 @@ static struct pci_device_id hpwdt_devices[] = {
140}; 140};
141MODULE_DEVICE_TABLE(pci, hpwdt_devices); 141MODULE_DEVICE_TABLE(pci, hpwdt_devices);
142 142
143extern asmlinkage void asminline_call(struct cmn_registers *pi86Regs, unsigned long *pRomEntry);
144
143#ifndef CONFIG_X86_64 145#ifndef CONFIG_X86_64
144/* --32 Bit Bios------------------------------------------------------------ */ 146/* --32 Bit Bios------------------------------------------------------------ */
145 147
146#define HPWDT_ARCH 32 148#define HPWDT_ARCH 32
147 149
148static void asminline_call(struct cmn_registers *pi86Regs, 150asm(".text \n\t"
149 unsigned long *pRomEntry) 151 ".align 4 \n"
150{ 152 "asminline_call: \n\t"
151 asm("pushl %ebp \n\t" 153 "pushl %ebp \n\t"
152 "movl %esp, %ebp \n\t" 154 "movl %esp, %ebp \n\t"
153 "pusha \n\t" 155 "pusha \n\t"
154 "pushf \n\t" 156 "pushf \n\t"
155 "push %es \n\t" 157 "push %es \n\t"
156 "push %ds \n\t" 158 "push %ds \n\t"
157 "pop %es \n\t" 159 "pop %es \n\t"
158 "movl 8(%ebp),%eax \n\t" 160 "movl 8(%ebp),%eax \n\t"
159 "movl 4(%eax),%ebx \n\t" 161 "movl 4(%eax),%ebx \n\t"
160 "movl 8(%eax),%ecx \n\t" 162 "movl 8(%eax),%ecx \n\t"
161 "movl 12(%eax),%edx \n\t" 163 "movl 12(%eax),%edx \n\t"
162 "movl 16(%eax),%esi \n\t" 164 "movl 16(%eax),%esi \n\t"
163 "movl 20(%eax),%edi \n\t" 165 "movl 20(%eax),%edi \n\t"
164 "movl (%eax),%eax \n\t" 166 "movl (%eax),%eax \n\t"
165 "push %cs \n\t" 167 "push %cs \n\t"
166 "call *12(%ebp) \n\t" 168 "call *12(%ebp) \n\t"
167 "pushf \n\t" 169 "pushf \n\t"
168 "pushl %eax \n\t" 170 "pushl %eax \n\t"
169 "movl 8(%ebp),%eax \n\t" 171 "movl 8(%ebp),%eax \n\t"
170 "movl %ebx,4(%eax) \n\t" 172 "movl %ebx,4(%eax) \n\t"
171 "movl %ecx,8(%eax) \n\t" 173 "movl %ecx,8(%eax) \n\t"
172 "movl %edx,12(%eax) \n\t" 174 "movl %edx,12(%eax) \n\t"
173 "movl %esi,16(%eax) \n\t" 175 "movl %esi,16(%eax) \n\t"
174 "movl %edi,20(%eax) \n\t" 176 "movl %edi,20(%eax) \n\t"
175 "movw %ds,24(%eax) \n\t" 177 "movw %ds,24(%eax) \n\t"
176 "movw %es,26(%eax) \n\t" 178 "movw %es,26(%eax) \n\t"
177 "popl %ebx \n\t" 179 "popl %ebx \n\t"
178 "movl %ebx,(%eax) \n\t" 180 "movl %ebx,(%eax) \n\t"
179 "popl %ebx \n\t" 181 "popl %ebx \n\t"
180 "movl %ebx,28(%eax) \n\t" 182 "movl %ebx,28(%eax) \n\t"
181 "pop %es \n\t" 183 "pop %es \n\t"
182 "popf \n\t" 184 "popf \n\t"
183 "popa \n\t" 185 "popa \n\t"
184 "leave \n\t" "ret"); 186 "leave \n\t"
185} 187 "ret \n\t"
188 ".previous");
189
186 190
187/* 191/*
188 * cru_detect 192 * cru_detect
@@ -333,43 +337,44 @@ static int __devinit detect_cru_service(void)
333 337
334#define HPWDT_ARCH 64 338#define HPWDT_ARCH 64
335 339
336static void asminline_call(struct cmn_registers *pi86Regs, 340asm(".text \n\t"
337 unsigned long *pRomEntry) 341 ".align 4 \n"
338{ 342 "asminline_call: \n\t"
339 asm("pushq %rbp \n\t" 343 "pushq %rbp \n\t"
340 "movq %rsp, %rbp \n\t" 344 "movq %rsp, %rbp \n\t"
341 "pushq %rax \n\t" 345 "pushq %rax \n\t"
342 "pushq %rbx \n\t" 346 "pushq %rbx \n\t"
343 "pushq %rdx \n\t" 347 "pushq %rdx \n\t"
344 "pushq %r12 \n\t" 348 "pushq %r12 \n\t"
345 "pushq %r9 \n\t" 349 "pushq %r9 \n\t"
346 "movq %rsi, %r12 \n\t" 350 "movq %rsi, %r12 \n\t"
347 "movq %rdi, %r9 \n\t" 351 "movq %rdi, %r9 \n\t"
348 "movl 4(%r9),%ebx \n\t" 352 "movl 4(%r9),%ebx \n\t"
349 "movl 8(%r9),%ecx \n\t" 353 "movl 8(%r9),%ecx \n\t"
350 "movl 12(%r9),%edx \n\t" 354 "movl 12(%r9),%edx \n\t"
351 "movl 16(%r9),%esi \n\t" 355 "movl 16(%r9),%esi \n\t"
352 "movl 20(%r9),%edi \n\t" 356 "movl 20(%r9),%edi \n\t"
353 "movl (%r9),%eax \n\t" 357 "movl (%r9),%eax \n\t"
354 "call *%r12 \n\t" 358 "call *%r12 \n\t"
355 "pushfq \n\t" 359 "pushfq \n\t"
356 "popq %r12 \n\t" 360 "popq %r12 \n\t"
357 "popfq \n\t" 361 "popfq \n\t"
358 "movl %eax, (%r9) \n\t" 362 "movl %eax, (%r9) \n\t"
359 "movl %ebx, 4(%r9) \n\t" 363 "movl %ebx, 4(%r9) \n\t"
360 "movl %ecx, 8(%r9) \n\t" 364 "movl %ecx, 8(%r9) \n\t"
361 "movl %edx, 12(%r9) \n\t" 365 "movl %edx, 12(%r9) \n\t"
362 "movl %esi, 16(%r9) \n\t" 366 "movl %esi, 16(%r9) \n\t"
363 "movl %edi, 20(%r9) \n\t" 367 "movl %edi, 20(%r9) \n\t"
364 "movq %r12, %rax \n\t" 368 "movq %r12, %rax \n\t"
365 "movl %eax, 28(%r9) \n\t" 369 "movl %eax, 28(%r9) \n\t"
366 "popq %r9 \n\t" 370 "popq %r9 \n\t"
367 "popq %r12 \n\t" 371 "popq %r12 \n\t"
368 "popq %rdx \n\t" 372 "popq %rdx \n\t"
369 "popq %rbx \n\t" 373 "popq %rbx \n\t"
370 "popq %rax \n\t" 374 "popq %rax \n\t"
371 "leave \n\t" "ret"); 375 "leave \n\t"
372} 376 "ret \n\t"
377 ".previous");
373 378
374/* 379/*
375 * dmi_find_cru 380 * dmi_find_cru
@@ -418,20 +423,23 @@ static int hpwdt_pretimeout(struct notifier_block *nb, unsigned long ulReason,
418 static unsigned long rom_pl; 423 static unsigned long rom_pl;
419 static int die_nmi_called; 424 static int die_nmi_called;
420 425
421 if (ulReason == DIE_NMI || ulReason == DIE_NMI_IPI) { 426 if (ulReason != DIE_NMI && ulReason != DIE_NMI_IPI)
422 spin_lock_irqsave(&rom_lock, rom_pl); 427 return NOTIFY_OK;
423 if (!die_nmi_called) 428
424 asminline_call(&cmn_regs, cru_rom_addr); 429 spin_lock_irqsave(&rom_lock, rom_pl);
425 die_nmi_called = 1; 430 if (!die_nmi_called)
426 spin_unlock_irqrestore(&rom_lock, rom_pl); 431 asminline_call(&cmn_regs, cru_rom_addr);
427 if (cmn_regs.u1.ral != 0) { 432 die_nmi_called = 1;
428 panic("An NMI occurred, please see the Integrated " 433 spin_unlock_irqrestore(&rom_lock, rom_pl);
429 "Management Log for details.\n"); 434 if (cmn_regs.u1.ral == 0) {
430 } 435 printk(KERN_WARNING "hpwdt: An NMI occurred, "
436 "but unable to determine source.\n");
437 } else {
438 panic("An NMI occurred, please see the Integrated "
439 "Management Log for details.\n");
431 } 440 }
432 441
433 die_nmi_called = 0; 442 return NOTIFY_STOP;
434 return NOTIFY_DONE;
435} 443}
436 444
437/* 445/*
diff --git a/drivers/xen/events.c b/drivers/xen/events.c
index 4f0f22b020e..76e5b7386af 100644
--- a/drivers/xen/events.c
+++ b/drivers/xen/events.c
@@ -529,7 +529,7 @@ void xen_evtchn_do_upcall(struct pt_regs *regs)
529 529
530#ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */ 530#ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */
531 /* Clear master flag /before/ clearing selector flag. */ 531 /* Clear master flag /before/ clearing selector flag. */
532 rmb(); 532 wmb();
533#endif 533#endif
534 pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0); 534 pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0);
535 while (pending_words != 0) { 535 while (pending_words != 0) {
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 21:35:58 -0500