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path: root/drivers/spi/spi_imx.c
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Diffstat (limited to 'drivers/spi/spi_imx.c')
-rw-r--r--drivers/spi/spi_imx.c402
1 files changed, 335 insertions, 67 deletions
diff --git a/drivers/spi/spi_imx.c b/drivers/spi/spi_imx.c
index 7972e907747..55a38e2c6c1 100644
--- a/drivers/spi/spi_imx.c
+++ b/drivers/spi/spi_imx.c
@@ -56,7 +56,28 @@ struct spi_imx_config {
56 unsigned int speed_hz; 56 unsigned int speed_hz;
57 unsigned int bpw; 57 unsigned int bpw;
58 unsigned int mode; 58 unsigned int mode;
59 int cs; 59 u8 cs;
60};
61
62enum spi_imx_devtype {
63 SPI_IMX_VER_IMX1,
64 SPI_IMX_VER_0_0,
65 SPI_IMX_VER_0_4,
66 SPI_IMX_VER_0_5,
67 SPI_IMX_VER_0_7,
68 SPI_IMX_VER_2_3,
69 SPI_IMX_VER_AUTODETECT,
70};
71
72struct spi_imx_data;
73
74struct spi_imx_devtype_data {
75 void (*intctrl)(struct spi_imx_data *, int);
76 int (*config)(struct spi_imx_data *, struct spi_imx_config *);
77 void (*trigger)(struct spi_imx_data *);
78 int (*rx_available)(struct spi_imx_data *);
79 void (*reset)(struct spi_imx_data *);
80 unsigned int fifosize;
60}; 81};
61 82
62struct spi_imx_data { 83struct spi_imx_data {
@@ -76,11 +97,7 @@ struct spi_imx_data {
76 const void *tx_buf; 97 const void *tx_buf;
77 unsigned int txfifo; /* number of words pushed in tx FIFO */ 98 unsigned int txfifo; /* number of words pushed in tx FIFO */
78 99
79 /* SoC specific functions */ 100 struct spi_imx_devtype_data devtype_data;
80 void (*intctrl)(struct spi_imx_data *, int);
81 int (*config)(struct spi_imx_data *, struct spi_imx_config *);
82 void (*trigger)(struct spi_imx_data *);
83 int (*rx_available)(struct spi_imx_data *);
84}; 101};
85 102
86#define MXC_SPI_BUF_RX(type) \ 103#define MXC_SPI_BUF_RX(type) \
@@ -140,7 +157,7 @@ static unsigned int spi_imx_clkdiv_1(unsigned int fin,
140 return max; 157 return max;
141} 158}
142 159
143/* MX1, MX31, MX35 */ 160/* MX1, MX31, MX35, MX51 CSPI */
144static unsigned int spi_imx_clkdiv_2(unsigned int fin, 161static unsigned int spi_imx_clkdiv_2(unsigned int fin,
145 unsigned int fspi) 162 unsigned int fspi)
146{ 163{
@@ -155,6 +172,128 @@ static unsigned int spi_imx_clkdiv_2(unsigned int fin,
155 return 7; 172 return 7;
156} 173}
157 174
175#define SPI_IMX2_3_CTRL 0x08
176#define SPI_IMX2_3_CTRL_ENABLE (1 << 0)
177#define SPI_IMX2_3_CTRL_XCH (1 << 2)
178#define SPI_IMX2_3_CTRL_MODE(cs) (1 << ((cs) + 4))
179#define SPI_IMX2_3_CTRL_POSTDIV_OFFSET 8
180#define SPI_IMX2_3_CTRL_PREDIV_OFFSET 12
181#define SPI_IMX2_3_CTRL_CS(cs) ((cs) << 18)
182#define SPI_IMX2_3_CTRL_BL_OFFSET 20
183
184#define SPI_IMX2_3_CONFIG 0x0c
185#define SPI_IMX2_3_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
186#define SPI_IMX2_3_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
187#define SPI_IMX2_3_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
188#define SPI_IMX2_3_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
189
190#define SPI_IMX2_3_INT 0x10
191#define SPI_IMX2_3_INT_TEEN (1 << 0)
192#define SPI_IMX2_3_INT_RREN (1 << 3)
193
194#define SPI_IMX2_3_STAT 0x18
195#define SPI_IMX2_3_STAT_RR (1 << 3)
196
197/* MX51 eCSPI */
198static unsigned int spi_imx2_3_clkdiv(unsigned int fin, unsigned int fspi)
199{
200 /*
201 * there are two 4-bit dividers, the pre-divider divides by
202 * $pre, the post-divider by 2^$post
203 */
204 unsigned int pre, post;
205
206 if (unlikely(fspi > fin))
207 return 0;
208
209 post = fls(fin) - fls(fspi);
210 if (fin > fspi << post)
211 post++;
212
213 /* now we have: (fin <= fspi << post) with post being minimal */
214
215 post = max(4U, post) - 4;
216 if (unlikely(post > 0xf)) {
217 pr_err("%s: cannot set clock freq: %u (base freq: %u)\n",
218 __func__, fspi, fin);
219 return 0xff;
220 }
221
222 pre = DIV_ROUND_UP(fin, fspi << post) - 1;
223
224 pr_debug("%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
225 __func__, fin, fspi, post, pre);
226 return (pre << SPI_IMX2_3_CTRL_PREDIV_OFFSET) |
227 (post << SPI_IMX2_3_CTRL_POSTDIV_OFFSET);
228}
229
230static void __maybe_unused spi_imx2_3_intctrl(struct spi_imx_data *spi_imx, int enable)
231{
232 unsigned val = 0;
233
234 if (enable & MXC_INT_TE)
235 val |= SPI_IMX2_3_INT_TEEN;
236
237 if (enable & MXC_INT_RR)
238 val |= SPI_IMX2_3_INT_RREN;
239
240 writel(val, spi_imx->base + SPI_IMX2_3_INT);
241}
242
243static void __maybe_unused spi_imx2_3_trigger(struct spi_imx_data *spi_imx)
244{
245 u32 reg;
246
247 reg = readl(spi_imx->base + SPI_IMX2_3_CTRL);
248 reg |= SPI_IMX2_3_CTRL_XCH;
249 writel(reg, spi_imx->base + SPI_IMX2_3_CTRL);
250}
251
252static int __maybe_unused spi_imx2_3_config(struct spi_imx_data *spi_imx,
253 struct spi_imx_config *config)
254{
255 u32 ctrl = SPI_IMX2_3_CTRL_ENABLE, cfg = 0;
256
257 /* set master mode */
258 ctrl |= SPI_IMX2_3_CTRL_MODE(config->cs);
259
260 /* set clock speed */
261 ctrl |= spi_imx2_3_clkdiv(spi_imx->spi_clk, config->speed_hz);
262
263 /* set chip select to use */
264 ctrl |= SPI_IMX2_3_CTRL_CS(config->cs);
265
266 ctrl |= (config->bpw - 1) << SPI_IMX2_3_CTRL_BL_OFFSET;
267
268 cfg |= SPI_IMX2_3_CONFIG_SBBCTRL(config->cs);
269
270 if (config->mode & SPI_CPHA)
271 cfg |= SPI_IMX2_3_CONFIG_SCLKPHA(config->cs);
272
273 if (config->mode & SPI_CPOL)
274 cfg |= SPI_IMX2_3_CONFIG_SCLKPOL(config->cs);
275
276 if (config->mode & SPI_CS_HIGH)
277 cfg |= SPI_IMX2_3_CONFIG_SSBPOL(config->cs);
278
279 writel(ctrl, spi_imx->base + SPI_IMX2_3_CTRL);
280 writel(cfg, spi_imx->base + SPI_IMX2_3_CONFIG);
281
282 return 0;
283}
284
285static int __maybe_unused spi_imx2_3_rx_available(struct spi_imx_data *spi_imx)
286{
287 return readl(spi_imx->base + SPI_IMX2_3_STAT) & SPI_IMX2_3_STAT_RR;
288}
289
290static void __maybe_unused spi_imx2_3_reset(struct spi_imx_data *spi_imx)
291{
292 /* drain receive buffer */
293 while (spi_imx2_3_rx_available(spi_imx))
294 readl(spi_imx->base + MXC_CSPIRXDATA);
295}
296
158#define MX31_INTREG_TEEN (1 << 0) 297#define MX31_INTREG_TEEN (1 << 0)
159#define MX31_INTREG_RREN (1 << 3) 298#define MX31_INTREG_RREN (1 << 3)
160 299
@@ -178,7 +317,7 @@ static unsigned int spi_imx_clkdiv_2(unsigned int fin,
178 * the i.MX35 has a slightly different register layout for bits 317 * the i.MX35 has a slightly different register layout for bits
179 * we do not use here. 318 * we do not use here.
180 */ 319 */
181static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable) 320static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
182{ 321{
183 unsigned int val = 0; 322 unsigned int val = 0;
184 323
@@ -190,7 +329,7 @@ static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
190 writel(val, spi_imx->base + MXC_CSPIINT); 329 writel(val, spi_imx->base + MXC_CSPIINT);
191} 330}
192 331
193static void mx31_trigger(struct spi_imx_data *spi_imx) 332static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx)
194{ 333{
195 unsigned int reg; 334 unsigned int reg;
196 335
@@ -199,20 +338,16 @@ static void mx31_trigger(struct spi_imx_data *spi_imx)
199 writel(reg, spi_imx->base + MXC_CSPICTRL); 338 writel(reg, spi_imx->base + MXC_CSPICTRL);
200} 339}
201 340
202static int mx31_config(struct spi_imx_data *spi_imx, 341static int __maybe_unused spi_imx0_4_config(struct spi_imx_data *spi_imx,
203 struct spi_imx_config *config) 342 struct spi_imx_config *config)
204{ 343{
205 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER; 344 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
345 int cs = spi_imx->chipselect[config->cs];
206 346
207 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) << 347 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
208 MX31_CSPICTRL_DR_SHIFT; 348 MX31_CSPICTRL_DR_SHIFT;
209 349
210 if (cpu_is_mx31()) 350 reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
211 reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
212 else if (cpu_is_mx25() || cpu_is_mx35()) {
213 reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
214 reg |= MX31_CSPICTRL_SSCTL;
215 }
216 351
217 if (config->mode & SPI_CPHA) 352 if (config->mode & SPI_CPHA)
218 reg |= MX31_CSPICTRL_PHA; 353 reg |= MX31_CSPICTRL_PHA;
@@ -220,23 +355,52 @@ static int mx31_config(struct spi_imx_data *spi_imx,
220 reg |= MX31_CSPICTRL_POL; 355 reg |= MX31_CSPICTRL_POL;
221 if (config->mode & SPI_CS_HIGH) 356 if (config->mode & SPI_CS_HIGH)
222 reg |= MX31_CSPICTRL_SSPOL; 357 reg |= MX31_CSPICTRL_SSPOL;
223 if (config->cs < 0) { 358 if (cs < 0)
224 if (cpu_is_mx31()) 359 reg |= (cs + 32) << MX31_CSPICTRL_CS_SHIFT;
225 reg |= (config->cs + 32) << MX31_CSPICTRL_CS_SHIFT; 360
226 else if (cpu_is_mx25() || cpu_is_mx35()) 361 writel(reg, spi_imx->base + MXC_CSPICTRL);
227 reg |= (config->cs + 32) << MX35_CSPICTRL_CS_SHIFT; 362
228 } 363 return 0;
364}
365
366static int __maybe_unused spi_imx0_7_config(struct spi_imx_data *spi_imx,
367 struct spi_imx_config *config)
368{
369 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
370 int cs = spi_imx->chipselect[config->cs];
371
372 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
373 MX31_CSPICTRL_DR_SHIFT;
374
375 reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
376 reg |= MX31_CSPICTRL_SSCTL;
377
378 if (config->mode & SPI_CPHA)
379 reg |= MX31_CSPICTRL_PHA;
380 if (config->mode & SPI_CPOL)
381 reg |= MX31_CSPICTRL_POL;
382 if (config->mode & SPI_CS_HIGH)
383 reg |= MX31_CSPICTRL_SSPOL;
384 if (cs < 0)
385 reg |= (cs + 32) << MX35_CSPICTRL_CS_SHIFT;
229 386
230 writel(reg, spi_imx->base + MXC_CSPICTRL); 387 writel(reg, spi_imx->base + MXC_CSPICTRL);
231 388
232 return 0; 389 return 0;
233} 390}
234 391
235static int mx31_rx_available(struct spi_imx_data *spi_imx) 392static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx)
236{ 393{
237 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR; 394 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
238} 395}
239 396
397static void __maybe_unused spi_imx0_4_reset(struct spi_imx_data *spi_imx)
398{
399 /* drain receive buffer */
400 while (readl(spi_imx->base + MX3_CSPISTAT) & MX3_CSPISTAT_RR)
401 readl(spi_imx->base + MXC_CSPIRXDATA);
402}
403
240#define MX27_INTREG_RR (1 << 4) 404#define MX27_INTREG_RR (1 << 4)
241#define MX27_INTREG_TEEN (1 << 9) 405#define MX27_INTREG_TEEN (1 << 9)
242#define MX27_INTREG_RREN (1 << 13) 406#define MX27_INTREG_RREN (1 << 13)
@@ -250,7 +414,7 @@ static int mx31_rx_available(struct spi_imx_data *spi_imx)
250#define MX27_CSPICTRL_DR_SHIFT 14 414#define MX27_CSPICTRL_DR_SHIFT 14
251#define MX27_CSPICTRL_CS_SHIFT 19 415#define MX27_CSPICTRL_CS_SHIFT 19
252 416
253static void mx27_intctrl(struct spi_imx_data *spi_imx, int enable) 417static void __maybe_unused mx27_intctrl(struct spi_imx_data *spi_imx, int enable)
254{ 418{
255 unsigned int val = 0; 419 unsigned int val = 0;
256 420
@@ -262,7 +426,7 @@ static void mx27_intctrl(struct spi_imx_data *spi_imx, int enable)
262 writel(val, spi_imx->base + MXC_CSPIINT); 426 writel(val, spi_imx->base + MXC_CSPIINT);
263} 427}
264 428
265static void mx27_trigger(struct spi_imx_data *spi_imx) 429static void __maybe_unused mx27_trigger(struct spi_imx_data *spi_imx)
266{ 430{
267 unsigned int reg; 431 unsigned int reg;
268 432
@@ -271,10 +435,11 @@ static void mx27_trigger(struct spi_imx_data *spi_imx)
271 writel(reg, spi_imx->base + MXC_CSPICTRL); 435 writel(reg, spi_imx->base + MXC_CSPICTRL);
272} 436}
273 437
274static int mx27_config(struct spi_imx_data *spi_imx, 438static int __maybe_unused mx27_config(struct spi_imx_data *spi_imx,
275 struct spi_imx_config *config) 439 struct spi_imx_config *config)
276{ 440{
277 unsigned int reg = MX27_CSPICTRL_ENABLE | MX27_CSPICTRL_MASTER; 441 unsigned int reg = MX27_CSPICTRL_ENABLE | MX27_CSPICTRL_MASTER;
442 int cs = spi_imx->chipselect[config->cs];
278 443
279 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz) << 444 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz) <<
280 MX27_CSPICTRL_DR_SHIFT; 445 MX27_CSPICTRL_DR_SHIFT;
@@ -286,19 +451,24 @@ static int mx27_config(struct spi_imx_data *spi_imx,
286 reg |= MX27_CSPICTRL_POL; 451 reg |= MX27_CSPICTRL_POL;
287 if (config->mode & SPI_CS_HIGH) 452 if (config->mode & SPI_CS_HIGH)
288 reg |= MX27_CSPICTRL_SSPOL; 453 reg |= MX27_CSPICTRL_SSPOL;
289 if (config->cs < 0) 454 if (cs < 0)
290 reg |= (config->cs + 32) << MX27_CSPICTRL_CS_SHIFT; 455 reg |= (cs + 32) << MX27_CSPICTRL_CS_SHIFT;
291 456
292 writel(reg, spi_imx->base + MXC_CSPICTRL); 457 writel(reg, spi_imx->base + MXC_CSPICTRL);
293 458
294 return 0; 459 return 0;
295} 460}
296 461
297static int mx27_rx_available(struct spi_imx_data *spi_imx) 462static int __maybe_unused mx27_rx_available(struct spi_imx_data *spi_imx)
298{ 463{
299 return readl(spi_imx->base + MXC_CSPIINT) & MX27_INTREG_RR; 464 return readl(spi_imx->base + MXC_CSPIINT) & MX27_INTREG_RR;
300} 465}
301 466
467static void __maybe_unused spi_imx0_0_reset(struct spi_imx_data *spi_imx)
468{
469 writel(1, spi_imx->base + MXC_RESET);
470}
471
302#define MX1_INTREG_RR (1 << 3) 472#define MX1_INTREG_RR (1 << 3)
303#define MX1_INTREG_TEEN (1 << 8) 473#define MX1_INTREG_TEEN (1 << 8)
304#define MX1_INTREG_RREN (1 << 11) 474#define MX1_INTREG_RREN (1 << 11)
@@ -310,7 +480,7 @@ static int mx27_rx_available(struct spi_imx_data *spi_imx)
310#define MX1_CSPICTRL_MASTER (1 << 10) 480#define MX1_CSPICTRL_MASTER (1 << 10)
311#define MX1_CSPICTRL_DR_SHIFT 13 481#define MX1_CSPICTRL_DR_SHIFT 13
312 482
313static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable) 483static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
314{ 484{
315 unsigned int val = 0; 485 unsigned int val = 0;
316 486
@@ -322,7 +492,7 @@ static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
322 writel(val, spi_imx->base + MXC_CSPIINT); 492 writel(val, spi_imx->base + MXC_CSPIINT);
323} 493}
324 494
325static void mx1_trigger(struct spi_imx_data *spi_imx) 495static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx)
326{ 496{
327 unsigned int reg; 497 unsigned int reg;
328 498
@@ -331,7 +501,7 @@ static void mx1_trigger(struct spi_imx_data *spi_imx)
331 writel(reg, spi_imx->base + MXC_CSPICTRL); 501 writel(reg, spi_imx->base + MXC_CSPICTRL);
332} 502}
333 503
334static int mx1_config(struct spi_imx_data *spi_imx, 504static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx,
335 struct spi_imx_config *config) 505 struct spi_imx_config *config)
336{ 506{
337 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER; 507 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
@@ -350,11 +520,73 @@ static int mx1_config(struct spi_imx_data *spi_imx,
350 return 0; 520 return 0;
351} 521}
352 522
353static int mx1_rx_available(struct spi_imx_data *spi_imx) 523static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx)
354{ 524{
355 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR; 525 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
356} 526}
357 527
528static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx)
529{
530 writel(1, spi_imx->base + MXC_RESET);
531}
532
533/*
534 * These version numbers are taken from the Freescale driver. Unfortunately it
535 * doesn't support i.MX1, so this entry doesn't match the scheme. :-(
536 */
537static struct spi_imx_devtype_data spi_imx_devtype_data[] __devinitdata = {
538#ifdef CONFIG_SPI_IMX_VER_IMX1
539 [SPI_IMX_VER_IMX1] = {
540 .intctrl = mx1_intctrl,
541 .config = mx1_config,
542 .trigger = mx1_trigger,
543 .rx_available = mx1_rx_available,
544 .reset = mx1_reset,
545 .fifosize = 8,
546 },
547#endif
548#ifdef CONFIG_SPI_IMX_VER_0_0
549 [SPI_IMX_VER_0_0] = {
550 .intctrl = mx27_intctrl,
551 .config = mx27_config,
552 .trigger = mx27_trigger,
553 .rx_available = mx27_rx_available,
554 .reset = spi_imx0_0_reset,
555 .fifosize = 8,
556 },
557#endif
558#ifdef CONFIG_SPI_IMX_VER_0_4
559 [SPI_IMX_VER_0_4] = {
560 .intctrl = mx31_intctrl,
561 .config = spi_imx0_4_config,
562 .trigger = mx31_trigger,
563 .rx_available = mx31_rx_available,
564 .reset = spi_imx0_4_reset,
565 .fifosize = 8,
566 },
567#endif
568#ifdef CONFIG_SPI_IMX_VER_0_7
569 [SPI_IMX_VER_0_7] = {
570 .intctrl = mx31_intctrl,
571 .config = spi_imx0_7_config,
572 .trigger = mx31_trigger,
573 .rx_available = mx31_rx_available,
574 .reset = spi_imx0_4_reset,
575 .fifosize = 8,
576 },
577#endif
578#ifdef CONFIG_SPI_IMX_VER_2_3
579 [SPI_IMX_VER_2_3] = {
580 .intctrl = spi_imx2_3_intctrl,
581 .config = spi_imx2_3_config,
582 .trigger = spi_imx2_3_trigger,
583 .rx_available = spi_imx2_3_rx_available,
584 .reset = spi_imx2_3_reset,
585 .fifosize = 64,
586 },
587#endif
588};
589
358static void spi_imx_chipselect(struct spi_device *spi, int is_active) 590static void spi_imx_chipselect(struct spi_device *spi, int is_active)
359{ 591{
360 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 592 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
@@ -370,21 +602,21 @@ static void spi_imx_chipselect(struct spi_device *spi, int is_active)
370 602
371static void spi_imx_push(struct spi_imx_data *spi_imx) 603static void spi_imx_push(struct spi_imx_data *spi_imx)
372{ 604{
373 while (spi_imx->txfifo < 8) { 605 while (spi_imx->txfifo < spi_imx->devtype_data.fifosize) {
374 if (!spi_imx->count) 606 if (!spi_imx->count)
375 break; 607 break;
376 spi_imx->tx(spi_imx); 608 spi_imx->tx(spi_imx);
377 spi_imx->txfifo++; 609 spi_imx->txfifo++;
378 } 610 }
379 611
380 spi_imx->trigger(spi_imx); 612 spi_imx->devtype_data.trigger(spi_imx);
381} 613}
382 614
383static irqreturn_t spi_imx_isr(int irq, void *dev_id) 615static irqreturn_t spi_imx_isr(int irq, void *dev_id)
384{ 616{
385 struct spi_imx_data *spi_imx = dev_id; 617 struct spi_imx_data *spi_imx = dev_id;
386 618
387 while (spi_imx->rx_available(spi_imx)) { 619 while (spi_imx->devtype_data.rx_available(spi_imx)) {
388 spi_imx->rx(spi_imx); 620 spi_imx->rx(spi_imx);
389 spi_imx->txfifo--; 621 spi_imx->txfifo--;
390 } 622 }
@@ -398,11 +630,12 @@ static irqreturn_t spi_imx_isr(int irq, void *dev_id)
398 /* No data left to push, but still waiting for rx data, 630 /* No data left to push, but still waiting for rx data,
399 * enable receive data available interrupt. 631 * enable receive data available interrupt.
400 */ 632 */
401 spi_imx->intctrl(spi_imx, MXC_INT_RR); 633 spi_imx->devtype_data.intctrl(
634 spi_imx, MXC_INT_RR);
402 return IRQ_HANDLED; 635 return IRQ_HANDLED;
403 } 636 }
404 637
405 spi_imx->intctrl(spi_imx, 0); 638 spi_imx->devtype_data.intctrl(spi_imx, 0);
406 complete(&spi_imx->xfer_done); 639 complete(&spi_imx->xfer_done);
407 640
408 return IRQ_HANDLED; 641 return IRQ_HANDLED;
@@ -417,7 +650,7 @@ static int spi_imx_setupxfer(struct spi_device *spi,
417 config.bpw = t ? t->bits_per_word : spi->bits_per_word; 650 config.bpw = t ? t->bits_per_word : spi->bits_per_word;
418 config.speed_hz = t ? t->speed_hz : spi->max_speed_hz; 651 config.speed_hz = t ? t->speed_hz : spi->max_speed_hz;
419 config.mode = spi->mode; 652 config.mode = spi->mode;
420 config.cs = spi_imx->chipselect[spi->chip_select]; 653 config.cs = spi->chip_select;
421 654
422 if (!config.speed_hz) 655 if (!config.speed_hz)
423 config.speed_hz = spi->max_speed_hz; 656 config.speed_hz = spi->max_speed_hz;
@@ -439,7 +672,7 @@ static int spi_imx_setupxfer(struct spi_device *spi,
439 } else 672 } else
440 BUG(); 673 BUG();
441 674
442 spi_imx->config(spi_imx, &config); 675 spi_imx->devtype_data.config(spi_imx, &config);
443 676
444 return 0; 677 return 0;
445} 678}
@@ -458,7 +691,7 @@ static int spi_imx_transfer(struct spi_device *spi,
458 691
459 spi_imx_push(spi_imx); 692 spi_imx_push(spi_imx);
460 693
461 spi_imx->intctrl(spi_imx, MXC_INT_TE); 694 spi_imx->devtype_data.intctrl(spi_imx, MXC_INT_TE);
462 695
463 wait_for_completion(&spi_imx->xfer_done); 696 wait_for_completion(&spi_imx->xfer_done);
464 697
@@ -485,6 +718,39 @@ static void spi_imx_cleanup(struct spi_device *spi)
485{ 718{
486} 719}
487 720
721static struct platform_device_id spi_imx_devtype[] = {
722 {
723 .name = DRIVER_NAME,
724 .driver_data = SPI_IMX_VER_AUTODETECT,
725 }, {
726 .name = "imx1-cspi",
727 .driver_data = SPI_IMX_VER_IMX1,
728 }, {
729 .name = "imx21-cspi",
730 .driver_data = SPI_IMX_VER_0_0,
731 }, {
732 .name = "imx25-cspi",
733 .driver_data = SPI_IMX_VER_0_7,
734 }, {
735 .name = "imx27-cspi",
736 .driver_data = SPI_IMX_VER_0_0,
737 }, {
738 .name = "imx31-cspi",
739 .driver_data = SPI_IMX_VER_0_4,
740 }, {
741 .name = "imx35-cspi",
742 .driver_data = SPI_IMX_VER_0_7,
743 }, {
744 .name = "imx51-cspi",
745 .driver_data = SPI_IMX_VER_0_7,
746 }, {
747 .name = "imx51-ecspi",
748 .driver_data = SPI_IMX_VER_2_3,
749 }, {
750 /* sentinel */
751 }
752};
753
488static int __devinit spi_imx_probe(struct platform_device *pdev) 754static int __devinit spi_imx_probe(struct platform_device *pdev)
489{ 755{
490 struct spi_imx_master *mxc_platform_info; 756 struct spi_imx_master *mxc_platform_info;
@@ -536,6 +802,31 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
536 802
537 init_completion(&spi_imx->xfer_done); 803 init_completion(&spi_imx->xfer_done);
538 804
805 if (pdev->id_entry->driver_data == SPI_IMX_VER_AUTODETECT) {
806 if (cpu_is_mx25() || cpu_is_mx35())
807 spi_imx->devtype_data =
808 spi_imx_devtype_data[SPI_IMX_VER_0_7];
809 else if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35())
810 spi_imx->devtype_data =
811 spi_imx_devtype_data[SPI_IMX_VER_0_4];
812 else if (cpu_is_mx27() || cpu_is_mx21())
813 spi_imx->devtype_data =
814 spi_imx_devtype_data[SPI_IMX_VER_0_0];
815 else if (cpu_is_mx1())
816 spi_imx->devtype_data =
817 spi_imx_devtype_data[SPI_IMX_VER_IMX1];
818 else
819 BUG();
820 } else
821 spi_imx->devtype_data =
822 spi_imx_devtype_data[pdev->id_entry->driver_data];
823
824 if (!spi_imx->devtype_data.intctrl) {
825 dev_err(&pdev->dev, "no support for this device compiled in\n");
826 ret = -ENODEV;
827 goto out_gpio_free;
828 }
829
539 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 830 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
540 if (!res) { 831 if (!res) {
541 dev_err(&pdev->dev, "can't get platform resource\n"); 832 dev_err(&pdev->dev, "can't get platform resource\n");
@@ -567,24 +858,6 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
567 goto out_iounmap; 858 goto out_iounmap;
568 } 859 }
569 860
570 if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35()) {
571 spi_imx->intctrl = mx31_intctrl;
572 spi_imx->config = mx31_config;
573 spi_imx->trigger = mx31_trigger;
574 spi_imx->rx_available = mx31_rx_available;
575 } else if (cpu_is_mx27() || cpu_is_mx21()) {
576 spi_imx->intctrl = mx27_intctrl;
577 spi_imx->config = mx27_config;
578 spi_imx->trigger = mx27_trigger;
579 spi_imx->rx_available = mx27_rx_available;
580 } else if (cpu_is_mx1()) {
581 spi_imx->intctrl = mx1_intctrl;
582 spi_imx->config = mx1_config;
583 spi_imx->trigger = mx1_trigger;
584 spi_imx->rx_available = mx1_rx_available;
585 } else
586 BUG();
587
588 spi_imx->clk = clk_get(&pdev->dev, NULL); 861 spi_imx->clk = clk_get(&pdev->dev, NULL);
589 if (IS_ERR(spi_imx->clk)) { 862 if (IS_ERR(spi_imx->clk)) {
590 dev_err(&pdev->dev, "unable to get clock\n"); 863 dev_err(&pdev->dev, "unable to get clock\n");
@@ -595,15 +868,9 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
595 clk_enable(spi_imx->clk); 868 clk_enable(spi_imx->clk);
596 spi_imx->spi_clk = clk_get_rate(spi_imx->clk); 869 spi_imx->spi_clk = clk_get_rate(spi_imx->clk);
597 870
598 if (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27()) 871 spi_imx->devtype_data.reset(spi_imx);
599 writel(1, spi_imx->base + MXC_RESET);
600
601 /* drain receive buffer */
602 if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35())
603 while (readl(spi_imx->base + MX3_CSPISTAT) & MX3_CSPISTAT_RR)
604 readl(spi_imx->base + MXC_CSPIRXDATA);
605 872
606 spi_imx->intctrl(spi_imx, 0); 873 spi_imx->devtype_data.intctrl(spi_imx, 0);
607 874
608 ret = spi_bitbang_start(&spi_imx->bitbang); 875 ret = spi_bitbang_start(&spi_imx->bitbang);
609 if (ret) { 876 if (ret) {
@@ -668,6 +935,7 @@ static struct platform_driver spi_imx_driver = {
668 .name = DRIVER_NAME, 935 .name = DRIVER_NAME,
669 .owner = THIS_MODULE, 936 .owner = THIS_MODULE,
670 }, 937 },
938 .id_table = spi_imx_devtype,
671 .probe = spi_imx_probe, 939 .probe = spi_imx_probe,
672 .remove = __devexit_p(spi_imx_remove), 940 .remove = __devexit_p(spi_imx_remove),
673}; 941};
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-09 14:21:45 -0500