1 files changed, 81 insertions, 86 deletions

diff --git a/drivers/scsi/bfa/bfa_ioc_ct.c b/drivers/scsi/bfa/bfa_ioc_ct.c
index f21b82c5f64..115730c0aa7 100644
--- a/drivers/scsi/bfa/bfa_ioc_ct.c
+++ b/drivers/scsi/bfa/bfa_ioc_ct.c
@@ -34,7 +34,7 @@ static void bfa_ioc_ct_ownership_reset(struct bfa_ioc_s *ioc);
 
 struct bfa_ioc_hwif_s hwif_ct;
 
-/**
+/*
  * Called from bfa_ioc_attach() to map asic specific calls.
  */
 void
@@ -52,7 +52,7 @@ bfa_ioc_set_ct_hwif(struct bfa_ioc_s *ioc)
         ioc->ioc_hwif = &hwif_ct;
 }
 
-/**
+/*
  * Return true if firmware of current driver matches the running firmware.
  */
 static bfa_boolean_t
@@ -62,13 +62,13 @@ bfa_ioc_ct_firmware_lock(struct bfa_ioc_s *ioc)
         u32 usecnt;
         struct bfi_ioc_image_hdr_s fwhdr;
 
-        /**
+        /*
          * Firmware match check is relevant only for CNA.
          */
         if (!ioc->cna)
                 return BFA_TRUE;
 
-        /**
+        /*
          * If bios boot (flash based) -- do not increment usage count
          */
         if (bfa_cb_image_get_size(BFA_IOC_FWIMG_TYPE(ioc)) <
@@ -76,27 +76,27 @@ bfa_ioc_ct_firmware_lock(struct bfa_ioc_s *ioc)
                 return BFA_TRUE;
 
         bfa_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg);
-        usecnt = bfa_reg_read(ioc->ioc_regs.ioc_usage_reg);
+        usecnt = readl(ioc->ioc_regs.ioc_usage_reg);
 
-        /**
+        /*
          * If usage count is 0, always return TRUE.
          */
         if (usecnt == 0) {
-                bfa_reg_write(ioc->ioc_regs.ioc_usage_reg, 1);
+                writel(1, ioc->ioc_regs.ioc_usage_reg);
                 bfa_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
                 bfa_trc(ioc, usecnt);
                 return BFA_TRUE;
         }
 
-        ioc_fwstate = bfa_reg_read(ioc->ioc_regs.ioc_fwstate);
+        ioc_fwstate = readl(ioc->ioc_regs.ioc_fwstate);
         bfa_trc(ioc, ioc_fwstate);
 
-        /**
+        /*
          * Use count cannot be non-zero and chip in uninitialized state.
          */
         bfa_assert(ioc_fwstate != BFI_IOC_UNINIT);
 
-        /**
+        /*
          * Check if another driver with a different firmware is active
          */
         bfa_ioc_fwver_get(ioc, &fwhdr);
@@ -106,11 +106,11 @@ bfa_ioc_ct_firmware_lock(struct bfa_ioc_s *ioc)
                 return BFA_FALSE;
         }
 
-        /**
+        /*
          * Same firmware version. Increment the reference count.
          */
         usecnt++;
-        bfa_reg_write(ioc->ioc_regs.ioc_usage_reg, usecnt);
+        writel(usecnt, ioc->ioc_regs.ioc_usage_reg);
         bfa_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
         bfa_trc(ioc, usecnt);
         return BFA_TRUE;
@@ -121,50 +121,50 @@ bfa_ioc_ct_firmware_unlock(struct bfa_ioc_s *ioc)
 {
         u32 usecnt;
 
-        /**
+        /*
          * Firmware lock is relevant only for CNA.
          */
         if (!ioc->cna)
                 return;
 
-        /**
+        /*
          * If bios boot (flash based) -- do not decrement usage count
          */
         if (bfa_cb_image_get_size(BFA_IOC_FWIMG_TYPE(ioc)) <
                                                 BFA_IOC_FWIMG_MINSZ)
                 return;
 
-        /**
+        /*
          * decrement usage count
          */
         bfa_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg);
-        usecnt = bfa_reg_read(ioc->ioc_regs.ioc_usage_reg);
+        usecnt = readl(ioc->ioc_regs.ioc_usage_reg);
         bfa_assert(usecnt > 0);
 
         usecnt--;
-        bfa_reg_write(ioc->ioc_regs.ioc_usage_reg, usecnt);
+        writel(usecnt, ioc->ioc_regs.ioc_usage_reg);
         bfa_trc(ioc, usecnt);
 
         bfa_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
 }
 
-/**
+/*
  * Notify other functions on HB failure.
  */
 static void
 bfa_ioc_ct_notify_hbfail(struct bfa_ioc_s *ioc)
 {
         if (ioc->cna) {
-                bfa_reg_write(ioc->ioc_regs.ll_halt, __FW_INIT_HALT_P);
+                writel(__FW_INIT_HALT_P, ioc->ioc_regs.ll_halt);
                 /* Wait for halt to take effect */
-                bfa_reg_read(ioc->ioc_regs.ll_halt);
+                readl(ioc->ioc_regs.ll_halt);
         } else {
-                bfa_reg_write(ioc->ioc_regs.err_set, __PSS_ERR_STATUS_SET);
-                bfa_reg_read(ioc->ioc_regs.err_set);
+                writel(__PSS_ERR_STATUS_SET, ioc->ioc_regs.err_set);
+                readl(ioc->ioc_regs.err_set);
         }
 }
 
-/**
+/*
  * Host to LPU mailbox message addresses
  */
 static struct { u32 hfn_mbox, lpu_mbox, hfn_pgn; } iocreg_fnreg[] = {
@@ -174,7 +174,7 @@ static struct { u32 hfn_mbox, lpu_mbox, hfn_pgn; } iocreg_fnreg[] = {
         { HOSTFN3_LPU_MBOX0_8, LPU_HOSTFN3_MBOX0_8, HOST_PAGE_NUM_FN3 }
 };
 
-/**
+/*
  * Host <-> LPU mailbox command/status registers - port 0
  */
 static struct { u32 hfn, lpu; } iocreg_mbcmd_p0[] = {
@@ -184,7 +184,7 @@ static struct { u32 hfn, lpu; } iocreg_mbcmd_p0[] = {
         { HOSTFN3_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN3_MBOX0_CMD_STAT }
 };
 
-/**
+/*
  * Host <-> LPU mailbox command/status registers - port 1
  */
 static struct { u32 hfn, lpu; } iocreg_mbcmd_p1[] = {
@@ -197,7 +197,7 @@ static struct { u32 hfn, lpu; } iocreg_mbcmd_p1[] = {
 static void
 bfa_ioc_ct_reg_init(struct bfa_ioc_s *ioc)
 {
-        bfa_os_addr_t   rb;
+        void __iomem *rb;
         int             pcifn = bfa_ioc_pcifn(ioc);
 
         rb = bfa_ioc_bar0(ioc);
@@ -236,7 +236,7 @@ bfa_ioc_ct_reg_init(struct bfa_ioc_s *ioc)
         ioc->ioc_regs.ioc_init_sem_reg = (rb + HOST_SEM2_REG);
         ioc->ioc_regs.ioc_usage_reg = (rb + BFA_FW_USE_COUNT);
 
-        /**
+        /*
          * sram memory access
          */
         ioc->ioc_regs.smem_page_start = (rb + PSS_SMEM_PAGE_START);
@@ -248,7 +248,7 @@ bfa_ioc_ct_reg_init(struct bfa_ioc_s *ioc)
         ioc->ioc_regs.err_set = (rb + ERR_SET_REG);
 }
 
-/**
+/*
  * Initialize IOC to port mapping.
  */
 
@@ -256,13 +256,13 @@ bfa_ioc_ct_reg_init(struct bfa_ioc_s *ioc)
 static void
 bfa_ioc_ct_map_port(struct bfa_ioc_s *ioc)
 {
-        bfa_os_addr_t   rb = ioc->pcidev.pci_bar_kva;
+        void __iomem *rb = ioc->pcidev.pci_bar_kva;
         u32     r32;
 
-        /**
+        /*
          * For catapult, base port id on personality register and IOC type
          */
-        r32 = bfa_reg_read(rb + FNC_PERS_REG);
+        r32 = readl(rb + FNC_PERS_REG);
         r32 >>= FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc));
         ioc->port_id = (r32 & __F0_PORT_MAP_MK) >> __F0_PORT_MAP_SH;
 
@@ -270,22 +270,22 @@ bfa_ioc_ct_map_port(struct bfa_ioc_s *ioc)
         bfa_trc(ioc, ioc->port_id);
 }
 
-/**
+/*
  * Set interrupt mode for a function: INTX or MSIX
  */
 static void
 bfa_ioc_ct_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix)
 {
-        bfa_os_addr_t   rb = ioc->pcidev.pci_bar_kva;
+        void __iomem *rb = ioc->pcidev.pci_bar_kva;
         u32     r32, mode;
 
-        r32 = bfa_reg_read(rb + FNC_PERS_REG);
+        r32 = readl(rb + FNC_PERS_REG);
         bfa_trc(ioc, r32);
 
         mode = (r32 >> FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc))) &
                 __F0_INTX_STATUS;
 
-        /**
+        /*
          * If already in desired mode, do not change anything
          */
         if (!msix && mode)
@@ -300,10 +300,10 @@ bfa_ioc_ct_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix)
         r32 |= (mode << FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc)));
         bfa_trc(ioc, r32);
 
-        bfa_reg_write(rb + FNC_PERS_REG, r32);
+        writel(r32, rb + FNC_PERS_REG);
 }
 
-/**
+/*
  * Cleanup hw semaphore and usecnt registers
  */
 static void
@@ -312,7 +312,7 @@ bfa_ioc_ct_ownership_reset(struct bfa_ioc_s *ioc)
 
         if (ioc->cna) {
                 bfa_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg);
-                bfa_reg_write(ioc->ioc_regs.ioc_usage_reg, 0);
+                writel(0, ioc->ioc_regs.ioc_usage_reg);
                 bfa_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
         }
 
@@ -321,7 +321,7 @@ bfa_ioc_ct_ownership_reset(struct bfa_ioc_s *ioc)
          * before we clear it. If it is not locked, writing 1
          * will lock it instead of clearing it.
          */
-        bfa_reg_read(ioc->ioc_regs.ioc_sem_reg);
+        readl(ioc->ioc_regs.ioc_sem_reg);
         bfa_ioc_hw_sem_release(ioc);
 }
 
@@ -331,17 +331,17 @@ bfa_ioc_ct_ownership_reset(struct bfa_ioc_s *ioc)
  * Check the firmware state to know if pll_init has been completed already
  */
 bfa_boolean_t
-bfa_ioc_ct_pll_init_complete(bfa_os_addr_t rb)
+bfa_ioc_ct_pll_init_complete(void __iomem *rb)
 {
-        if ((bfa_reg_read(rb + BFA_IOC0_STATE_REG) == BFI_IOC_OP) ||
-          (bfa_reg_read(rb + BFA_IOC1_STATE_REG) == BFI_IOC_OP))
+        if ((readl(rb + BFA_IOC0_STATE_REG) == BFI_IOC_OP) ||
+          (readl(rb + BFA_IOC1_STATE_REG) == BFI_IOC_OP))
                 return BFA_TRUE;
 
         return BFA_FALSE;
 }
 
 bfa_status_t
-bfa_ioc_ct_pll_init(bfa_os_addr_t rb, bfa_boolean_t fcmode)
+bfa_ioc_ct_pll_init(void __iomem *rb, bfa_boolean_t fcmode)
 {
         u32     pll_sclk, pll_fclk, r32;
 
@@ -354,56 +354,51 @@ bfa_ioc_ct_pll_init(bfa_os_addr_t rb, bfa_boolean_t fcmode)
                 __APP_PLL_425_JITLMT0_1(3U) |
                 __APP_PLL_425_CNTLMT0_1(1U);
         if (fcmode) {
-                bfa_reg_write((rb + OP_MODE), 0);
-                bfa_reg_write((rb + ETH_MAC_SER_REG),
-                                __APP_EMS_CMLCKSEL |
-                                __APP_EMS_REFCKBUFEN2 |
-                                __APP_EMS_CHANNEL_SEL);
+                writel(0, (rb + OP_MODE));
+                writel(__APP_EMS_CMLCKSEL | __APP_EMS_REFCKBUFEN2 |
+                         __APP_EMS_CHANNEL_SEL, (rb + ETH_MAC_SER_REG));
         } else {
-                bfa_reg_write((rb + OP_MODE), __GLOBAL_FCOE_MODE);
-                bfa_reg_write((rb + ETH_MAC_SER_REG),
-                                __APP_EMS_REFCKBUFEN1);
+                writel(__GLOBAL_FCOE_MODE, (rb + OP_MODE));
+                writel(__APP_EMS_REFCKBUFEN1, (rb + ETH_MAC_SER_REG));
         }
-        bfa_reg_write((rb + BFA_IOC0_STATE_REG), BFI_IOC_UNINIT);
-        bfa_reg_write((rb + BFA_IOC1_STATE_REG), BFI_IOC_UNINIT);
-        bfa_reg_write((rb + HOSTFN0_INT_MSK), 0xffffffffU);
-        bfa_reg_write((rb + HOSTFN1_INT_MSK), 0xffffffffU);
-        bfa_reg_write((rb + HOSTFN0_INT_STATUS), 0xffffffffU);
-        bfa_reg_write((rb + HOSTFN1_INT_STATUS), 0xffffffffU);
-        bfa_reg_write((rb + HOSTFN0_INT_MSK), 0xffffffffU);
-        bfa_reg_write((rb + HOSTFN1_INT_MSK), 0xffffffffU);
-        bfa_reg_write(rb + APP_PLL_312_CTL_REG, pll_sclk |
-                __APP_PLL_312_LOGIC_SOFT_RESET);
-        bfa_reg_write(rb + APP_PLL_425_CTL_REG, pll_fclk |
-                __APP_PLL_425_LOGIC_SOFT_RESET);
-        bfa_reg_write(rb + APP_PLL_312_CTL_REG, pll_sclk |
-                __APP_PLL_312_LOGIC_SOFT_RESET | __APP_PLL_312_ENABLE);
-        bfa_reg_write(rb + APP_PLL_425_CTL_REG, pll_fclk |
-                __APP_PLL_425_LOGIC_SOFT_RESET | __APP_PLL_425_ENABLE);
-        bfa_reg_read(rb + HOSTFN0_INT_MSK);
-        bfa_os_udelay(2000);
-        bfa_reg_write((rb + HOSTFN0_INT_STATUS), 0xffffffffU);
-        bfa_reg_write((rb + HOSTFN1_INT_STATUS), 0xffffffffU);
-        bfa_reg_write(rb + APP_PLL_312_CTL_REG, pll_sclk |
-                __APP_PLL_312_ENABLE);
-        bfa_reg_write(rb + APP_PLL_425_CTL_REG, pll_fclk |
-                __APP_PLL_425_ENABLE);
+        writel(BFI_IOC_UNINIT, (rb + BFA_IOC0_STATE_REG));
+        writel(BFI_IOC_UNINIT, (rb + BFA_IOC1_STATE_REG));
+        writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
+        writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
+        writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
+        writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
+        writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
+        writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
+        writel(pll_sclk | __APP_PLL_312_LOGIC_SOFT_RESET,
+                        rb + APP_PLL_312_CTL_REG);
+        writel(pll_fclk | __APP_PLL_425_LOGIC_SOFT_RESET,
+                        rb + APP_PLL_425_CTL_REG);
+        writel(pll_sclk | __APP_PLL_312_LOGIC_SOFT_RESET | __APP_PLL_312_ENABLE,
+                        rb + APP_PLL_312_CTL_REG);
+        writel(pll_fclk | __APP_PLL_425_LOGIC_SOFT_RESET | __APP_PLL_425_ENABLE,
+                        rb + APP_PLL_425_CTL_REG);
+        readl(rb + HOSTFN0_INT_MSK);
+        udelay(2000);
+        writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
+        writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
+        writel(pll_sclk | __APP_PLL_312_ENABLE, rb + APP_PLL_312_CTL_REG);
+        writel(pll_fclk | __APP_PLL_425_ENABLE, rb + APP_PLL_425_CTL_REG);
         if (!fcmode) {
-                bfa_reg_write((rb + PMM_1T_RESET_REG_P0), __PMM_1T_RESET_P);
-                bfa_reg_write((rb + PMM_1T_RESET_REG_P1), __PMM_1T_RESET_P);
+                writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P0));
+                writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P1));
         }
-        r32 = bfa_reg_read((rb + PSS_CTL_REG));
+        r32 = readl((rb + PSS_CTL_REG));
         r32 &= ~__PSS_LMEM_RESET;
-        bfa_reg_write((rb + PSS_CTL_REG), r32);
-        bfa_os_udelay(1000);
+        writel(r32, (rb + PSS_CTL_REG));
+        udelay(1000);
         if (!fcmode) {
-                bfa_reg_write((rb + PMM_1T_RESET_REG_P0), 0);
-                bfa_reg_write((rb + PMM_1T_RESET_REG_P1), 0);
+                writel(0, (rb + PMM_1T_RESET_REG_P0));
+                writel(0, (rb + PMM_1T_RESET_REG_P1));
         }
 
-        bfa_reg_write((rb + MBIST_CTL_REG), __EDRAM_BISTR_START);
-        bfa_os_udelay(1000);
-        r32 = bfa_reg_read((rb + MBIST_STAT_REG));
-        bfa_reg_write((rb + MBIST_CTL_REG), 0);
+        writel(__EDRAM_BISTR_START, (rb + MBIST_CTL_REG));
+        udelay(1000);
+        r32 = readl((rb + MBIST_STAT_REG));
+        writel(0, (rb + MBIST_CTL_REG));
         return BFA_STATUS_OK;
 }